clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbc.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbc -emit-llvm %s -o - \
// RUN:     | FileCheck %s  -check-prefix=RV32ZBC

// RV32ZBC-LABEL: @clmul(
// RV32ZBC-NEXT:  entry:
// RV32ZBC-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
// RV32ZBC-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
// RV32ZBC-NEXT:    store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
// RV32ZBC-NEXT:    store i32 [[B:%.*]], i32* [[B_ADDR]], align 4
// RV32ZBC-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// RV32ZBC-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
// RV32ZBC-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[TMP0]], i32 [[TMP1]])
// RV32ZBC-NEXT:    ret i32 [[TMP2]]
//
long clmul(long a, long b) {
  return __builtin_riscv_clmul(a, b);
}

// RV32ZBC-LABEL: @clmulh(
// RV32ZBC-NEXT:  entry:
// RV32ZBC-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
// RV32ZBC-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
// RV32ZBC-NEXT:    store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
// RV32ZBC-NEXT:    store i32 [[B:%.*]], i32* [[B_ADDR]], align 4
// RV32ZBC-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// RV32ZBC-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
// RV32ZBC-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.clmulh.i32(i32 [[TMP0]], i32 [[TMP1]])
// RV32ZBC-NEXT:    ret i32 [[TMP2]]
//
long clmulh(long a, long b) {
  return __builtin_riscv_clmulh(a, b);
}

// RV32ZBC-LABEL: @clmulr(
// RV32ZBC-NEXT:  entry:
// RV32ZBC-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
// RV32ZBC-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
// RV32ZBC-NEXT:    store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
// RV32ZBC-NEXT:    store i32 [[B:%.*]], i32* [[B_ADDR]], align 4
// RV32ZBC-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// RV32ZBC-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
// RV32ZBC-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.clmulr.i32(i32 [[TMP0]], i32 [[TMP1]])
// RV32ZBC-NEXT:    ret i32 [[TMP2]]
//
long clmulr(long a, long b) {
  return __builtin_riscv_clmulr(a, b);
}