llvm/test/CodeGen/AArch64/fp16-v4-instructions.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=aarch64 -mattr=-fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-CVT,CHECK-CVT-SD
; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16,CHECK-FP16-SD
; RUN: llc < %s -mtriple=aarch64 -mattr=-fullfp16 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-CVT,CHECK-CVT-GI
; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-FP16,CHECK-FP16-GI

define <4 x half> @add_h(<4 x half> %a, <4 x half> %b) {
; CHECK-CVT-SD-LABEL: add_h:
; CHECK-CVT-SD:       // %bb.0: // %entry
; CHECK-CVT-SD-NEXT:    fcvtl v1.4s, v1.4h
; CHECK-CVT-SD-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-SD-NEXT:    fadd v0.4s, v0.4s, v1.4s
; CHECK-CVT-SD-NEXT:    fcvtn v0.4h, v0.4s
; CHECK-CVT-SD-NEXT:    ret
;
; CHECK-FP16-LABEL: add_h:
; CHECK-FP16:       // %bb.0: // %entry
; CHECK-FP16-NEXT:    fadd v0.4h, v0.4h, v1.4h
; CHECK-FP16-NEXT:    ret
;
; CHECK-CVT-GI-LABEL: add_h:
; CHECK-CVT-GI:       // %bb.0: // %entry
; CHECK-CVT-GI-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-GI-NEXT:    fcvtl v1.4s, v1.4h
; CHECK-CVT-GI-NEXT:    fadd v0.4s, v0.4s, v1.4s
; CHECK-CVT-GI-NEXT:    fcvtn v0.4h, v0.4s
; CHECK-CVT-GI-NEXT:    ret
entry:

  %0 = fadd <4 x half> %a, %b
  ret <4 x half> %0
}

define <4 x half> @build_h4(<4 x half> %a) {
; CHECK-CVT-SD-LABEL: build_h4:
; CHECK-CVT-SD:       // %bb.0: // %entry
; CHECK-CVT-SD-NEXT:    mov w8, #15565 // =0x3ccd
; CHECK-CVT-SD-NEXT:    dup v0.4h, w8
; CHECK-CVT-SD-NEXT:    ret
;
; CHECK-FP16-SD-LABEL: build_h4:
; CHECK-FP16-SD:       // %bb.0: // %entry
; CHECK-FP16-SD-NEXT:    mov w8, #15565 // =0x3ccd
; CHECK-FP16-SD-NEXT:    dup v0.4h, w8
; CHECK-FP16-SD-NEXT:    ret
;
; CHECK-CVT-GI-LABEL: build_h4:
; CHECK-CVT-GI:       // %bb.0: // %entry
; CHECK-CVT-GI-NEXT:    adrp x8, .LCPI1_0
; CHECK-CVT-GI-NEXT:    ldr d0, [x8, :lo12:.LCPI1_0]
; CHECK-CVT-GI-NEXT:    ret
;
; CHECK-FP16-GI-LABEL: build_h4:
; CHECK-FP16-GI:       // %bb.0: // %entry
; CHECK-FP16-GI-NEXT:    adrp x8, .LCPI1_0
; CHECK-FP16-GI-NEXT:    ldr d0, [x8, :lo12:.LCPI1_0]
; CHECK-FP16-GI-NEXT:    ret
entry:
  ret <4 x half> <half 0xH3CCD, half 0xH3CCD, half 0xH3CCD, half 0xH3CCD>
}

define <4 x half> @sub_h(<4 x half> %a, <4 x half> %b) {
; CHECK-CVT-SD-LABEL: sub_h:
; CHECK-CVT-SD:       // %bb.0: // %entry
; CHECK-CVT-SD-NEXT:    fcvtl v1.4s, v1.4h
; CHECK-CVT-SD-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-SD-NEXT:    fsub v0.4s, v0.4s, v1.4s
; CHECK-CVT-SD-NEXT:    fcvtn v0.4h, v0.4s
; CHECK-CVT-SD-NEXT:    ret
;
; CHECK-FP16-LABEL: sub_h:
; CHECK-FP16:       // %bb.0: // %entry
; CHECK-FP16-NEXT:    fsub v0.4h, v0.4h, v1.4h
; CHECK-FP16-NEXT:    ret
;
; CHECK-CVT-GI-LABEL: sub_h:
; CHECK-CVT-GI:       // %bb.0: // %entry
; CHECK-CVT-GI-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-GI-NEXT:    fcvtl v1.4s, v1.4h
; CHECK-CVT-GI-NEXT:    fsub v0.4s, v0.4s, v1.4s
; CHECK-CVT-GI-NEXT:    fcvtn v0.4h, v0.4s
; CHECK-CVT-GI-NEXT:    ret
entry:

  %0 = fsub <4 x half> %a, %b
  ret <4 x half> %0
}

define <4 x half> @mul_h(<4 x half> %a, <4 x half> %b) {
; CHECK-CVT-SD-LABEL: mul_h:
; CHECK-CVT-SD:       // %bb.0: // %entry
; CHECK-CVT-SD-NEXT:    fcvtl v1.4s, v1.4h
; CHECK-CVT-SD-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-SD-NEXT:    fmul v0.4s, v0.4s, v1.4s
; CHECK-CVT-SD-NEXT:    fcvtn v0.4h, v0.4s
; CHECK-CVT-SD-NEXT:    ret
;
; CHECK-FP16-LABEL: mul_h:
; CHECK-FP16:       // %bb.0: // %entry
; CHECK-FP16-NEXT:    fmul v0.4h, v0.4h, v1.4h
; CHECK-FP16-NEXT:    ret
;
; CHECK-CVT-GI-LABEL: mul_h:
; CHECK-CVT-GI:       // %bb.0: // %entry
; CHECK-CVT-GI-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-GI-NEXT:    fcvtl v1.4s, v1.4h
; CHECK-CVT-GI-NEXT:    fmul v0.4s, v0.4s, v1.4s
; CHECK-CVT-GI-NEXT:    fcvtn v0.4h, v0.4s
; CHECK-CVT-GI-NEXT:    ret
entry:

  %0 = fmul <4 x half> %a, %b
  ret <4 x half> %0
}

define <4 x half> @div_h(<4 x half> %a, <4 x half> %b) {
; CHECK-CVT-SD-LABEL: div_h:
; CHECK-CVT-SD:       // %bb.0: // %entry
; CHECK-CVT-SD-NEXT:    fcvtl v1.4s, v1.4h
; CHECK-CVT-SD-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-SD-NEXT:    fdiv v0.4s, v0.4s, v1.4s
; CHECK-CVT-SD-NEXT:    fcvtn v0.4h, v0.4s
; CHECK-CVT-SD-NEXT:    ret
;
; CHECK-FP16-LABEL: div_h:
; CHECK-FP16:       // %bb.0: // %entry
; CHECK-FP16-NEXT:    fdiv v0.4h, v0.4h, v1.4h
; CHECK-FP16-NEXT:    ret
;
; CHECK-CVT-GI-LABEL: div_h:
; CHECK-CVT-GI:       // %bb.0: // %entry
; CHECK-CVT-GI-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-GI-NEXT:    fcvtl v1.4s, v1.4h
; CHECK-CVT-GI-NEXT:    fdiv v0.4s, v0.4s, v1.4s
; CHECK-CVT-GI-NEXT:    fcvtn v0.4h, v0.4s
; CHECK-CVT-GI-NEXT:    ret
entry:

  %0 = fdiv <4 x half> %a, %b
  ret <4 x half> %0
}

define <4 x half> @load_h(ptr %a) {
; CHECK-LABEL: load_h:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    ldr d0, [x0]
; CHECK-NEXT:    ret
entry:
  %0 = load <4 x half>, ptr %a, align 4
  ret <4 x half> %0
}

define void @store_h(ptr %a, <4 x half> %b) {
; CHECK-LABEL: store_h:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    str d0, [x0]
; CHECK-NEXT:    ret
entry:
  store <4 x half> %b, ptr %a, align 4
  ret void
}

define <4 x half> @s_to_h(<4 x float> %a) {
; CHECK-LABEL: s_to_h:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtn v0.4h, v0.4s
; CHECK-NEXT:    ret
  %1 = fptrunc <4 x float> %a to <4 x half>
  ret <4 x half> %1
}

define <4 x half> @d_to_h(<4 x double> %a) {
; CHECK-CVT-SD-LABEL: d_to_h:
; CHECK-CVT-SD:       // %bb.0:
; CHECK-CVT-SD-NEXT:    fcvtxn v0.2s, v0.2d
; CHECK-CVT-SD-NEXT:    fcvtxn2 v0.4s, v1.2d
; CHECK-CVT-SD-NEXT:    fcvtn v0.4h, v0.4s
; CHECK-CVT-SD-NEXT:    ret
;
; CHECK-FP16-SD-LABEL: d_to_h:
; CHECK-FP16-SD:       // %bb.0:
; CHECK-FP16-SD-NEXT:    fcvtxn v0.2s, v0.2d
; CHECK-FP16-SD-NEXT:    fcvtxn2 v0.4s, v1.2d
; CHECK-FP16-SD-NEXT:    fcvtn v0.4h, v0.4s
; CHECK-FP16-SD-NEXT:    ret
;
; CHECK-CVT-GI-LABEL: d_to_h:
; CHECK-CVT-GI:       // %bb.0:
; CHECK-CVT-GI-NEXT:    mov d2, v0.d[1]
; CHECK-CVT-GI-NEXT:    fcvt h0, d0
; CHECK-CVT-GI-NEXT:    mov d3, v1.d[1]
; CHECK-CVT-GI-NEXT:    fcvt h1, d1
; CHECK-CVT-GI-NEXT:    fcvt h2, d2
; CHECK-CVT-GI-NEXT:    mov v0.h[1], v2.h[0]
; CHECK-CVT-GI-NEXT:    fcvt h2, d3
; CHECK-CVT-GI-NEXT:    mov v0.h[2], v1.h[0]
; CHECK-CVT-GI-NEXT:    mov v0.h[3], v2.h[0]
; CHECK-CVT-GI-NEXT:    // kill: def $d0 killed $d0 killed $q0
; CHECK-CVT-GI-NEXT:    ret
;
; CHECK-FP16-GI-LABEL: d_to_h:
; CHECK-FP16-GI:       // %bb.0:
; CHECK-FP16-GI-NEXT:    mov d2, v0.d[1]
; CHECK-FP16-GI-NEXT:    fcvt h0, d0
; CHECK-FP16-GI-NEXT:    mov d3, v1.d[1]
; CHECK-FP16-GI-NEXT:    fcvt h1, d1
; CHECK-FP16-GI-NEXT:    fcvt h2, d2
; CHECK-FP16-GI-NEXT:    mov v0.h[1], v2.h[0]
; CHECK-FP16-GI-NEXT:    fcvt h2, d3
; CHECK-FP16-GI-NEXT:    mov v0.h[2], v1.h[0]
; CHECK-FP16-GI-NEXT:    mov v0.h[3], v2.h[0]
; CHECK-FP16-GI-NEXT:    // kill: def $d0 killed $d0 killed $q0
; CHECK-FP16-GI-NEXT:    ret
  %1 = fptrunc <4 x double> %a to <4 x half>
  ret <4 x half> %1
}

define <4 x float> @h_to_s(<4 x half> %a) {
; CHECK-LABEL: h_to_s:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-NEXT:    ret
  %1 = fpext <4 x half> %a to <4 x float>
  ret <4 x float> %1
}

define <4 x double> @h_to_d(<4 x half> %a) {
; CHECK-CVT-SD-LABEL: h_to_d:
; CHECK-CVT-SD:       // %bb.0:
; CHECK-CVT-SD-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-SD-NEXT:    fcvtl2 v1.2d, v0.4s
; CHECK-CVT-SD-NEXT:    fcvtl v0.2d, v0.2s
; CHECK-CVT-SD-NEXT:    ret
;
; CHECK-FP16-SD-LABEL: h_to_d:
; CHECK-FP16-SD:       // %bb.0:
; CHECK-FP16-SD-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-FP16-SD-NEXT:    fcvtl2 v1.2d, v0.4s
; CHECK-FP16-SD-NEXT:    fcvtl v0.2d, v0.2s
; CHECK-FP16-SD-NEXT:    ret
;
; CHECK-CVT-GI-LABEL: h_to_d:
; CHECK-CVT-GI:       // %bb.0:
; CHECK-CVT-GI-NEXT:    // kill: def $d0 killed $d0 def $q0
; CHECK-CVT-GI-NEXT:    mov h1, v0.h[1]
; CHECK-CVT-GI-NEXT:    mov h2, v0.h[2]
; CHECK-CVT-GI-NEXT:    mov h3, v0.h[3]
; CHECK-CVT-GI-NEXT:    fcvt d0, h0
; CHECK-CVT-GI-NEXT:    fcvt d4, h1
; CHECK-CVT-GI-NEXT:    fcvt d1, h2
; CHECK-CVT-GI-NEXT:    fcvt d2, h3
; CHECK-CVT-GI-NEXT:    mov v0.d[1], v4.d[0]
; CHECK-CVT-GI-NEXT:    mov v1.d[1], v2.d[0]
; CHECK-CVT-GI-NEXT:    ret
;
; CHECK-FP16-GI-LABEL: h_to_d:
; CHECK-FP16-GI:       // %bb.0:
; CHECK-FP16-GI-NEXT:    // kill: def $d0 killed $d0 def $q0
; CHECK-FP16-GI-NEXT:    mov h1, v0.h[1]
; CHECK-FP16-GI-NEXT:    mov h2, v0.h[2]
; CHECK-FP16-GI-NEXT:    mov h3, v0.h[3]
; CHECK-FP16-GI-NEXT:    fcvt d0, h0
; CHECK-FP16-GI-NEXT:    fcvt d4, h1
; CHECK-FP16-GI-NEXT:    fcvt d1, h2
; CHECK-FP16-GI-NEXT:    fcvt d2, h3
; CHECK-FP16-GI-NEXT:    mov v0.d[1], v4.d[0]
; CHECK-FP16-GI-NEXT:    mov v1.d[1], v2.d[0]
; CHECK-FP16-GI-NEXT:    ret
  %1 = fpext <4 x half> %a to <4 x double>
  ret <4 x double> %1
}

define <4 x half> @bitcast_i_to_h(float, <4 x i16> %a) {
; CHECK-LABEL: bitcast_i_to_h:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fmov d0, d1
; CHECK-NEXT:    ret
  %2 = bitcast <4 x i16> %a to <4 x half>
  ret <4 x half> %2
}

define <4 x i16> @bitcast_h_to_i(float, <4 x half> %a) {
; CHECK-LABEL: bitcast_h_to_i:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fmov d0, d1
; CHECK-NEXT:    ret
  %2 = bitcast <4 x half> %a to <4 x i16>
  ret <4 x i16> %2
}

define <4 x half> @sitofp_i8(<4 x i8> %a) #0 {
; CHECK-CVT-SD-LABEL: sitofp_i8:
; CHECK-CVT-SD:       // %bb.0:
; CHECK-CVT-SD-NEXT:    shl v0.4h, v0.4h, #8
; CHECK-CVT-SD-NEXT:    sshr v0.4h, v0.4h, #8
; CHECK-CVT-SD-NEXT:    sshll v0.4s, v0.4h, #0
; CHECK-CVT-SD-NEXT:    scvtf v0.4s, v0.4s
; CHECK-CVT-SD-NEXT:    fcvtn v0.4h, v0.4s
; CHECK-CVT-SD-NEXT:    ret
;
; CHECK-FP16-LABEL: sitofp_i8:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    shl v0.4h, v0.4h, #8
; CHECK-FP16-NEXT:    sshr v0.4h, v0.4h, #8
; CHECK-FP16-NEXT:    scvtf v0.4h, v0.4h
; CHECK-FP16-NEXT:    ret
;
; CHECK-CVT-GI-LABEL: sitofp_i8:
; CHECK-CVT-GI:       // %bb.0:
; CHECK-CVT-GI-NEXT:    ushll v0.4s, v0.4h, #0
; CHECK-CVT-GI-NEXT:    shl v0.4s, v0.4s, #24
; CHECK-CVT-GI-NEXT:    sshr v0.4s, v0.4s, #24
; CHECK-CVT-GI-NEXT:    scvtf v0.4s, v0.4s
; CHECK-CVT-GI-NEXT:    fcvtn v0.4h, v0.4s
; CHECK-CVT-GI-NEXT:    ret
  %1 = sitofp <4 x i8> %a to <4 x half>
  ret <4 x half> %1
}

define <4 x half> @sitofp_i16(<4 x i16> %a) #0 {
; CHECK-CVT-LABEL: sitofp_i16:
; CHECK-CVT:       // %bb.0:
; CHECK-CVT-NEXT:    sshll v0.4s, v0.4h, #0
; CHECK-CVT-NEXT:    scvtf v0.4s, v0.4s
; CHECK-CVT-NEXT:    fcvtn v0.4h, v0.4s
; CHECK-CVT-NEXT:    ret
;
; CHECK-FP16-LABEL: sitofp_i16:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    scvtf v0.4h, v0.4h
; CHECK-FP16-NEXT:    ret
  %1 = sitofp <4 x i16> %a to <4 x half>
  ret <4 x half> %1
}


define <4 x half> @sitofp_i32(<4 x i32> %a) #0 {
; CHECK-LABEL: sitofp_i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    scvtf v0.4s, v0.4s
; CHECK-NEXT:    fcvtn v0.4h, v0.4s
; CHECK-NEXT:    ret
  %1 = sitofp <4 x i32> %a to <4 x half>
  ret <4 x half> %1
}


define <4 x half> @sitofp_i64(<4 x i64> %a) #0 {
; CHECK-LABEL: sitofp_i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    scvtf v0.2d, v0.2d
; CHECK-NEXT:    scvtf v1.2d, v1.2d
; CHECK-NEXT:    fcvtn v0.2s, v0.2d
; CHECK-NEXT:    fcvtn2 v0.4s, v1.2d
; CHECK-NEXT:    fcvtn v0.4h, v0.4s
; CHECK-NEXT:    ret
  %1 = sitofp <4 x i64> %a to <4 x half>
  ret <4 x half> %1
}

define <4 x half> @uitofp_i8(<4 x i8> %a) #0 {
; CHECK-CVT-SD-LABEL: uitofp_i8:
; CHECK-CVT-SD:       // %bb.0:
; CHECK-CVT-SD-NEXT:    bic v0.4h, #255, lsl #8
; CHECK-CVT-SD-NEXT:    ushll v0.4s, v0.4h, #0
; CHECK-CVT-SD-NEXT:    ucvtf v0.4s, v0.4s
; CHECK-CVT-SD-NEXT:    fcvtn v0.4h, v0.4s
; CHECK-CVT-SD-NEXT:    ret
;
; CHECK-FP16-SD-LABEL: uitofp_i8:
; CHECK-FP16-SD:       // %bb.0:
; CHECK-FP16-SD-NEXT:    bic v0.4h, #255, lsl #8
; CHECK-FP16-SD-NEXT:    ucvtf v0.4h, v0.4h
; CHECK-FP16-SD-NEXT:    ret
;
; CHECK-CVT-GI-LABEL: uitofp_i8:
; CHECK-CVT-GI:       // %bb.0:
; CHECK-CVT-GI-NEXT:    movi v1.2d, #0x0000ff000000ff
; CHECK-CVT-GI-NEXT:    ushll v0.4s, v0.4h, #0
; CHECK-CVT-GI-NEXT:    and v0.16b, v0.16b, v1.16b
; CHECK-CVT-GI-NEXT:    ucvtf v0.4s, v0.4s
; CHECK-CVT-GI-NEXT:    fcvtn v0.4h, v0.4s
; CHECK-CVT-GI-NEXT:    ret
;
; CHECK-FP16-GI-LABEL: uitofp_i8:
; CHECK-FP16-GI:       // %bb.0:
; CHECK-FP16-GI-NEXT:    movi d1, #0xff00ff00ff00ff
; CHECK-FP16-GI-NEXT:    and v0.8b, v0.8b, v1.8b
; CHECK-FP16-GI-NEXT:    ucvtf v0.4h, v0.4h
; CHECK-FP16-GI-NEXT:    ret
  %1 = uitofp <4 x i8> %a to <4 x half>
  ret <4 x half> %1
}


define <4 x half> @uitofp_i16(<4 x i16> %a) #0 {
; CHECK-CVT-LABEL: uitofp_i16:
; CHECK-CVT:       // %bb.0:
; CHECK-CVT-NEXT:    ushll v0.4s, v0.4h, #0
; CHECK-CVT-NEXT:    ucvtf v0.4s, v0.4s
; CHECK-CVT-NEXT:    fcvtn v0.4h, v0.4s
; CHECK-CVT-NEXT:    ret
;
; CHECK-FP16-LABEL: uitofp_i16:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    ucvtf v0.4h, v0.4h
; CHECK-FP16-NEXT:    ret
  %1 = uitofp <4 x i16> %a to <4 x half>
  ret <4 x half> %1
}


define <4 x half> @uitofp_i32(<4 x i32> %a) #0 {
; CHECK-LABEL: uitofp_i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ucvtf v0.4s, v0.4s
; CHECK-NEXT:    fcvtn v0.4h, v0.4s
; CHECK-NEXT:    ret
  %1 = uitofp <4 x i32> %a to <4 x half>
  ret <4 x half> %1
}


define <4 x half> @uitofp_i64(<4 x i64> %a) #0 {
; CHECK-LABEL: uitofp_i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ucvtf v0.2d, v0.2d
; CHECK-NEXT:    ucvtf v1.2d, v1.2d
; CHECK-NEXT:    fcvtn v0.2s, v0.2d
; CHECK-NEXT:    fcvtn2 v0.4s, v1.2d
; CHECK-NEXT:    fcvtn v0.4h, v0.4s
; CHECK-NEXT:    ret
  %1 = uitofp <4 x i64> %a to <4 x half>
  ret <4 x half> %1
}

define void @test_insert_at_zero(half %a, ptr %b) #0 {
; CHECK-LABEL: test_insert_at_zero:
; CHECK:       // %bb.0:
; CHECK-NEXT:    // kill: def $h0 killed $h0 def $d0
; CHECK-NEXT:    str d0, [x0]
; CHECK-NEXT:    ret
  %1 = insertelement <4 x half> undef, half %a, i64 0
  store <4 x half> %1, ptr %b, align 4
  ret void
}

define <4 x i8> @fptosi_i8(<4 x half> %a) #0 {
; CHECK-CVT-LABEL: fptosi_i8:
; CHECK-CVT:       // %bb.0:
; CHECK-CVT-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-NEXT:    fcvtzs v0.4s, v0.4s
; CHECK-CVT-NEXT:    xtn v0.4h, v0.4s
; CHECK-CVT-NEXT:    ret
;
; CHECK-FP16-LABEL: fptosi_i8:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    fcvtzs v0.4h, v0.4h
; CHECK-FP16-NEXT:    ret
  %1 = fptosi<4 x half> %a to <4 x i8>
  ret <4 x i8> %1
}

define <4 x i16> @fptosi_i16(<4 x half> %a) #0 {
; CHECK-CVT-LABEL: fptosi_i16:
; CHECK-CVT:       // %bb.0:
; CHECK-CVT-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-NEXT:    fcvtzs v0.4s, v0.4s
; CHECK-CVT-NEXT:    xtn v0.4h, v0.4s
; CHECK-CVT-NEXT:    ret
;
; CHECK-FP16-LABEL: fptosi_i16:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    fcvtzs v0.4h, v0.4h
; CHECK-FP16-NEXT:    ret
  %1 = fptosi<4 x half> %a to <4 x i16>
  ret <4 x i16> %1
}

define <4 x i8> @fptoui_i8(<4 x half> %a) #0 {
; CHECK-CVT-SD-LABEL: fptoui_i8:
; CHECK-CVT-SD:       // %bb.0:
; CHECK-CVT-SD-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-SD-NEXT:    fcvtzs v0.4s, v0.4s
; CHECK-CVT-SD-NEXT:    xtn v0.4h, v0.4s
; CHECK-CVT-SD-NEXT:    ret
;
; CHECK-FP16-SD-LABEL: fptoui_i8:
; CHECK-FP16-SD:       // %bb.0:
; CHECK-FP16-SD-NEXT:    fcvtzs v0.4h, v0.4h
; CHECK-FP16-SD-NEXT:    ret
;
; CHECK-CVT-GI-LABEL: fptoui_i8:
; CHECK-CVT-GI:       // %bb.0:
; CHECK-CVT-GI-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-GI-NEXT:    fcvtzu v0.4s, v0.4s
; CHECK-CVT-GI-NEXT:    xtn v0.4h, v0.4s
; CHECK-CVT-GI-NEXT:    ret
;
; CHECK-FP16-GI-LABEL: fptoui_i8:
; CHECK-FP16-GI:       // %bb.0:
; CHECK-FP16-GI-NEXT:    fcvtzu v0.4h, v0.4h
; CHECK-FP16-GI-NEXT:    ret
; NOTE: fcvtzs selected here because the xtn shaves the sign bit
  %1 = fptoui<4 x half> %a to <4 x i8>
  ret <4 x i8> %1
}

define <4 x i16> @fptoui_i16(<4 x half> %a) #0 {
; CHECK-CVT-LABEL: fptoui_i16:
; CHECK-CVT:       // %bb.0:
; CHECK-CVT-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-NEXT:    fcvtzu v0.4s, v0.4s
; CHECK-CVT-NEXT:    xtn v0.4h, v0.4s
; CHECK-CVT-NEXT:    ret
;
; CHECK-FP16-LABEL: fptoui_i16:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    fcvtzu v0.4h, v0.4h
; CHECK-FP16-NEXT:    ret
  %1 = fptoui<4 x half> %a to <4 x i16>
  ret <4 x i16> %1
}

define <4 x i1> @test_fcmp_une(<4 x half> %a, <4 x half> %b) #0 {
; CHECK-CVT-SD-LABEL: test_fcmp_une:
; CHECK-CVT-SD:       // %bb.0:
; CHECK-CVT-SD-NEXT:    fcvtl v1.4s, v1.4h
; CHECK-CVT-SD-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-SD-NEXT:    fcmeq v0.4s, v0.4s, v1.4s
; CHECK-CVT-SD-NEXT:    mvn v0.16b, v0.16b
; CHECK-CVT-SD-NEXT:    xtn v0.4h, v0.4s
; CHECK-CVT-SD-NEXT:    ret
;
; CHECK-FP16-LABEL: test_fcmp_une:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    fcmeq v0.4h, v0.4h, v1.4h
; CHECK-FP16-NEXT:    mvn v0.8b, v0.8b
; CHECK-FP16-NEXT:    ret
;
; CHECK-CVT-GI-LABEL: test_fcmp_une:
; CHECK-CVT-GI:       // %bb.0:
; CHECK-CVT-GI-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-GI-NEXT:    fcvtl v1.4s, v1.4h
; CHECK-CVT-GI-NEXT:    fcmeq v0.4s, v0.4s, v1.4s
; CHECK-CVT-GI-NEXT:    mvn v0.16b, v0.16b
; CHECK-CVT-GI-NEXT:    xtn v0.4h, v0.4s
; CHECK-CVT-GI-NEXT:    ret

  %1 = fcmp une <4 x half> %a, %b
  ret <4 x i1> %1
}

define <4 x i1> @test_fcmp_ueq(<4 x half> %a, <4 x half> %b) #0 {
; CHECK-CVT-SD-LABEL: test_fcmp_ueq:
; CHECK-CVT-SD:       // %bb.0:
; CHECK-CVT-SD-NEXT:    fcvtl v1.4s, v1.4h
; CHECK-CVT-SD-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-SD-NEXT:    fcmgt v2.4s, v0.4s, v1.4s
; CHECK-CVT-SD-NEXT:    fcmgt v0.4s, v1.4s, v0.4s
; CHECK-CVT-SD-NEXT:    orr v0.16b, v0.16b, v2.16b
; CHECK-CVT-SD-NEXT:    xtn v0.4h, v0.4s
; CHECK-CVT-SD-NEXT:    mvn v0.8b, v0.8b
; CHECK-CVT-SD-NEXT:    ret
;
; CHECK-FP16-LABEL: test_fcmp_ueq:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    fcmgt v2.4h, v0.4h, v1.4h
; CHECK-FP16-NEXT:    fcmgt v0.4h, v1.4h, v0.4h
; CHECK-FP16-NEXT:    orr v0.8b, v0.8b, v2.8b
; CHECK-FP16-NEXT:    mvn v0.8b, v0.8b
; CHECK-FP16-NEXT:    ret
;
; CHECK-CVT-GI-LABEL: test_fcmp_ueq:
; CHECK-CVT-GI:       // %bb.0:
; CHECK-CVT-GI-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-GI-NEXT:    fcvtl v1.4s, v1.4h
; CHECK-CVT-GI-NEXT:    fcmgt v2.4s, v0.4s, v1.4s
; CHECK-CVT-GI-NEXT:    fcmgt v0.4s, v1.4s, v0.4s
; CHECK-CVT-GI-NEXT:    orr v0.16b, v0.16b, v2.16b
; CHECK-CVT-GI-NEXT:    mvn v0.16b, v0.16b
; CHECK-CVT-GI-NEXT:    xtn v0.4h, v0.4s
; CHECK-CVT-GI-NEXT:    ret

  %1 = fcmp ueq <4 x half> %a, %b
  ret <4 x i1> %1
}

define <4 x i1> @test_fcmp_ugt(<4 x half> %a, <4 x half> %b) #0 {
; CHECK-CVT-SD-LABEL: test_fcmp_ugt:
; CHECK-CVT-SD:       // %bb.0:
; CHECK-CVT-SD-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-SD-NEXT:    fcvtl v1.4s, v1.4h
; CHECK-CVT-SD-NEXT:    fcmge v0.4s, v1.4s, v0.4s
; CHECK-CVT-SD-NEXT:    xtn v0.4h, v0.4s
; CHECK-CVT-SD-NEXT:    mvn v0.8b, v0.8b
; CHECK-CVT-SD-NEXT:    ret
;
; CHECK-FP16-LABEL: test_fcmp_ugt:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    fcmge v0.4h, v1.4h, v0.4h
; CHECK-FP16-NEXT:    mvn v0.8b, v0.8b
; CHECK-FP16-NEXT:    ret
;
; CHECK-CVT-GI-LABEL: test_fcmp_ugt:
; CHECK-CVT-GI:       // %bb.0:
; CHECK-CVT-GI-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-GI-NEXT:    fcvtl v1.4s, v1.4h
; CHECK-CVT-GI-NEXT:    fcmge v0.4s, v1.4s, v0.4s
; CHECK-CVT-GI-NEXT:    mvn v0.16b, v0.16b
; CHECK-CVT-GI-NEXT:    xtn v0.4h, v0.4s
; CHECK-CVT-GI-NEXT:    ret

  %1 = fcmp ugt <4 x half> %a, %b
  ret <4 x i1> %1
}

define <4 x i1> @test_fcmp_uge(<4 x half> %a, <4 x half> %b) #0 {
; CHECK-CVT-SD-LABEL: test_fcmp_uge:
; CHECK-CVT-SD:       // %bb.0:
; CHECK-CVT-SD-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-SD-NEXT:    fcvtl v1.4s, v1.4h
; CHECK-CVT-SD-NEXT:    fcmgt v0.4s, v1.4s, v0.4s
; CHECK-CVT-SD-NEXT:    xtn v0.4h, v0.4s
; CHECK-CVT-SD-NEXT:    mvn v0.8b, v0.8b
; CHECK-CVT-SD-NEXT:    ret
;
; CHECK-FP16-LABEL: test_fcmp_uge:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    fcmgt v0.4h, v1.4h, v0.4h
; CHECK-FP16-NEXT:    mvn v0.8b, v0.8b
; CHECK-FP16-NEXT:    ret
;
; CHECK-CVT-GI-LABEL: test_fcmp_uge:
; CHECK-CVT-GI:       // %bb.0:
; CHECK-CVT-GI-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-GI-NEXT:    fcvtl v1.4s, v1.4h
; CHECK-CVT-GI-NEXT:    fcmgt v0.4s, v1.4s, v0.4s
; CHECK-CVT-GI-NEXT:    mvn v0.16b, v0.16b
; CHECK-CVT-GI-NEXT:    xtn v0.4h, v0.4s
; CHECK-CVT-GI-NEXT:    ret

  %1 = fcmp uge <4 x half> %a, %b
  ret <4 x i1> %1
}

define <4 x i1> @test_fcmp_ult(<4 x half> %a, <4 x half> %b) #0 {
; CHECK-CVT-SD-LABEL: test_fcmp_ult:
; CHECK-CVT-SD:       // %bb.0:
; CHECK-CVT-SD-NEXT:    fcvtl v1.4s, v1.4h
; CHECK-CVT-SD-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-SD-NEXT:    fcmge v0.4s, v0.4s, v1.4s
; CHECK-CVT-SD-NEXT:    xtn v0.4h, v0.4s
; CHECK-CVT-SD-NEXT:    mvn v0.8b, v0.8b
; CHECK-CVT-SD-NEXT:    ret
;
; CHECK-FP16-LABEL: test_fcmp_ult:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    fcmge v0.4h, v0.4h, v1.4h
; CHECK-FP16-NEXT:    mvn v0.8b, v0.8b
; CHECK-FP16-NEXT:    ret
;
; CHECK-CVT-GI-LABEL: test_fcmp_ult:
; CHECK-CVT-GI:       // %bb.0:
; CHECK-CVT-GI-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-GI-NEXT:    fcvtl v1.4s, v1.4h
; CHECK-CVT-GI-NEXT:    fcmge v0.4s, v0.4s, v1.4s
; CHECK-CVT-GI-NEXT:    mvn v0.16b, v0.16b
; CHECK-CVT-GI-NEXT:    xtn v0.4h, v0.4s
; CHECK-CVT-GI-NEXT:    ret

  %1 = fcmp ult <4 x half> %a, %b
  ret <4 x i1> %1
}

define <4 x i1> @test_fcmp_ule(<4 x half> %a, <4 x half> %b) #0 {
; CHECK-CVT-SD-LABEL: test_fcmp_ule:
; CHECK-CVT-SD:       // %bb.0:
; CHECK-CVT-SD-NEXT:    fcvtl v1.4s, v1.4h
; CHECK-CVT-SD-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-SD-NEXT:    fcmgt v0.4s, v0.4s, v1.4s
; CHECK-CVT-SD-NEXT:    xtn v0.4h, v0.4s
; CHECK-CVT-SD-NEXT:    mvn v0.8b, v0.8b
; CHECK-CVT-SD-NEXT:    ret
;
; CHECK-FP16-LABEL: test_fcmp_ule:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    fcmgt v0.4h, v0.4h, v1.4h
; CHECK-FP16-NEXT:    mvn v0.8b, v0.8b
; CHECK-FP16-NEXT:    ret
;
; CHECK-CVT-GI-LABEL: test_fcmp_ule:
; CHECK-CVT-GI:       // %bb.0:
; CHECK-CVT-GI-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-GI-NEXT:    fcvtl v1.4s, v1.4h
; CHECK-CVT-GI-NEXT:    fcmgt v0.4s, v0.4s, v1.4s
; CHECK-CVT-GI-NEXT:    mvn v0.16b, v0.16b
; CHECK-CVT-GI-NEXT:    xtn v0.4h, v0.4s
; CHECK-CVT-GI-NEXT:    ret

  %1 = fcmp ule <4 x half> %a, %b
  ret <4 x i1> %1
}

define <4 x i1> @test_fcmp_uno(<4 x half> %a, <4 x half> %b) #0 {
; CHECK-CVT-SD-LABEL: test_fcmp_uno:
; CHECK-CVT-SD:       // %bb.0:
; CHECK-CVT-SD-NEXT:    fcvtl v1.4s, v1.4h
; CHECK-CVT-SD-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-SD-NEXT:    fcmge v2.4s, v0.4s, v1.4s
; CHECK-CVT-SD-NEXT:    fcmgt v0.4s, v1.4s, v0.4s
; CHECK-CVT-SD-NEXT:    orr v0.16b, v0.16b, v2.16b
; CHECK-CVT-SD-NEXT:    xtn v0.4h, v0.4s
; CHECK-CVT-SD-NEXT:    mvn v0.8b, v0.8b
; CHECK-CVT-SD-NEXT:    ret
;
; CHECK-FP16-LABEL: test_fcmp_uno:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    fcmge v2.4h, v0.4h, v1.4h
; CHECK-FP16-NEXT:    fcmgt v0.4h, v1.4h, v0.4h
; CHECK-FP16-NEXT:    orr v0.8b, v0.8b, v2.8b
; CHECK-FP16-NEXT:    mvn v0.8b, v0.8b
; CHECK-FP16-NEXT:    ret
;
; CHECK-CVT-GI-LABEL: test_fcmp_uno:
; CHECK-CVT-GI:       // %bb.0:
; CHECK-CVT-GI-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-GI-NEXT:    fcvtl v1.4s, v1.4h
; CHECK-CVT-GI-NEXT:    fcmge v2.4s, v0.4s, v1.4s
; CHECK-CVT-GI-NEXT:    fcmgt v0.4s, v1.4s, v0.4s
; CHECK-CVT-GI-NEXT:    orr v0.16b, v0.16b, v2.16b
; CHECK-CVT-GI-NEXT:    mvn v0.16b, v0.16b
; CHECK-CVT-GI-NEXT:    xtn v0.4h, v0.4s
; CHECK-CVT-GI-NEXT:    ret

  %1 = fcmp uno <4 x half> %a, %b
  ret <4 x i1> %1
}

define <4 x i1> @test_fcmp_one(<4 x half> %a, <4 x half> %b) #0 {
; CHECK-CVT-SD-LABEL: test_fcmp_one:
; CHECK-CVT-SD:       // %bb.0:
; CHECK-CVT-SD-NEXT:    fcvtl v1.4s, v1.4h
; CHECK-CVT-SD-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-SD-NEXT:    fcmgt v2.4s, v0.4s, v1.4s
; CHECK-CVT-SD-NEXT:    fcmgt v0.4s, v1.4s, v0.4s
; CHECK-CVT-SD-NEXT:    orr v0.16b, v0.16b, v2.16b
; CHECK-CVT-SD-NEXT:    xtn v0.4h, v0.4s
; CHECK-CVT-SD-NEXT:    ret
;
; CHECK-FP16-LABEL: test_fcmp_one:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    fcmgt v2.4h, v0.4h, v1.4h
; CHECK-FP16-NEXT:    fcmgt v0.4h, v1.4h, v0.4h
; CHECK-FP16-NEXT:    orr v0.8b, v0.8b, v2.8b
; CHECK-FP16-NEXT:    ret
;
; CHECK-CVT-GI-LABEL: test_fcmp_one:
; CHECK-CVT-GI:       // %bb.0:
; CHECK-CVT-GI-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-GI-NEXT:    fcvtl v1.4s, v1.4h
; CHECK-CVT-GI-NEXT:    fcmgt v2.4s, v0.4s, v1.4s
; CHECK-CVT-GI-NEXT:    fcmgt v0.4s, v1.4s, v0.4s
; CHECK-CVT-GI-NEXT:    orr v0.16b, v0.16b, v2.16b
; CHECK-CVT-GI-NEXT:    xtn v0.4h, v0.4s
; CHECK-CVT-GI-NEXT:    ret

  %1 = fcmp one <4 x half> %a, %b
  ret <4 x i1> %1
}

define <4 x i1> @test_fcmp_oeq(<4 x half> %a, <4 x half> %b) #0 {
; CHECK-CVT-SD-LABEL: test_fcmp_oeq:
; CHECK-CVT-SD:       // %bb.0:
; CHECK-CVT-SD-NEXT:    fcvtl v1.4s, v1.4h
; CHECK-CVT-SD-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-SD-NEXT:    fcmeq v0.4s, v0.4s, v1.4s
; CHECK-CVT-SD-NEXT:    xtn v0.4h, v0.4s
; CHECK-CVT-SD-NEXT:    ret
;
; CHECK-FP16-LABEL: test_fcmp_oeq:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    fcmeq v0.4h, v0.4h, v1.4h
; CHECK-FP16-NEXT:    ret
;
; CHECK-CVT-GI-LABEL: test_fcmp_oeq:
; CHECK-CVT-GI:       // %bb.0:
; CHECK-CVT-GI-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-GI-NEXT:    fcvtl v1.4s, v1.4h
; CHECK-CVT-GI-NEXT:    fcmeq v0.4s, v0.4s, v1.4s
; CHECK-CVT-GI-NEXT:    xtn v0.4h, v0.4s
; CHECK-CVT-GI-NEXT:    ret

  %1 = fcmp oeq <4 x half> %a, %b
  ret <4 x i1> %1
}

define <4 x i1> @test_fcmp_ogt(<4 x half> %a, <4 x half> %b) #0 {
; CHECK-CVT-SD-LABEL: test_fcmp_ogt:
; CHECK-CVT-SD:       // %bb.0:
; CHECK-CVT-SD-NEXT:    fcvtl v1.4s, v1.4h
; CHECK-CVT-SD-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-SD-NEXT:    fcmgt v0.4s, v0.4s, v1.4s
; CHECK-CVT-SD-NEXT:    xtn v0.4h, v0.4s
; CHECK-CVT-SD-NEXT:    ret
;
; CHECK-FP16-LABEL: test_fcmp_ogt:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    fcmgt v0.4h, v0.4h, v1.4h
; CHECK-FP16-NEXT:    ret
;
; CHECK-CVT-GI-LABEL: test_fcmp_ogt:
; CHECK-CVT-GI:       // %bb.0:
; CHECK-CVT-GI-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-GI-NEXT:    fcvtl v1.4s, v1.4h
; CHECK-CVT-GI-NEXT:    fcmgt v0.4s, v0.4s, v1.4s
; CHECK-CVT-GI-NEXT:    xtn v0.4h, v0.4s
; CHECK-CVT-GI-NEXT:    ret

  %1 = fcmp ogt <4 x half> %a, %b
  ret <4 x i1> %1
}

define <4 x i1> @test_fcmp_oge(<4 x half> %a, <4 x half> %b) #0 {
; CHECK-CVT-SD-LABEL: test_fcmp_oge:
; CHECK-CVT-SD:       // %bb.0:
; CHECK-CVT-SD-NEXT:    fcvtl v1.4s, v1.4h
; CHECK-CVT-SD-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-SD-NEXT:    fcmge v0.4s, v0.4s, v1.4s
; CHECK-CVT-SD-NEXT:    xtn v0.4h, v0.4s
; CHECK-CVT-SD-NEXT:    ret
;
; CHECK-FP16-LABEL: test_fcmp_oge:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    fcmge v0.4h, v0.4h, v1.4h
; CHECK-FP16-NEXT:    ret
;
; CHECK-CVT-GI-LABEL: test_fcmp_oge:
; CHECK-CVT-GI:       // %bb.0:
; CHECK-CVT-GI-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-GI-NEXT:    fcvtl v1.4s, v1.4h
; CHECK-CVT-GI-NEXT:    fcmge v0.4s, v0.4s, v1.4s
; CHECK-CVT-GI-NEXT:    xtn v0.4h, v0.4s
; CHECK-CVT-GI-NEXT:    ret

  %1 = fcmp oge <4 x half> %a, %b
  ret <4 x i1> %1
}

define <4 x i1> @test_fcmp_olt(<4 x half> %a, <4 x half> %b) #0 {
; CHECK-CVT-LABEL: test_fcmp_olt:
; CHECK-CVT:       // %bb.0:
; CHECK-CVT-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-NEXT:    fcvtl v1.4s, v1.4h
; CHECK-CVT-NEXT:    fcmgt v0.4s, v1.4s, v0.4s
; CHECK-CVT-NEXT:    xtn v0.4h, v0.4s
; CHECK-CVT-NEXT:    ret
;
; CHECK-FP16-LABEL: test_fcmp_olt:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    fcmgt v0.4h, v1.4h, v0.4h
; CHECK-FP16-NEXT:    ret

  %1 = fcmp olt <4 x half> %a, %b
  ret <4 x i1> %1
}

define <4 x i1> @test_fcmp_ole(<4 x half> %a, <4 x half> %b) #0 {
; CHECK-CVT-LABEL: test_fcmp_ole:
; CHECK-CVT:       // %bb.0:
; CHECK-CVT-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-NEXT:    fcvtl v1.4s, v1.4h
; CHECK-CVT-NEXT:    fcmge v0.4s, v1.4s, v0.4s
; CHECK-CVT-NEXT:    xtn v0.4h, v0.4s
; CHECK-CVT-NEXT:    ret
;
; CHECK-FP16-LABEL: test_fcmp_ole:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    fcmge v0.4h, v1.4h, v0.4h
; CHECK-FP16-NEXT:    ret

  %1 = fcmp ole <4 x half> %a, %b
  ret <4 x i1> %1
}

define <4 x i1> @test_fcmp_ord(<4 x half> %a, <4 x half> %b) #0 {
; CHECK-CVT-SD-LABEL: test_fcmp_ord:
; CHECK-CVT-SD:       // %bb.0:
; CHECK-CVT-SD-NEXT:    fcvtl v1.4s, v1.4h
; CHECK-CVT-SD-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-SD-NEXT:    fcmge v2.4s, v0.4s, v1.4s
; CHECK-CVT-SD-NEXT:    fcmgt v0.4s, v1.4s, v0.4s
; CHECK-CVT-SD-NEXT:    orr v0.16b, v0.16b, v2.16b
; CHECK-CVT-SD-NEXT:    xtn v0.4h, v0.4s
; CHECK-CVT-SD-NEXT:    ret
;
; CHECK-FP16-LABEL: test_fcmp_ord:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    fcmge v2.4h, v0.4h, v1.4h
; CHECK-FP16-NEXT:    fcmgt v0.4h, v1.4h, v0.4h
; CHECK-FP16-NEXT:    orr v0.8b, v0.8b, v2.8b
; CHECK-FP16-NEXT:    ret
;
; CHECK-CVT-GI-LABEL: test_fcmp_ord:
; CHECK-CVT-GI:       // %bb.0:
; CHECK-CVT-GI-NEXT:    fcvtl v0.4s, v0.4h
; CHECK-CVT-GI-NEXT:    fcvtl v1.4s, v1.4h
; CHECK-CVT-GI-NEXT:    fcmge v2.4s, v0.4s, v1.4s
; CHECK-CVT-GI-NEXT:    fcmgt v0.4s, v1.4s, v0.4s
; CHECK-CVT-GI-NEXT:    orr v0.16b, v0.16b, v2.16b
; CHECK-CVT-GI-NEXT:    xtn v0.4h, v0.4s
; CHECK-CVT-GI-NEXT:    ret

  %1 = fcmp ord <4 x half> %a, %b
  ret <4 x i1> %1
}

attributes #0 = { nounwind }