| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 |
| ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ |
| ; RUN: -mcpu=future -ppc-asm-full-reg-names \ |
| ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s |
| ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix \ |
| ; RUN: -mcpu=future -ppc-asm-full-reg-names \ |
| ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE |
| |
| define void @tdmrz(ptr nocapture readonly %vp1, ptr nocapture %resp) { |
| ; CHECK-LABEL: tdmrz: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: dmsetdmrz dmr0 |
| ; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0 |
| ; CHECK-NEXT: stxvp vsp34, 96(r4) |
| ; CHECK-NEXT: stxvp vsp36, 64(r4) |
| ; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1 |
| ; CHECK-NEXT: stxvp vsp34, 32(r4) |
| ; CHECK-NEXT: stxvp vsp36, 0(r4) |
| ; CHECK-NEXT: blr |
| ; |
| ; CHECK-BE-LABEL: tdmrz: |
| ; CHECK-BE: # %bb.0: # %entry |
| ; CHECK-BE-NEXT: dmsetdmrz dmr0 |
| ; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1 |
| ; CHECK-BE-NEXT: stxvp vsp36, 96(r4) |
| ; CHECK-BE-NEXT: stxvp vsp34, 64(r4) |
| ; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0 |
| ; CHECK-BE-NEXT: stxvp vsp36, 32(r4) |
| ; CHECK-BE-NEXT: stxvp vsp34, 0(r4) |
| ; CHECK-BE-NEXT: blr |
| entry: |
| %z = call <1024 x i1> @llvm.ppc.mma.dmsetdmrz() |
| store <1024 x i1> %z, ptr %resp, align 32 |
| ret void |
| } |
| |
| define void @tdmmr(ptr nocapture readonly %vp1, ptr nocapture %resp) { |
| ; CHECK-LABEL: tdmmr: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: lxvp vsp34, 0(r3) |
| ; CHECK-NEXT: lxvp vsp36, 32(r3) |
| ; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1 |
| ; CHECK-NEXT: lxvp vsp34, 64(r3) |
| ; CHECK-NEXT: lxvp vsp36, 96(r3) |
| ; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0 |
| ; CHECK-NEXT: dmmr dmr0, dmr0 |
| ; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0 |
| ; CHECK-NEXT: stxvp vsp34, 96(r4) |
| ; CHECK-NEXT: stxvp vsp36, 64(r4) |
| ; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1 |
| ; CHECK-NEXT: stxvp vsp34, 32(r4) |
| ; CHECK-NEXT: stxvp vsp36, 0(r4) |
| ; CHECK-NEXT: blr |
| ; |
| ; CHECK-BE-LABEL: tdmmr: |
| ; CHECK-BE: # %bb.0: # %entry |
| ; CHECK-BE-NEXT: lxvp vsp34, 96(r3) |
| ; CHECK-BE-NEXT: lxvp vsp36, 64(r3) |
| ; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1 |
| ; CHECK-BE-NEXT: lxvp vsp34, 32(r3) |
| ; CHECK-BE-NEXT: lxvp vsp36, 0(r3) |
| ; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0 |
| ; CHECK-BE-NEXT: dmmr dmr0, dmr0 |
| ; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1 |
| ; CHECK-BE-NEXT: stxvp vsp36, 96(r4) |
| ; CHECK-BE-NEXT: stxvp vsp34, 64(r4) |
| ; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0 |
| ; CHECK-BE-NEXT: stxvp vsp36, 32(r4) |
| ; CHECK-BE-NEXT: stxvp vsp34, 0(r4) |
| ; CHECK-BE-NEXT: blr |
| entry: |
| %l = load <1024 x i1>, ptr %vp1, align 32 |
| %c = call <1024 x i1> @llvm.ppc.mma.dmmr(<1024 x i1> %l) |
| store <1024 x i1> %c, ptr %resp, align 32 |
| ret void |
| } |
| |
| define void @tdmxor(ptr nocapture readonly %vp1, ptr %vp2, ptr nocapture %resp) { |
| ; CHECK-LABEL: tdmxor: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: lxvp vsp34, 0(r3) |
| ; CHECK-NEXT: lxvp vsp36, 32(r3) |
| ; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1 |
| ; CHECK-NEXT: lxvp vsp34, 64(r3) |
| ; CHECK-NEXT: lxvp vsp36, 96(r3) |
| ; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0 |
| ; CHECK-NEXT: lxvp vsp34, 0(r4) |
| ; CHECK-NEXT: lxvp vsp36, 32(r4) |
| ; CHECK-NEXT: dmxxinstdmr512 wacc_hi1, vsp36, vsp34, 1 |
| ; CHECK-NEXT: lxvp vsp34, 64(r4) |
| ; CHECK-NEXT: lxvp vsp36, 96(r4) |
| ; CHECK-NEXT: dmxxinstdmr512 wacc1, vsp36, vsp34, 0 |
| ; CHECK-NEXT: dmxor dmr0, dmr1 |
| ; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0 |
| ; CHECK-NEXT: stxvp vsp34, 96(r5) |
| ; CHECK-NEXT: stxvp vsp36, 64(r5) |
| ; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1 |
| ; CHECK-NEXT: stxvp vsp34, 32(r5) |
| ; CHECK-NEXT: stxvp vsp36, 0(r5) |
| ; CHECK-NEXT: blr |
| ; |
| ; CHECK-BE-LABEL: tdmxor: |
| ; CHECK-BE: # %bb.0: # %entry |
| ; CHECK-BE-NEXT: lxvp vsp34, 96(r3) |
| ; CHECK-BE-NEXT: lxvp vsp36, 64(r3) |
| ; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1 |
| ; CHECK-BE-NEXT: lxvp vsp34, 32(r3) |
| ; CHECK-BE-NEXT: lxvp vsp36, 0(r3) |
| ; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0 |
| ; CHECK-BE-NEXT: lxvp vsp34, 96(r4) |
| ; CHECK-BE-NEXT: lxvp vsp36, 64(r4) |
| ; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi1, vsp36, vsp34, 1 |
| ; CHECK-BE-NEXT: lxvp vsp34, 32(r4) |
| ; CHECK-BE-NEXT: lxvp vsp36, 0(r4) |
| ; CHECK-BE-NEXT: dmxxinstdmr512 wacc1, vsp36, vsp34, 0 |
| ; CHECK-BE-NEXT: dmxor dmr0, dmr1 |
| ; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1 |
| ; CHECK-BE-NEXT: stxvp vsp36, 96(r5) |
| ; CHECK-BE-NEXT: stxvp vsp34, 64(r5) |
| ; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0 |
| ; CHECK-BE-NEXT: stxvp vsp36, 32(r5) |
| ; CHECK-BE-NEXT: stxvp vsp34, 0(r5) |
| ; CHECK-BE-NEXT: blr |
| entry: |
| %l = load <1024 x i1>, ptr %vp1, align 32 |
| %r = load <1024 x i1>, ptr %vp2, align 32 |
| %x = call <1024 x i1> @llvm.ppc.mma.dmxor(<1024 x i1> %l, <1024 x i1> %r) |
| store <1024 x i1> %x, ptr %resp, align 32 |
| ret void |
| } |
| |
| declare <1024 x i1> @llvm.ppc.mma.dmsetdmrz() |
| declare <1024 x i1> @llvm.ppc.mma.dmmr(<1024 x i1>) |
| declare <1024 x i1> @llvm.ppc.mma.dmxor(<1024 x i1>, <1024 x i1>) |
