llvm/test/CodeGen/AArch64/add-extract.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=aarch64-none-elf -mattr=+aes < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc -mtriple=aarch64-none-elf -mattr=+aes -global-isel < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI

define i64 @add_i64_ext_load(<1 x i64> %A, ptr %B) nounwind {
; CHECK-SD-LABEL: add_i64_ext_load:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    ldr d1, [x0]
; CHECK-SD-NEXT:    add d0, d0, d1
; CHECK-SD-NEXT:    fmov x0, d0
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: add_i64_ext_load:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    fmov x9, d0
; CHECK-GI-NEXT:    ldr x8, [x0]
; CHECK-GI-NEXT:    add x0, x9, x8
; CHECK-GI-NEXT:    ret
  %a = extractelement <1 x i64> %A, i32 0
  %b = load i64, ptr %B
  %c = add i64 %a, %b
  ret i64 %c
}

define i64 @sub_i64_ext_load(<1 x i64> %A, ptr %B) nounwind {
; CHECK-SD-LABEL: sub_i64_ext_load:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    ldr d1, [x0]
; CHECK-SD-NEXT:    sub d0, d0, d1
; CHECK-SD-NEXT:    fmov x0, d0
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: sub_i64_ext_load:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    fmov x9, d0
; CHECK-GI-NEXT:    ldr x8, [x0]
; CHECK-GI-NEXT:    sub x0, x9, x8
; CHECK-GI-NEXT:    ret
  %a = extractelement <1 x i64> %A, i32 0
  %b = load i64, ptr %B
  %c = sub i64 %a, %b
  ret i64 %c
}

define void @add_i64_ext_load_store(<1 x i64> %A, ptr %B) nounwind {
; CHECK-SD-LABEL: add_i64_ext_load_store:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    ldr d1, [x0]
; CHECK-SD-NEXT:    add d0, d0, d1
; CHECK-SD-NEXT:    str d0, [x0]
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: add_i64_ext_load_store:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    fmov x9, d0
; CHECK-GI-NEXT:    ldr x8, [x0]
; CHECK-GI-NEXT:    add x8, x9, x8
; CHECK-GI-NEXT:    str x8, [x0]
; CHECK-GI-NEXT:    ret
  %a = extractelement <1 x i64> %A, i32 0
  %b = load i64, ptr %B
  %c = add i64 %a, %b
  store i64 %c, ptr %B
  ret void
}

define i64 @add_v2i64_ext_load(<2 x i64> %A, ptr %B) nounwind {
; CHECK-LABEL: add_v2i64_ext_load:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fmov x9, d0
; CHECK-NEXT:    ldr x8, [x0]
; CHECK-NEXT:    add x0, x9, x8
; CHECK-NEXT:    ret
  %a = extractelement <2 x i64> %A, i32 0
  %b = load i64, ptr %B
  %c = add i64 %a, %b
  ret i64 %c
}

define i64 @add_i64_ext_ext(<1 x i64> %A, <1 x i64> %B) nounwind {
; CHECK-SD-LABEL: add_i64_ext_ext:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    add d0, d0, d1
; CHECK-SD-NEXT:    fmov x0, d0
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: add_i64_ext_ext:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    fmov x8, d0
; CHECK-GI-NEXT:    fmov x9, d1
; CHECK-GI-NEXT:    add x0, x8, x9
; CHECK-GI-NEXT:    ret
  %a = extractelement <1 x i64> %A, i32 0
  %b = extractelement <1 x i64> %B, i32 0
  %c = add i64 %a, %b
  ret i64 %c
}

define i32 @add_i32_ext_load(<1 x i32> %A, ptr %B) nounwind {
; CHECK-SD-LABEL: add_i32_ext_load:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 def $q0
; CHECK-SD-NEXT:    fmov w9, s0
; CHECK-SD-NEXT:    ldr w8, [x0]
; CHECK-SD-NEXT:    add w0, w9, w8
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: add_i32_ext_load:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    fmov w9, s0
; CHECK-GI-NEXT:    ldr w8, [x0]
; CHECK-GI-NEXT:    add w0, w9, w8
; CHECK-GI-NEXT:    ret
  %a = extractelement <1 x i32> %A, i32 0
  %b = load i32, ptr %B
  %c = add i32 %a, %b
  ret i32 %c
}

define i64 @add_i64_ext_ext_test1(<1 x i64> %A, <2 x i64> %B) nounwind {
; CHECK-SD-LABEL: add_i64_ext_ext_test1:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    ext v2.16b, v1.16b, v1.16b, #8
; CHECK-SD-NEXT:    add d0, d0, d1
; CHECK-SD-NEXT:    add d0, d0, d2
; CHECK-SD-NEXT:    fmov x0, d0
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: add_i64_ext_ext_test1:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    mov x8, v1.d[1]
; CHECK-GI-NEXT:    fmov x9, d0
; CHECK-GI-NEXT:    fmov x10, d1
; CHECK-GI-NEXT:    add x9, x9, x10
; CHECK-GI-NEXT:    add x0, x9, x8
; CHECK-GI-NEXT:    ret
  %a = extractelement <1 x i64> %A, i32 0
  %b = extractelement <2 x i64> %B, i32 0
  %c = extractelement <2 x i64> %B, i32 1
  %d = add i64 %a, %b
  %e = add i64 %d, %c
  ret i64 %e
}

define i64 @sub_i64_ext_ext_test1(<1 x i64> %A, <2 x i64> %B) nounwind {
; CHECK-SD-LABEL: sub_i64_ext_ext_test1:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    ext v2.16b, v1.16b, v1.16b, #8
; CHECK-SD-NEXT:    sub d0, d0, d1
; CHECK-SD-NEXT:    sub d0, d0, d2
; CHECK-SD-NEXT:    fmov x0, d0
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: sub_i64_ext_ext_test1:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    mov x8, v1.d[1]
; CHECK-GI-NEXT:    fmov x9, d0
; CHECK-GI-NEXT:    fmov x10, d1
; CHECK-GI-NEXT:    sub x9, x9, x10
; CHECK-GI-NEXT:    sub x0, x9, x8
; CHECK-GI-NEXT:    ret
  %a = extractelement <1 x i64> %A, i32 0
  %b = extractelement <2 x i64> %B, i32 0
  %c = extractelement <2 x i64> %B, i32 1
  %d = sub i64 %a, %b
  %e = sub i64 %d, %c
  ret i64 %e
}