llvm/test/CodeGen/AMDGPU/limit-coalesce.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=amdgcn -run-pass register-coalescer -o - %s | FileCheck %s

# Check that coalescer does not create wider register tuple than in
# source.
# No more registers shall be defined
---
name:            main
tracksRegLiveness: true
registers:
  - { id: 0, class: sreg_32_xm0, preferred-register: '%0' }
  - { id: 1, class: vreg_64, preferred-register: '%1' }
body:             |
  bb.0:
    liveins: $sgpr0, $vgpr0_vgpr1

    ; CHECK-LABEL: name: main
    ; CHECK: liveins: $sgpr0, $vgpr0_vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
    ; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0:vreg_64 = COPY $sgpr0
    ; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:vreg_64 = COPY [[DEF]].sub0
    ; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:vreg_64 = COPY [[COPY]].sub1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:vreg_64 = COPY [[COPY]].sub0
    ; CHECK-NEXT: FLAT_STORE_DWORDX2 $vgpr0_vgpr1, [[COPY1]], 0, 0, implicit $exec, implicit $flat_scr
    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_96 = IMPLICIT_DEF
    ; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0_sub1:vreg_96 = COPY [[DEF1]]
    ; CHECK-NEXT: [[COPY2:%[0-9]+]].sub2:vreg_96 = COPY [[DEF]].sub0
    ; CHECK-NEXT: FLAT_STORE_DWORDX3 $vgpr0_vgpr1, [[COPY2]], 0, 0, implicit $exec, implicit $flat_scr
    ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_128 = IMPLICIT_DEF
    ; CHECK-NEXT: undef [[COPY3:%[0-9]+]].sub0_sub1_sub2:vreg_128 = COPY [[DEF2]]
    ; CHECK-NEXT: [[COPY3:%[0-9]+]].sub3:vreg_128 = COPY [[DEF]].sub0
    ; CHECK-NEXT: FLAT_STORE_DWORDX4 $vgpr0_vgpr1, [[COPY3]], 0, 0, implicit $exec, implicit $flat_scr
    %2:vreg_64 = IMPLICIT_DEF
    undef %3.sub0:vreg_64 = COPY $sgpr0
    %3.sub1:vreg_64 = COPY %2.sub0
    undef %4.sub0:vreg_64 = COPY %3.sub1
    %4.sub1:vreg_64 = COPY %3.sub0
    FLAT_STORE_DWORDX2 $vgpr0_vgpr1, killed %4, 0, 0, implicit $exec, implicit $flat_scr

    %5:vreg_96 = IMPLICIT_DEF
    undef %6.sub0_sub1:vreg_96 = COPY %5
    %6.sub2:vreg_96 = COPY %2.sub0
    FLAT_STORE_DWORDX3 $vgpr0_vgpr1, killed %6, 0, 0, implicit $exec, implicit $flat_scr

    %7:vreg_128 = IMPLICIT_DEF
    undef %8.sub0_sub1_sub2:vreg_128 = COPY %7
    %8.sub3:vreg_128 = COPY %2.sub0
    FLAT_STORE_DWORDX4 $vgpr0_vgpr1, killed %8, 0, 0, implicit $exec, implicit $flat_scr

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