llvm/test/CodeGen/SystemZ/vec-unpack-03.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5

; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s

define <8 x i16> @f1(<16 x i8> %a) {
; CHECK-LABEL: f1:
; CHECK:       # %bb.0: # %start
; CHECK-NEXT:    vuplhb %v24, %v24
; CHECK-NEXT:    br %r14
start:
  %0 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
  %1 = zext <8 x i8> %0 to <8 x i16>
  ret <8 x i16> %1
}

define <8 x i16> @f2(<16 x i8> %a) {
; CHECK-LABEL: f2:
; CHECK:       # %bb.0: # %start
; CHECK-NEXT:    vupllb %v24, %v24
; CHECK-NEXT:    br %r14
start:
  %0 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
  %1 = zext <8 x i8> %0 to <8 x i16>
  ret <8 x i16> %1
}

define <4 x i32> @f3(<8 x i16> %a) {
; CHECK-LABEL: f3:
; CHECK:       # %bb.0: # %start
; CHECK-NEXT:    vuplhh %v24, %v24
; CHECK-NEXT:    br %r14
start:
  %0 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %1 = zext <4 x i16> %0 to <4 x i32>
  ret <4 x i32> %1
}

define <4 x i32> @f4(<8 x i16> %a) {
; CHECK-LABEL: f4:
; CHECK:       # %bb.0: # %start
; CHECK-NEXT:    vupllh %v24, %v24
; CHECK-NEXT:    br %r14
start:
  %0 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
  %1 = zext <4 x i16> %0 to <4 x i32>
  ret <4 x i32> %1
}

define <2 x i64> @f5(<4 x i32> %a) {
; CHECK-LABEL: f5:
; CHECK:       # %bb.0: # %start
; CHECK-NEXT:    vuplhf %v24, %v24
; CHECK-NEXT:    br %r14
start:
  %0 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 0, i32 1>
  %1 = zext <2 x i32> %0 to <2 x i64>
  ret <2 x i64> %1
}

define <2 x i64> @f6(<4 x i32> %a) {
; CHECK-LABEL: f6:
; CHECK:       # %bb.0: # %start
; CHECK-NEXT:    vupllf %v24, %v24
; CHECK-NEXT:    br %r14
start:
  %0 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 2, i32 3>
  %1 = zext <2 x i32> %0 to <2 x i64>
  ret <2 x i64> %1
}