commit 2680e8806958a60ca2f1bedac48f795c0b79a159
author Matt Arsenault <Matthew.Arsenault@amd.com> Thu Apr 02 18:50:09 2020 -0400
committer Matt Arsenault <arsenm2@gmail.com> Thu Apr 02 18:52:49 2020 -0400
tree 01734903ab4403331c739a1c184b606437173290
parent 2aab46ab0282b968de8593f916950d793a5a76d6

AMDGPU: Fix broken check lines

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.ll

diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.ll
index f35bb54..69ee096 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.ll
@@ -357,9 +357,9 @@
 ; SI: s_mov_b32 [[K:s[0-9]+]], 0x80000{{$}}
 ; SI: s_buffer_load_dword s0, s[0:3], [[K]]{{$}}
 
-; CI s_buffer_load_dword s0, s[0:3], 0x20000{{$}}
+; CI: s_buffer_load_dword s0, s[0:3], 0x20000{{$}}
 
-; VI s_buffer_load_dword s0, s[0:3], 0x20000{{$}}
+; VI: s_buffer_load_dword s0, s[0:3], 0x80000{{$}}
 define amdgpu_ps i32 @s_buffer_load_imm_bit19(<4 x i32> inreg %desc) {
   %load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 524288, i32 0)
   ret i32 %load
@@ -369,9 +369,10 @@
 ; SI: s_mov_b32 [[K:s[0-9]+]], 0xfff80000{{$}}
 ; SI: s_buffer_load_dword s0, s[0:3], [[K]]{{$}}
 
-; CI s_buffer_load_dword s0, s[0:3], 0x20000{{$}}
+; CI: s_buffer_load_dword s0, s[0:3], 0x3ffe0000{{$}}
 
-; VI s_buffer_load_dword s0, s[0:3], 0x20000{{$}}
+; VI: s_mov_b32 [[K:s[0-9]+]], 0xfff80000{{$}}
+; VI: s_buffer_load_dword s0, s[0:3], [[K]]{{$}}
 define amdgpu_ps i32 @s_buffer_load_imm_neg_bit19(<4 x i32> inreg %desc) {
   %load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 -524288, i32 0)
   ret i32 %load