| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -stress-regalloc=2 -verify-machineinstrs < %s | FileCheck %s |
| |
| |
| define void @test_remat_s_getpc_b64() { |
| ; CHECK-LABEL: test_remat_s_getpc_b64: |
| ; CHECK: ; %bb.0: ; %entry |
| ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; CHECK-NEXT: s_xor_saveexec_b64 s[4:5], -1 |
| ; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill |
| ; CHECK-NEXT: s_mov_b64 exec, s[4:5] |
| ; CHECK-NEXT: v_writelane_b32 v0, s30, 0 |
| ; CHECK-NEXT: s_getpc_b64 s[4:5] |
| ; CHECK-NEXT: v_writelane_b32 v0, s31, 1 |
| ; CHECK-NEXT: ;;#ASMSTART |
| ; CHECK-NEXT: ;;#ASMEND |
| ; CHECK-NEXT: ;;#ASMSTART |
| ; CHECK-NEXT: ;;#ASMEND |
| ; CHECK-NEXT: s_getpc_b64 s[4:5] |
| ; CHECK-NEXT: v_mov_b32_e32 v1, s4 |
| ; CHECK-NEXT: v_mov_b32_e32 v2, s5 |
| ; CHECK-NEXT: global_store_dwordx2 v[1:2], v[1:2], off |
| ; CHECK-NEXT: v_readlane_b32 s31, v0, 1 |
| ; CHECK-NEXT: v_readlane_b32 s30, v0, 0 |
| ; CHECK-NEXT: s_xor_saveexec_b64 s[4:5], -1 |
| ; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload |
| ; CHECK-NEXT: s_mov_b64 exec, s[4:5] |
| ; CHECK-NEXT: s_waitcnt vmcnt(0) |
| ; CHECK-NEXT: s_setpc_b64 s[30:31] |
| entry: |
| %0 = tail call i64 @llvm.amdgcn.s.getpc() |
| tail call void asm sideeffect "", "s"(i64 %0) |
| tail call void asm sideeffect "", "~{s0},~{s1},~{s2},~{s3},~{s4},~{s5},~{s6},~{s7},~{s8},~{s9},~{s10},~{s11},~{s12},~{s13},~{s14},~{s15},~{s16},~{s17},~{s18},~{s19},~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s29},~{s30},~{s31}"() |
| store i64 %0, ptr addrspace(1) undef |
| ret void |
| } |
| |
| declare i64 @llvm.amdgcn.s.getpc() |
