| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=regallocfast -o - %s | FileCheck -check-prefix=SPILLED %s |
| # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=regallocfast,si-lower-sgpr-spills -o - %s | FileCheck -check-prefix=EXPANDED %s |
| |
| # Make sure spill/restore of 192 bit registers works. We have to |
| # settle for a MIR test for now since inlineasm fails without 192-bit |
| # MVT. |
| |
| --- |
| name: spill_restore_sgpr192 |
| tracksRegLiveness: true |
| machineFunctionInfo: |
| scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3 |
| stackPtrOffsetReg: $sgpr32 |
| body: | |
| ; SPILLED-LABEL: name: spill_restore_sgpr192 |
| ; SPILLED: bb.0: |
| ; SPILLED: successors: %bb.1(0x80000000) |
| ; SPILLED: S_NOP 0, implicit-def renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9 |
| ; SPILLED: SI_SPILL_S192_SAVE killed $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9, %stack.0, implicit $exec, implicit $sgpr32 :: (store (s192) into %stack.0, align 4, addrspace 5) |
| ; SPILLED: S_CBRANCH_SCC1 %bb.1, implicit undef $scc |
| ; SPILLED: bb.1: |
| ; SPILLED: successors: %bb.2(0x80000000) |
| ; SPILLED: S_NOP 1 |
| ; SPILLED: bb.2: |
| ; SPILLED: $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9 = SI_SPILL_S192_RESTORE %stack.0, implicit $exec, implicit $sgpr32 :: (load (s192) from %stack.0, align 4, addrspace 5) |
| ; SPILLED: S_NOP 0, implicit killed renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9 |
| ; EXPANDED-LABEL: name: spill_restore_sgpr192 |
| ; EXPANDED: bb.0: |
| ; EXPANDED: successors: %bb.1(0x80000000) |
| ; EXPANDED: liveins: $vgpr0 |
| ; EXPANDED: S_NOP 0, implicit-def renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9 |
| ; EXPANDED: $vgpr0 = V_WRITELANE_B32 $sgpr4, 0, $vgpr0, implicit-def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9, implicit $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9 |
| ; EXPANDED: $vgpr0 = V_WRITELANE_B32 $sgpr5, 1, $vgpr0, implicit $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9 |
| ; EXPANDED: $vgpr0 = V_WRITELANE_B32 $sgpr6, 2, $vgpr0, implicit $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9 |
| ; EXPANDED: $vgpr0 = V_WRITELANE_B32 $sgpr7, 3, $vgpr0, implicit $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9 |
| ; EXPANDED: $vgpr0 = V_WRITELANE_B32 $sgpr8, 4, $vgpr0, implicit $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9 |
| ; EXPANDED: $vgpr0 = V_WRITELANE_B32 killed $sgpr9, 5, $vgpr0, implicit killed $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9 |
| ; EXPANDED: S_CBRANCH_SCC1 %bb.1, implicit undef $scc |
| ; EXPANDED: bb.1: |
| ; EXPANDED: successors: %bb.2(0x80000000) |
| ; EXPANDED: liveins: $vgpr0 |
| ; EXPANDED: S_NOP 1 |
| ; EXPANDED: bb.2: |
| ; EXPANDED: liveins: $vgpr0 |
| ; EXPANDED: $sgpr4 = V_READLANE_B32 $vgpr0, 0, implicit-def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9 |
| ; EXPANDED: $sgpr5 = V_READLANE_B32 $vgpr0, 1 |
| ; EXPANDED: $sgpr6 = V_READLANE_B32 $vgpr0, 2 |
| ; EXPANDED: $sgpr7 = V_READLANE_B32 $vgpr0, 3 |
| ; EXPANDED: $sgpr8 = V_READLANE_B32 $vgpr0, 4 |
| ; EXPANDED: $sgpr9 = V_READLANE_B32 $vgpr0, 5 |
| ; EXPANDED: S_NOP 0, implicit killed renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9 |
| bb.0: |
| S_NOP 0, implicit-def %0:sgpr_192 |
| S_CBRANCH_SCC1 implicit undef $scc, %bb.1 |
| |
| bb.1: |
| S_NOP 1 |
| |
| bb.2: |
| S_NOP 0, implicit %0 |
| ... |
| |
| --- |
| name: spill_restore_vgpr192 |
| tracksRegLiveness: true |
| machineFunctionInfo: |
| scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3 |
| stackPtrOffsetReg: $sgpr32 |
| body: | |
| ; SPILLED-LABEL: name: spill_restore_vgpr192 |
| ; SPILLED: bb.0: |
| ; SPILLED: successors: %bb.1(0x80000000) |
| ; SPILLED: S_NOP 0, implicit-def renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 |
| ; SPILLED: SI_SPILL_V192_SAVE killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, %stack.0, $sgpr32, 0, implicit $exec :: (store (s192) into %stack.0, align 4, addrspace 5) |
| ; SPILLED: S_CBRANCH_SCC1 %bb.1, implicit undef $scc |
| ; SPILLED: bb.1: |
| ; SPILLED: successors: %bb.2(0x80000000) |
| ; SPILLED: S_NOP 1 |
| ; SPILLED: bb.2: |
| ; SPILLED: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = SI_SPILL_V192_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s192) from %stack.0, align 4, addrspace 5) |
| ; SPILLED: S_NOP 0, implicit killed renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 |
| ; EXPANDED-LABEL: name: spill_restore_vgpr192 |
| ; EXPANDED: bb.0: |
| ; EXPANDED: successors: %bb.1(0x80000000) |
| ; EXPANDED: S_NOP 0, implicit-def renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 |
| ; EXPANDED: SI_SPILL_V192_SAVE killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, %stack.0, $sgpr32, 0, implicit $exec :: (store (s192) into %stack.0, align 4, addrspace 5) |
| ; EXPANDED: S_CBRANCH_SCC1 %bb.1, implicit undef $scc |
| ; EXPANDED: bb.1: |
| ; EXPANDED: successors: %bb.2(0x80000000) |
| ; EXPANDED: S_NOP 1 |
| ; EXPANDED: bb.2: |
| ; EXPANDED: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = SI_SPILL_V192_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s192) from %stack.0, align 4, addrspace 5) |
| ; EXPANDED: S_NOP 0, implicit killed renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 |
| bb.0: |
| S_NOP 0, implicit-def %0:vreg_192 |
| S_CBRANCH_SCC1 implicit undef $scc, %bb.1 |
| |
| bb.1: |
| S_NOP 1 |
| |
| bb.2: |
| S_NOP 0, implicit %0 |
| ... |