| ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py |
| ; RUN: opt < %s -passes='sroa<preserve-cfg>' -S | FileCheck %s --check-prefixes=CHECK,CHECK-PRESERVE-CFG |
| ; RUN: opt < %s -passes='sroa<modify-cfg>' -S | FileCheck %s --check-prefixes=CHECK,CHECK-MODIFY-CFG |
| target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64" |
| |
| define <4 x i1> @vector_bitcast() { |
| ; CHECK-LABEL: @vector_bitcast( |
| ; CHECK-NEXT: [[A:%.*]] = alloca <3 x i1>, align 1 |
| ; CHECK-NEXT: store <3 x i1> <i1 true, i1 false, i1 true>, ptr [[A]], align 1 |
| ; CHECK-NEXT: [[A_0_VEC:%.*]] = load <4 x i1>, ptr [[A]], align 1 |
| ; CHECK-NEXT: ret <4 x i1> [[A_0_VEC]] |
| ; |
| %a = alloca <3 x i1> |
| store <3 x i1> <i1 1,i1 0,i1 1>, ptr %a |
| %vec = load <4 x i1>, ptr %a |
| ret <4 x i1> %vec |
| } |
| |
| define <64 x i16> @vector_bitcast_2(<32 x i16> %v) { |
| ; CHECK-LABEL: @vector_bitcast_2( |
| ; CHECK-NEXT: [[P:%.*]] = alloca <32 x i16>, align 64 |
| ; CHECK-NEXT: store <32 x i16> [[V:%.*]], ptr [[P]], align 64 |
| ; CHECK-NEXT: [[P_0_LOAD:%.*]] = load <64 x i16>, ptr [[P]], align 64 |
| ; CHECK-NEXT: ret <64 x i16> [[P_0_LOAD]] |
| ; |
| %p = alloca <32 x i16> |
| store <32 x i16> %v, ptr %p |
| %load = load <64 x i16>, ptr %p |
| ret <64 x i16> %load |
| } |
| ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: |
| ; CHECK-MODIFY-CFG: {{.*}} |
| ; CHECK-PRESERVE-CFG: {{.*}} |
