| ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py |
| ; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=i686-pc-win32 -mcpu=corei7-avx | FileCheck %s |
| |
| target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" |
| target triple = "x86_64-unknown-linux" |
| |
| @e = dso_local global i32 0, align 4 |
| @f = dso_local local_unnamed_addr global i32 0, align 4 |
| @d = dso_local global i32 0, align 4 |
| @c = dso_local global i32 0, align 4 |
| @b = dso_local global i32 0, align 4 |
| @a = dso_local local_unnamed_addr global i32 0, align 4 |
| |
| define dso_local i32 @main() { |
| ; CHECK-LABEL: @main( |
| ; CHECK-NEXT: entry: |
| ; CHECK-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @e, align 4 |
| ; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @f, align 4 |
| ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], [[TMP1]] |
| ; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] |
| ; CHECK: if.then: |
| ; CHECK-NEXT: [[TMP2:%.*]] = load volatile i32, ptr @d, align 4 |
| ; CHECK-NEXT: [[TMP3:%.*]] = load volatile i32, ptr @c, align 4 |
| ; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i32 [[TMP3]], 0 |
| ; CHECK-NEXT: br i1 [[TOBOOL_NOT]], label [[LOR_RHS:%.*]], label [[LOR_END:%.*]] |
| ; CHECK: lor.rhs: |
| ; CHECK-NEXT: [[TMP4:%.*]] = load volatile i32, ptr @d, align 4 |
| ; CHECK-NEXT: [[TOBOOL1:%.*]] = icmp ne i32 [[TMP4]], 0 |
| ; CHECK-NEXT: [[PHI_CAST:%.*]] = zext i1 [[TOBOOL1]] to i32 |
| ; CHECK-NEXT: br label [[LOR_END]] |
| ; CHECK: lor.end: |
| ; CHECK-NEXT: [[TMP5:%.*]] = phi i32 [ 1, [[IF_THEN]] ], [ [[PHI_CAST]], [[LOR_RHS]] ] |
| ; CHECK-NEXT: [[TOBOOL2:%.*]] = icmp ne i32 [[TMP1]], 0 |
| ; CHECK-NEXT: [[LAND_EXT:%.*]] = zext i1 [[TOBOOL2]] to i32 |
| ; CHECK-NEXT: [[OR:%.*]] = or i32 [[TMP5]], [[LAND_EXT]] |
| ; CHECK-NEXT: store volatile i32 [[OR]], ptr @b, align 4 |
| ; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP1]], [[TMP2]] |
| ; CHECK-NEXT: [[TMP6:%.*]] = load volatile i32, ptr @d, align 4 |
| ; CHECK-NEXT: [[TOBOOL4_NOT:%.*]] = icmp eq i32 [[TMP6]], 0 |
| ; CHECK-NEXT: br i1 [[TOBOOL4_NOT]], label [[LAND_END7:%.*]], label [[LAND_RHS5:%.*]] |
| ; CHECK: land.rhs5: |
| ; CHECK-NEXT: [[TMP7:%.*]] = load volatile i32, ptr @c, align 4 |
| ; CHECK-NEXT: [[TOBOOL6:%.*]] = icmp ne i32 [[TMP7]], 0 |
| ; CHECK-NEXT: [[PHI_CAST11:%.*]] = zext i1 [[TOBOOL6]] to i32 |
| ; CHECK-NEXT: br label [[LAND_END7]] |
| ; CHECK: land.end7: |
| ; CHECK-NEXT: [[TMP8:%.*]] = phi i32 [ 0, [[LOR_END]] ], [ [[PHI_CAST11]], [[LAND_RHS5]] ] |
| ; CHECK-NEXT: [[OR9:%.*]] = or i32 [[TMP8]], [[DIV]] |
| ; CHECK-NEXT: store i32 [[OR9]], ptr @a, align 4 |
| ; CHECK-NEXT: br label [[IF_END]] |
| ; CHECK: if.end: |
| ; CHECK-NEXT: ret i32 0 |
| ; |
| entry: |
| %0 = load volatile i32, ptr @e, align 4 |
| %1 = load i32, ptr @f, align 4 |
| %cmp = icmp sgt i32 %0, %1 |
| br i1 %cmp, label %if.then, label %if.end |
| |
| if.then: ; preds = %entry |
| %2 = load volatile i32, ptr @d, align 4 |
| %3 = load volatile i32, ptr @c, align 4 |
| %tobool.not = icmp eq i32 %3, 0 |
| br i1 %tobool.not, label %lor.rhs, label %lor.end |
| |
| lor.rhs: ; preds = %if.then |
| %4 = load volatile i32, ptr @d, align 4 |
| %tobool1 = icmp ne i32 %4, 0 |
| %phi.cast = zext i1 %tobool1 to i32 |
| br label %lor.end |
| |
| lor.end: ; preds = %lor.rhs, %if.then |
| %5 = phi i32 [ 1, %if.then ], [ %phi.cast, %lor.rhs ] |
| %tobool2 = icmp ne i32 %1, 0 |
| %land.ext = zext i1 %tobool2 to i32 |
| %or = or i32 %5, %land.ext |
| store volatile i32 %or, ptr @b, align 4 |
| %div = sdiv i32 %1, %2 |
| %6 = load volatile i32, ptr @d, align 4 |
| %tobool4.not = icmp eq i32 %6, 0 |
| br i1 %tobool4.not, label %land.end7, label %land.rhs5 |
| |
| land.rhs5: ; preds = %lor.end |
| %7 = load volatile i32, ptr @c, align 4 |
| %tobool6 = icmp ne i32 %7, 0 |
| %phi.cast11 = zext i1 %tobool6 to i32 |
| br label %land.end7 |
| |
| land.end7: ; preds = %land.rhs5, %lor.end |
| %8 = phi i32 [ 0, %lor.end ], [ %phi.cast11, %land.rhs5 ] |
| %or9 = or i32 %8, %div |
| store i32 %or9, ptr @a, align 4 |
| br label %if.end |
| |
| if.end: ; preds = %land.end7, %entry |
| ret i32 0 |
| } |