| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc < %s -mtriple=arm-eabi -mattr=+neon -mcpu=cortex-a8 | FileCheck %s |
| |
| define <8 x i8> @v_andi8(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_andi8: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vldr d16, [r1] |
| ; CHECK-NEXT: vldr d17, [r0] |
| ; CHECK-NEXT: vand d16, d17, d16 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <8 x i8>, ptr %A |
| %tmp2 = load <8 x i8>, ptr %B |
| %tmp3 = and <8 x i8> %tmp1, %tmp2 |
| ret <8 x i8> %tmp3 |
| } |
| |
| define <4 x i16> @v_andi16(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_andi16: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vldr d16, [r1] |
| ; CHECK-NEXT: vldr d17, [r0] |
| ; CHECK-NEXT: vand d16, d17, d16 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <4 x i16>, ptr %A |
| %tmp2 = load <4 x i16>, ptr %B |
| %tmp3 = and <4 x i16> %tmp1, %tmp2 |
| ret <4 x i16> %tmp3 |
| } |
| |
| define <2 x i32> @v_andi32(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_andi32: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vldr d16, [r1] |
| ; CHECK-NEXT: vldr d17, [r0] |
| ; CHECK-NEXT: vand d16, d17, d16 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <2 x i32>, ptr %A |
| %tmp2 = load <2 x i32>, ptr %B |
| %tmp3 = and <2 x i32> %tmp1, %tmp2 |
| ret <2 x i32> %tmp3 |
| } |
| |
| define <1 x i64> @v_andi64(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_andi64: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vldr d16, [r1] |
| ; CHECK-NEXT: vldr d17, [r0] |
| ; CHECK-NEXT: vand d16, d17, d16 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <1 x i64>, ptr %A |
| %tmp2 = load <1 x i64>, ptr %B |
| %tmp3 = and <1 x i64> %tmp1, %tmp2 |
| ret <1 x i64> %tmp3 |
| } |
| |
| define <16 x i8> @v_andQi8(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_andQi8: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] |
| ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] |
| ; CHECK-NEXT: vand q8, q9, q8 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: vmov r2, r3, d17 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <16 x i8>, ptr %A |
| %tmp2 = load <16 x i8>, ptr %B |
| %tmp3 = and <16 x i8> %tmp1, %tmp2 |
| ret <16 x i8> %tmp3 |
| } |
| |
| define <8 x i16> @v_andQi16(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_andQi16: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] |
| ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] |
| ; CHECK-NEXT: vand q8, q9, q8 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: vmov r2, r3, d17 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <8 x i16>, ptr %A |
| %tmp2 = load <8 x i16>, ptr %B |
| %tmp3 = and <8 x i16> %tmp1, %tmp2 |
| ret <8 x i16> %tmp3 |
| } |
| |
| define <4 x i32> @v_andQi32(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_andQi32: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] |
| ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] |
| ; CHECK-NEXT: vand q8, q9, q8 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: vmov r2, r3, d17 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <4 x i32>, ptr %A |
| %tmp2 = load <4 x i32>, ptr %B |
| %tmp3 = and <4 x i32> %tmp1, %tmp2 |
| ret <4 x i32> %tmp3 |
| } |
| |
| define <2 x i64> @v_andQi64(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_andQi64: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] |
| ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] |
| ; CHECK-NEXT: vand q8, q9, q8 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: vmov r2, r3, d17 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <2 x i64>, ptr %A |
| %tmp2 = load <2 x i64>, ptr %B |
| %tmp3 = and <2 x i64> %tmp1, %tmp2 |
| ret <2 x i64> %tmp3 |
| } |
| |
| define <8 x i8> @v_bici8(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_bici8: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vldr d16, [r1] |
| ; CHECK-NEXT: vldr d17, [r0] |
| ; CHECK-NEXT: vbic d16, d17, d16 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <8 x i8>, ptr %A |
| %tmp2 = load <8 x i8>, ptr %B |
| %tmp3 = xor <8 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > |
| %tmp4 = and <8 x i8> %tmp1, %tmp3 |
| ret <8 x i8> %tmp4 |
| } |
| |
| define <4 x i16> @v_bici16(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_bici16: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vldr d16, [r1] |
| ; CHECK-NEXT: vldr d17, [r0] |
| ; CHECK-NEXT: vbic d16, d17, d16 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <4 x i16>, ptr %A |
| %tmp2 = load <4 x i16>, ptr %B |
| %tmp3 = xor <4 x i16> %tmp2, < i16 -1, i16 -1, i16 -1, i16 -1 > |
| %tmp4 = and <4 x i16> %tmp1, %tmp3 |
| ret <4 x i16> %tmp4 |
| } |
| |
| define <2 x i32> @v_bici32(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_bici32: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vldr d16, [r1] |
| ; CHECK-NEXT: vldr d17, [r0] |
| ; CHECK-NEXT: vbic d16, d17, d16 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <2 x i32>, ptr %A |
| %tmp2 = load <2 x i32>, ptr %B |
| %tmp3 = xor <2 x i32> %tmp2, < i32 -1, i32 -1 > |
| %tmp4 = and <2 x i32> %tmp1, %tmp3 |
| ret <2 x i32> %tmp4 |
| } |
| |
| define <1 x i64> @v_bici64(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_bici64: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vldr d16, [r1] |
| ; CHECK-NEXT: vldr d17, [r0] |
| ; CHECK-NEXT: vbic d16, d17, d16 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <1 x i64>, ptr %A |
| %tmp2 = load <1 x i64>, ptr %B |
| %tmp3 = xor <1 x i64> %tmp2, < i64 -1 > |
| %tmp4 = and <1 x i64> %tmp1, %tmp3 |
| ret <1 x i64> %tmp4 |
| } |
| |
| define <16 x i8> @v_bicQi8(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_bicQi8: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] |
| ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] |
| ; CHECK-NEXT: vbic q8, q9, q8 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: vmov r2, r3, d17 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <16 x i8>, ptr %A |
| %tmp2 = load <16 x i8>, ptr %B |
| %tmp3 = xor <16 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > |
| %tmp4 = and <16 x i8> %tmp1, %tmp3 |
| ret <16 x i8> %tmp4 |
| } |
| |
| define <8 x i16> @v_bicQi16(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_bicQi16: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] |
| ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] |
| ; CHECK-NEXT: vbic q8, q9, q8 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: vmov r2, r3, d17 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <8 x i16>, ptr %A |
| %tmp2 = load <8 x i16>, ptr %B |
| %tmp3 = xor <8 x i16> %tmp2, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 > |
| %tmp4 = and <8 x i16> %tmp1, %tmp3 |
| ret <8 x i16> %tmp4 |
| } |
| |
| define <4 x i32> @v_bicQi32(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_bicQi32: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] |
| ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] |
| ; CHECK-NEXT: vbic q8, q9, q8 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: vmov r2, r3, d17 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <4 x i32>, ptr %A |
| %tmp2 = load <4 x i32>, ptr %B |
| %tmp3 = xor <4 x i32> %tmp2, < i32 -1, i32 -1, i32 -1, i32 -1 > |
| %tmp4 = and <4 x i32> %tmp1, %tmp3 |
| ret <4 x i32> %tmp4 |
| } |
| |
| define <2 x i64> @v_bicQi64(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_bicQi64: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] |
| ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] |
| ; CHECK-NEXT: vbic q8, q9, q8 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: vmov r2, r3, d17 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <2 x i64>, ptr %A |
| %tmp2 = load <2 x i64>, ptr %B |
| %tmp3 = xor <2 x i64> %tmp2, < i64 -1, i64 -1 > |
| %tmp4 = and <2 x i64> %tmp1, %tmp3 |
| ret <2 x i64> %tmp4 |
| } |
| |
| define <8 x i8> @v_eori8(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_eori8: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vldr d16, [r1] |
| ; CHECK-NEXT: vldr d17, [r0] |
| ; CHECK-NEXT: veor d16, d17, d16 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <8 x i8>, ptr %A |
| %tmp2 = load <8 x i8>, ptr %B |
| %tmp3 = xor <8 x i8> %tmp1, %tmp2 |
| ret <8 x i8> %tmp3 |
| } |
| |
| define <4 x i16> @v_eori16(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_eori16: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vldr d16, [r1] |
| ; CHECK-NEXT: vldr d17, [r0] |
| ; CHECK-NEXT: veor d16, d17, d16 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <4 x i16>, ptr %A |
| %tmp2 = load <4 x i16>, ptr %B |
| %tmp3 = xor <4 x i16> %tmp1, %tmp2 |
| ret <4 x i16> %tmp3 |
| } |
| |
| define <2 x i32> @v_eori32(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_eori32: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vldr d16, [r1] |
| ; CHECK-NEXT: vldr d17, [r0] |
| ; CHECK-NEXT: veor d16, d17, d16 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <2 x i32>, ptr %A |
| %tmp2 = load <2 x i32>, ptr %B |
| %tmp3 = xor <2 x i32> %tmp1, %tmp2 |
| ret <2 x i32> %tmp3 |
| } |
| |
| define <1 x i64> @v_eori64(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_eori64: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vldr d16, [r1] |
| ; CHECK-NEXT: vldr d17, [r0] |
| ; CHECK-NEXT: veor d16, d17, d16 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <1 x i64>, ptr %A |
| %tmp2 = load <1 x i64>, ptr %B |
| %tmp3 = xor <1 x i64> %tmp1, %tmp2 |
| ret <1 x i64> %tmp3 |
| } |
| |
| define <16 x i8> @v_eorQi8(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_eorQi8: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] |
| ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] |
| ; CHECK-NEXT: veor q8, q9, q8 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: vmov r2, r3, d17 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <16 x i8>, ptr %A |
| %tmp2 = load <16 x i8>, ptr %B |
| %tmp3 = xor <16 x i8> %tmp1, %tmp2 |
| ret <16 x i8> %tmp3 |
| } |
| |
| define <8 x i16> @v_eorQi16(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_eorQi16: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] |
| ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] |
| ; CHECK-NEXT: veor q8, q9, q8 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: vmov r2, r3, d17 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <8 x i16>, ptr %A |
| %tmp2 = load <8 x i16>, ptr %B |
| %tmp3 = xor <8 x i16> %tmp1, %tmp2 |
| ret <8 x i16> %tmp3 |
| } |
| |
| define <4 x i32> @v_eorQi32(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_eorQi32: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] |
| ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] |
| ; CHECK-NEXT: veor q8, q9, q8 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: vmov r2, r3, d17 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <4 x i32>, ptr %A |
| %tmp2 = load <4 x i32>, ptr %B |
| %tmp3 = xor <4 x i32> %tmp1, %tmp2 |
| ret <4 x i32> %tmp3 |
| } |
| |
| define <2 x i64> @v_eorQi64(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_eorQi64: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] |
| ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] |
| ; CHECK-NEXT: veor q8, q9, q8 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: vmov r2, r3, d17 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <2 x i64>, ptr %A |
| %tmp2 = load <2 x i64>, ptr %B |
| %tmp3 = xor <2 x i64> %tmp1, %tmp2 |
| ret <2 x i64> %tmp3 |
| } |
| |
| define <8 x i8> @v_mvni8(ptr %A) nounwind { |
| ; CHECK-LABEL: v_mvni8: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vldr d16, [r0] |
| ; CHECK-NEXT: vmvn d16, d16 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <8 x i8>, ptr %A |
| %tmp2 = xor <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > |
| ret <8 x i8> %tmp2 |
| } |
| |
| define <4 x i16> @v_mvni16(ptr %A) nounwind { |
| ; CHECK-LABEL: v_mvni16: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vldr d16, [r0] |
| ; CHECK-NEXT: vmvn d16, d16 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <4 x i16>, ptr %A |
| %tmp2 = xor <4 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1 > |
| ret <4 x i16> %tmp2 |
| } |
| |
| define <2 x i32> @v_mvni32(ptr %A) nounwind { |
| ; CHECK-LABEL: v_mvni32: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vldr d16, [r0] |
| ; CHECK-NEXT: vmvn d16, d16 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <2 x i32>, ptr %A |
| %tmp2 = xor <2 x i32> %tmp1, < i32 -1, i32 -1 > |
| ret <2 x i32> %tmp2 |
| } |
| |
| define <1 x i64> @v_mvni64(ptr %A) nounwind { |
| ; CHECK-LABEL: v_mvni64: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vldr d16, [r0] |
| ; CHECK-NEXT: vmvn d16, d16 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <1 x i64>, ptr %A |
| %tmp2 = xor <1 x i64> %tmp1, < i64 -1 > |
| ret <1 x i64> %tmp2 |
| } |
| |
| define <16 x i8> @v_mvnQi8(ptr %A) nounwind { |
| ; CHECK-LABEL: v_mvnQi8: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] |
| ; CHECK-NEXT: vmvn q8, q8 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: vmov r2, r3, d17 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <16 x i8>, ptr %A |
| %tmp2 = xor <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > |
| ret <16 x i8> %tmp2 |
| } |
| |
| define <8 x i16> @v_mvnQi16(ptr %A) nounwind { |
| ; CHECK-LABEL: v_mvnQi16: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] |
| ; CHECK-NEXT: vmvn q8, q8 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: vmov r2, r3, d17 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <8 x i16>, ptr %A |
| %tmp2 = xor <8 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 > |
| ret <8 x i16> %tmp2 |
| } |
| |
| define <4 x i32> @v_mvnQi32(ptr %A) nounwind { |
| ; CHECK-LABEL: v_mvnQi32: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] |
| ; CHECK-NEXT: vmvn q8, q8 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: vmov r2, r3, d17 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <4 x i32>, ptr %A |
| %tmp2 = xor <4 x i32> %tmp1, < i32 -1, i32 -1, i32 -1, i32 -1 > |
| ret <4 x i32> %tmp2 |
| } |
| |
| define <2 x i64> @v_mvnQi64(ptr %A) nounwind { |
| ; CHECK-LABEL: v_mvnQi64: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] |
| ; CHECK-NEXT: vmvn q8, q8 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: vmov r2, r3, d17 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <2 x i64>, ptr %A |
| %tmp2 = xor <2 x i64> %tmp1, < i64 -1, i64 -1 > |
| ret <2 x i64> %tmp2 |
| } |
| |
| define <8 x i8> @v_orri8(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_orri8: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vldr d16, [r1] |
| ; CHECK-NEXT: vldr d17, [r0] |
| ; CHECK-NEXT: vorr d16, d17, d16 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <8 x i8>, ptr %A |
| %tmp2 = load <8 x i8>, ptr %B |
| %tmp3 = or <8 x i8> %tmp1, %tmp2 |
| ret <8 x i8> %tmp3 |
| } |
| |
| define <4 x i16> @v_orri16(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_orri16: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vldr d16, [r1] |
| ; CHECK-NEXT: vldr d17, [r0] |
| ; CHECK-NEXT: vorr d16, d17, d16 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <4 x i16>, ptr %A |
| %tmp2 = load <4 x i16>, ptr %B |
| %tmp3 = or <4 x i16> %tmp1, %tmp2 |
| ret <4 x i16> %tmp3 |
| } |
| |
| define <2 x i32> @v_orri32(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_orri32: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vldr d16, [r1] |
| ; CHECK-NEXT: vldr d17, [r0] |
| ; CHECK-NEXT: vorr d16, d17, d16 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <2 x i32>, ptr %A |
| %tmp2 = load <2 x i32>, ptr %B |
| %tmp3 = or <2 x i32> %tmp1, %tmp2 |
| ret <2 x i32> %tmp3 |
| } |
| |
| define <1 x i64> @v_orri64(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_orri64: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vldr d16, [r1] |
| ; CHECK-NEXT: vldr d17, [r0] |
| ; CHECK-NEXT: vorr d16, d17, d16 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <1 x i64>, ptr %A |
| %tmp2 = load <1 x i64>, ptr %B |
| %tmp3 = or <1 x i64> %tmp1, %tmp2 |
| ret <1 x i64> %tmp3 |
| } |
| |
| define <16 x i8> @v_orrQi8(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_orrQi8: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] |
| ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] |
| ; CHECK-NEXT: vorr q8, q9, q8 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: vmov r2, r3, d17 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <16 x i8>, ptr %A |
| %tmp2 = load <16 x i8>, ptr %B |
| %tmp3 = or <16 x i8> %tmp1, %tmp2 |
| ret <16 x i8> %tmp3 |
| } |
| |
| define <8 x i16> @v_orrQi16(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_orrQi16: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] |
| ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] |
| ; CHECK-NEXT: vorr q8, q9, q8 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: vmov r2, r3, d17 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <8 x i16>, ptr %A |
| %tmp2 = load <8 x i16>, ptr %B |
| %tmp3 = or <8 x i16> %tmp1, %tmp2 |
| ret <8 x i16> %tmp3 |
| } |
| |
| define <4 x i32> @v_orrQi32(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_orrQi32: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] |
| ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] |
| ; CHECK-NEXT: vorr q8, q9, q8 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: vmov r2, r3, d17 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <4 x i32>, ptr %A |
| %tmp2 = load <4 x i32>, ptr %B |
| %tmp3 = or <4 x i32> %tmp1, %tmp2 |
| ret <4 x i32> %tmp3 |
| } |
| |
| define <2 x i64> @v_orrQi64(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_orrQi64: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] |
| ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] |
| ; CHECK-NEXT: vorr q8, q9, q8 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: vmov r2, r3, d17 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <2 x i64>, ptr %A |
| %tmp2 = load <2 x i64>, ptr %B |
| %tmp3 = or <2 x i64> %tmp1, %tmp2 |
| ret <2 x i64> %tmp3 |
| } |
| |
| define <8 x i8> @v_orni8(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_orni8: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vldr d16, [r1] |
| ; CHECK-NEXT: vldr d17, [r0] |
| ; CHECK-NEXT: vorn d16, d17, d16 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <8 x i8>, ptr %A |
| %tmp2 = load <8 x i8>, ptr %B |
| %tmp3 = xor <8 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > |
| %tmp4 = or <8 x i8> %tmp1, %tmp3 |
| ret <8 x i8> %tmp4 |
| } |
| |
| define <4 x i16> @v_orni16(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_orni16: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vldr d16, [r1] |
| ; CHECK-NEXT: vldr d17, [r0] |
| ; CHECK-NEXT: vorn d16, d17, d16 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <4 x i16>, ptr %A |
| %tmp2 = load <4 x i16>, ptr %B |
| %tmp3 = xor <4 x i16> %tmp2, < i16 -1, i16 -1, i16 -1, i16 -1 > |
| %tmp4 = or <4 x i16> %tmp1, %tmp3 |
| ret <4 x i16> %tmp4 |
| } |
| |
| define <2 x i32> @v_orni32(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_orni32: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vldr d16, [r1] |
| ; CHECK-NEXT: vldr d17, [r0] |
| ; CHECK-NEXT: vorn d16, d17, d16 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <2 x i32>, ptr %A |
| %tmp2 = load <2 x i32>, ptr %B |
| %tmp3 = xor <2 x i32> %tmp2, < i32 -1, i32 -1 > |
| %tmp4 = or <2 x i32> %tmp1, %tmp3 |
| ret <2 x i32> %tmp4 |
| } |
| |
| define <1 x i64> @v_orni64(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_orni64: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vldr d16, [r1] |
| ; CHECK-NEXT: vldr d17, [r0] |
| ; CHECK-NEXT: vorn d16, d17, d16 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <1 x i64>, ptr %A |
| %tmp2 = load <1 x i64>, ptr %B |
| %tmp3 = xor <1 x i64> %tmp2, < i64 -1 > |
| %tmp4 = or <1 x i64> %tmp1, %tmp3 |
| ret <1 x i64> %tmp4 |
| } |
| |
| define <16 x i8> @v_ornQi8(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_ornQi8: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] |
| ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] |
| ; CHECK-NEXT: vorn q8, q9, q8 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: vmov r2, r3, d17 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <16 x i8>, ptr %A |
| %tmp2 = load <16 x i8>, ptr %B |
| %tmp3 = xor <16 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > |
| %tmp4 = or <16 x i8> %tmp1, %tmp3 |
| ret <16 x i8> %tmp4 |
| } |
| |
| define <8 x i16> @v_ornQi16(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_ornQi16: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] |
| ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] |
| ; CHECK-NEXT: vorn q8, q9, q8 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: vmov r2, r3, d17 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <8 x i16>, ptr %A |
| %tmp2 = load <8 x i16>, ptr %B |
| %tmp3 = xor <8 x i16> %tmp2, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 > |
| %tmp4 = or <8 x i16> %tmp1, %tmp3 |
| ret <8 x i16> %tmp4 |
| } |
| |
| define <4 x i32> @v_ornQi32(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_ornQi32: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] |
| ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] |
| ; CHECK-NEXT: vorn q8, q9, q8 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: vmov r2, r3, d17 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <4 x i32>, ptr %A |
| %tmp2 = load <4 x i32>, ptr %B |
| %tmp3 = xor <4 x i32> %tmp2, < i32 -1, i32 -1, i32 -1, i32 -1 > |
| %tmp4 = or <4 x i32> %tmp1, %tmp3 |
| ret <4 x i32> %tmp4 |
| } |
| |
| define <2 x i64> @v_ornQi64(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: v_ornQi64: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] |
| ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] |
| ; CHECK-NEXT: vorn q8, q9, q8 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: vmov r2, r3, d17 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <2 x i64>, ptr %A |
| %tmp2 = load <2 x i64>, ptr %B |
| %tmp3 = xor <2 x i64> %tmp2, < i64 -1, i64 -1 > |
| %tmp4 = or <2 x i64> %tmp1, %tmp3 |
| ret <2 x i64> %tmp4 |
| } |
| |
| define <8 x i8> @vtsti8(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: vtsti8: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vldr d16, [r1] |
| ; CHECK-NEXT: vldr d17, [r0] |
| ; CHECK-NEXT: vtst.8 d16, d17, d16 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <8 x i8>, ptr %A |
| %tmp2 = load <8 x i8>, ptr %B |
| %tmp3 = and <8 x i8> %tmp1, %tmp2 |
| %tmp4 = icmp ne <8 x i8> %tmp3, zeroinitializer |
| %tmp5 = sext <8 x i1> %tmp4 to <8 x i8> |
| ret <8 x i8> %tmp5 |
| } |
| |
| define <4 x i16> @vtsti16(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: vtsti16: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vldr d16, [r1] |
| ; CHECK-NEXT: vldr d17, [r0] |
| ; CHECK-NEXT: vtst.16 d16, d17, d16 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <4 x i16>, ptr %A |
| %tmp2 = load <4 x i16>, ptr %B |
| %tmp3 = and <4 x i16> %tmp1, %tmp2 |
| %tmp4 = icmp ne <4 x i16> %tmp3, zeroinitializer |
| %tmp5 = sext <4 x i1> %tmp4 to <4 x i16> |
| ret <4 x i16> %tmp5 |
| } |
| |
| define <2 x i32> @vtsti32(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: vtsti32: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vldr d16, [r1] |
| ; CHECK-NEXT: vldr d17, [r0] |
| ; CHECK-NEXT: vtst.32 d16, d17, d16 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <2 x i32>, ptr %A |
| %tmp2 = load <2 x i32>, ptr %B |
| %tmp3 = and <2 x i32> %tmp1, %tmp2 |
| %tmp4 = icmp ne <2 x i32> %tmp3, zeroinitializer |
| %tmp5 = sext <2 x i1> %tmp4 to <2 x i32> |
| ret <2 x i32> %tmp5 |
| } |
| |
| define <16 x i8> @vtstQi8(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: vtstQi8: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] |
| ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] |
| ; CHECK-NEXT: vtst.8 q8, q9, q8 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: vmov r2, r3, d17 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <16 x i8>, ptr %A |
| %tmp2 = load <16 x i8>, ptr %B |
| %tmp3 = and <16 x i8> %tmp1, %tmp2 |
| %tmp4 = icmp ne <16 x i8> %tmp3, zeroinitializer |
| %tmp5 = sext <16 x i1> %tmp4 to <16 x i8> |
| ret <16 x i8> %tmp5 |
| } |
| |
| define <8 x i16> @vtstQi16(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: vtstQi16: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] |
| ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] |
| ; CHECK-NEXT: vtst.16 q8, q9, q8 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: vmov r2, r3, d17 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <8 x i16>, ptr %A |
| %tmp2 = load <8 x i16>, ptr %B |
| %tmp3 = and <8 x i16> %tmp1, %tmp2 |
| %tmp4 = icmp ne <8 x i16> %tmp3, zeroinitializer |
| %tmp5 = sext <8 x i1> %tmp4 to <8 x i16> |
| ret <8 x i16> %tmp5 |
| } |
| |
| define <4 x i32> @vtstQi32(ptr %A, ptr %B) nounwind { |
| ; CHECK-LABEL: vtstQi32: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] |
| ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] |
| ; CHECK-NEXT: vtst.32 q8, q9, q8 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: vmov r2, r3, d17 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <4 x i32>, ptr %A |
| %tmp2 = load <4 x i32>, ptr %B |
| %tmp3 = and <4 x i32> %tmp1, %tmp2 |
| %tmp4 = icmp ne <4 x i32> %tmp3, zeroinitializer |
| %tmp5 = sext <4 x i1> %tmp4 to <4 x i32> |
| ret <4 x i32> %tmp5 |
| } |
| |
| define <8 x i8> @v_orrimm(ptr %A) nounwind { |
| ; CHECK-LABEL: v_orrimm: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vldr d16, [r0] |
| ; CHECK-NEXT: vorr.i32 d16, #0x1000000 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <8 x i8>, ptr %A |
| %tmp3 = or <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1> |
| ret <8 x i8> %tmp3 |
| } |
| |
| define <16 x i8> @v_orrimmQ(ptr %A) nounwind { |
| ; CHECK-LABEL: v_orrimmQ: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] |
| ; CHECK-NEXT: vorr.i32 q8, #0x1000000 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: vmov r2, r3, d17 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <16 x i8>, ptr %A |
| %tmp3 = or <16 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1> |
| ret <16 x i8> %tmp3 |
| } |
| |
| define <8 x i8> @v_bicimm(ptr %A) nounwind { |
| ; CHECK-LABEL: v_bicimm: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vldr d16, [r0] |
| ; CHECK-NEXT: vbic.i32 d16, #0xff000000 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <8 x i8>, ptr %A |
| %tmp3 = and <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 > |
| ret <8 x i8> %tmp3 |
| } |
| |
| define <16 x i8> @v_bicimmQ(ptr %A) nounwind { |
| ; CHECK-LABEL: v_bicimmQ: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] |
| ; CHECK-NEXT: vbic.i32 q8, #0xff000000 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: vmov r2, r3, d17 |
| ; CHECK-NEXT: bx lr |
| %tmp1 = load <16 x i8>, ptr %A |
| %tmp3 = and <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 > |
| ret <16 x i8> %tmp3 |
| } |
| |
| define <4 x i32> @hidden_not_v4i32(<4 x i32> %x) nounwind { |
| ; CHECK-LABEL: hidden_not_v4i32: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vmov d19, r2, r3 |
| ; CHECK-NEXT: vmov.i32 q8, #0x6 |
| ; CHECK-NEXT: vmov d18, r0, r1 |
| ; CHECK-NEXT: vbic q8, q8, q9 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: vmov r2, r3, d17 |
| ; CHECK-NEXT: bx lr |
| %xor = xor <4 x i32> %x, <i32 15, i32 15, i32 15, i32 15> |
| %and = and <4 x i32> %xor, <i32 6, i32 6, i32 6, i32 6> |
| ret <4 x i32> %and |
| } |
| |