| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # |
| # Check that we can select G_UZP1 and G_UZP2 via the tablegen importer. |
| # |
| # RUN: llc -mtriple aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s |
| |
| ... |
| --- |
| name: uzp1_v4s32 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.1.entry: |
| liveins: $q0, $q1 |
| |
| ; CHECK-LABEL: name: uzp1_v4s32 |
| ; CHECK: liveins: $q0, $q1 |
| ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 |
| ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 |
| ; CHECK: [[UZP1v4i32_:%[0-9]+]]:fpr128 = UZP1v4i32 [[COPY]], [[COPY1]] |
| ; CHECK: $q0 = COPY [[UZP1v4i32_]] |
| ; CHECK: RET_ReallyLR implicit $q0 |
| %0:fpr(<4 x s32>) = COPY $q0 |
| %1:fpr(<4 x s32>) = COPY $q1 |
| %2:fpr(<4 x s32>) = G_UZP1 %0, %1 |
| $q0 = COPY %2(<4 x s32>) |
| RET_ReallyLR implicit $q0 |
| |
| ... |
| --- |
| name: uzp2_v4s32 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.1.entry: |
| liveins: $q0, $q1 |
| |
| ; CHECK-LABEL: name: uzp2_v4s32 |
| ; CHECK: liveins: $q0, $q1 |
| ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 |
| ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 |
| ; CHECK: [[UZP2v4i32_:%[0-9]+]]:fpr128 = UZP2v4i32 [[COPY]], [[COPY1]] |
| ; CHECK: $q0 = COPY [[UZP2v4i32_]] |
| ; CHECK: RET_ReallyLR implicit $q0 |
| %0:fpr(<4 x s32>) = COPY $q0 |
| %1:fpr(<4 x s32>) = COPY $q1 |
| %2:fpr(<4 x s32>) = G_UZP2 %0, %1 |
| $q0 = COPY %2(<4 x s32>) |
| RET_ReallyLR implicit $q0 |
| |
| ... |