llvm/test/CodeGen/AArch64/GlobalISel/select-store-truncating-float.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- |
  define void @truncating_f32(double %x) {
    %alloca = alloca i32, align 4
    %bitcast = bitcast double %x to i64
    %trunc = trunc i64 %bitcast to i32
    store i32 %trunc, i32* %alloca, align 4
    ret void
  }

  define void @truncating_f16(double %x) {
    %alloca = alloca i16, align 2
    %bitcast = bitcast double %x to i64
    %trunc = trunc i64 %bitcast to i16
    store i16 %trunc, i16* %alloca, align 2
    ret void
  }

  define void @truncating_f8(double %x) {
    %alloca = alloca i8, align 1
    %bitcast = bitcast double %x to i64
    %trunc = trunc i64 %bitcast to i8
    store i8 %trunc, i8* %alloca, align 1
    ret void
  }

...
---
name:            truncating_f32
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
liveins:
  - { reg: '$d0' }
frameInfo:
  maxAlignment:    4
stack:
  - { id: 0, name: alloca, size: 4, alignment: 4 }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0

    ; CHECK-LABEL: name: truncating_f32
    ; CHECK: liveins: $d0
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]].ssub
    ; CHECK: STRSui [[COPY1]], %stack.0.alloca, 0 :: (store (s32) into %ir.alloca)
    ; CHECK: RET_ReallyLR
    %0:fpr(s64) = COPY $d0
    %1:gpr(p0) = G_FRAME_INDEX %stack.0.alloca
    G_STORE %0(s64), %1(p0) :: (store (s32) into %ir.alloca)
    RET_ReallyLR

...
---
name:            truncating_f16
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
liveins:
  - { reg: '$d0' }
frameInfo:
  maxAlignment:    2
stack:
  - { id: 0, name: alloca, size: 2, alignment: 2 }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0

    ; CHECK-LABEL: name: truncating_f16
    ; CHECK: liveins: $d0
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr16 = COPY [[COPY]].hsub
    ; CHECK: STRHui [[COPY1]], %stack.0.alloca, 0 :: (store (s16) into %ir.alloca)
    ; CHECK: RET_ReallyLR
    %0:fpr(s64) = COPY $d0
    %1:gpr(p0) = G_FRAME_INDEX %stack.0.alloca
    G_STORE %0(s64), %1(p0) :: (store (s16) into %ir.alloca)
    RET_ReallyLR

...
---
name:            truncating_f8
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
liveins:
  - { reg: '$d0' }
frameInfo:
  maxAlignment:    1
stack:
  - { id: 0, name: alloca, size: 1, alignment: 1 }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0

    ; CHECK-LABEL: name: truncating_f8
    ; CHECK: liveins: $d0
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr8 = COPY [[COPY]].bsub
    ; CHECK: STRBui [[COPY1]], %stack.0.alloca, 0 :: (store (s8) into %ir.alloca)
    ; CHECK: RET_ReallyLR
    %0:fpr(s64) = COPY $d0
    %1:gpr(p0) = G_FRAME_INDEX %stack.0.alloca
    G_STORE %0(s64), %1(p0) :: (store (s8) into %ir.alloca)
    RET_ReallyLR

...