llvm/test/CodeGen/AArch64/GlobalISel/select-bitreverse.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s

...
---
name:            s32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $w0

    ; CHECK-LABEL: name: s32
    ; CHECK: liveins: $w0
    ; CHECK: %copy:gpr32 = COPY $w0
    ; CHECK: %bitreverse:gpr32 = RBITWr %copy
    ; CHECK: $w0 = COPY %bitreverse
    ; CHECK: RET_ReallyLR implicit $w0
    %copy:gpr(s32) = COPY $w0
    %bitreverse:gpr(s32) = G_BITREVERSE %copy
    $w0 = COPY %bitreverse(s32)
    RET_ReallyLR implicit $w0

...
---
name:            s64
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: s64
    ; CHECK: liveins: $x0
    ; CHECK: %copy:gpr64 = COPY $x0
    ; CHECK: %bitreverse:gpr64 = RBITXr %copy
    ; CHECK: $x0 = COPY %bitreverse
    ; CHECK: RET_ReallyLR implicit $x0
    %copy:gpr(s64) = COPY $x0
    %bitreverse:gpr(s64) = G_BITREVERSE %copy
    $x0 = COPY %bitreverse(s64)
    RET_ReallyLR implicit $x0

...
---
name:            v8s8_legal
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: v8s8_legal
    ; CHECK: liveins: $x0
    ; CHECK: %vec:fpr64 = IMPLICIT_DEF
    ; CHECK: %bitreverse:fpr64 = RBITv8i8 %vec
    ; CHECK: $x0 = COPY %bitreverse
    ; CHECK: RET_ReallyLR implicit $x0
    %vec:fpr(<8 x s8>) = G_IMPLICIT_DEF
    %bitreverse:fpr(<8 x s8>) = G_BITREVERSE %vec
    $x0 = COPY %bitreverse(<8 x s8>)
    RET_ReallyLR implicit $x0

...
---
name:            v16s8_legal
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $q0

    ; CHECK-LABEL: name: v16s8_legal
    ; CHECK: liveins: $q0
    ; CHECK: %vec:fpr128 = IMPLICIT_DEF
    ; CHECK: %bitreverse:fpr128 = RBITv16i8 %vec
    ; CHECK: $q0 = COPY %bitreverse
    ; CHECK: RET_ReallyLR implicit $q0
    %vec:fpr(<16 x s8>) = G_IMPLICIT_DEF
    %bitreverse:fpr(<16 x s8>) = G_BITREVERSE %vec
    $q0 = COPY %bitreverse(<16 x s8>)
    RET_ReallyLR implicit $q0

...