llvm/test/CodeGen/AArch64/GlobalISel/regbank-llround.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s

...
---
name:            no_cross_bank_copies_needed
legalized:       true
regBankSelected: false
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $d0
    ; CHECK-LABEL: name: no_cross_bank_copies_needed
    ; CHECK: liveins: $d0
    ; CHECK: %fpr:fpr(s64) = COPY $d0
    ; CHECK: %llround:gpr(s64) = G_LLROUND %fpr(s64)
    ; CHECK: $d0 = COPY %llround(s64)
    ; CHECK: RET_ReallyLR implicit $s0
    %fpr:_(s64) = COPY $d0
    %llround:_(s64) = G_LLROUND %fpr
    $d0 = COPY %llround:_(s64)
    RET_ReallyLR implicit $s0
...
---
name:            source_needs_copy
legalized:       true
regBankSelected: false
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x0
    ; CHECK-LABEL: name: source_needs_copy
    ; CHECK: liveins: $x0
    ; CHECK: %gpr:gpr(s64) = COPY $x0
    ; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY %gpr(s64)
    ; CHECK: %llround:gpr(s64) = G_LLROUND [[COPY]](s64)
    ; CHECK: $d0 = COPY %llround(s64)
    ; CHECK: RET_ReallyLR implicit $s0
    %gpr:_(s64) = COPY $x0
    %llround:_(s64) = G_LLROUND %gpr
    $d0 = COPY %llround:_(s64)
    RET_ReallyLR implicit $s0
...
---
name:            load_gets_fpr
legalized:       true
regBankSelected: false
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x0
    ; CHECK-LABEL: name: load_gets_fpr
    ; CHECK: liveins: $x0
    ; CHECK: %ptr:gpr(p0) = COPY $x0
    ; CHECK: %load:fpr(s32) = G_LOAD %ptr(p0) :: (load (s32))
    ; CHECK: %llround:gpr(s64) = G_LLROUND %load(s32)
    ; CHECK: $d0 = COPY %llround(s64)
    ; CHECK: RET_ReallyLR implicit $s0
    %ptr:_(p0) = COPY $x0
    %load:_(s32) = G_LOAD %ptr(p0) :: (load (s32))
    %llround:_(s64) = G_LLROUND %load
    $d0 = COPY %llround:_(s64)
    RET_ReallyLR implicit $s0

...