llvm/test/CodeGen/AArch64/GlobalISel/regbank-fcmp.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s

...
---
name:            vector
legalized: true
tracksRegLiveness: true
body:             |
  bb.0:
  liveins: $q0, $q1
    ; Vectors should always end up on a FPR.

    ; CHECK-LABEL: name: vector
    ; CHECK: liveins: $q0, $q1
    ; CHECK: %x:fpr(<2 x s64>) = COPY $q0
    ; CHECK: %y:fpr(<2 x s64>) = COPY $q1
    ; CHECK: %fcmp:fpr(<2 x s64>) = G_FCMP floatpred(olt), %x(<2 x s64>), %y
    ; CHECK: $q0 = COPY %fcmp(<2 x s64>)
    ; CHECK: RET_ReallyLR implicit $q0
    %x:_(<2 x s64>) = COPY $q0
    %y:_(<2 x s64>) = COPY $q1
    %fcmp:_(<2 x s64>) = G_FCMP floatpred(olt), %x:_(<2 x s64>), %y:_
    $q0 = COPY %fcmp
    RET_ReallyLR implicit $q0
...