llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=aarch64-- -run-pass=legalizer %s -o - | FileCheck %s
---
name:            test_urem_64
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: test_urem_64
    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
    ; CHECK-NEXT: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[COPY]], [[COPY1]]
    ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[UDIV]], [[COPY1]]
    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[MUL]]
    ; CHECK-NEXT: $x0 = COPY [[SUB]](s64)
    %0:_(s64) = COPY $x0
    %1:_(s64) = COPY $x1
    %2:_(s64) = G_UREM %0, %1
    $x0 = COPY %2(s64)

...
---
name:            test_srem_32
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: test_srem_32
    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
    ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
    ; CHECK-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[TRUNC]], [[TRUNC1]]
    ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SDIV]], [[TRUNC1]]
    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[MUL]]
    ; CHECK-NEXT: $w0 = COPY [[SUB]](s32)
    %0:_(s64) = COPY $x0
    %1:_(s64) = COPY $x1
    %2:_(s32) = G_TRUNC %0(s64)
    %3:_(s32) = G_TRUNC %1(s64)
    %4:_(s32) = G_SREM %2, %3
    $w0 = COPY %4(s32)

...
---
name:            test_srem_8
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: test_srem_8
    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC]], 8
    ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
    ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
    ; CHECK-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
    ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
    ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SDIV]], [[TRUNC2]]
    ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC3]], [[MUL]]
    ; CHECK-NEXT: $w0 = COPY [[SUB]](s32)
    %0:_(s64) = COPY $x0
    %1:_(s64) = COPY $x1
    %2:_(s8) = G_TRUNC %0(s64)
    %3:_(s8) = G_TRUNC %1(s64)
    %4:_(s8) = G_SREM %2, %3
    %5:_(s32) = G_ANYEXT %4(s8)
    $w0 = COPY %5(s32)

...
---
name:            test_frem
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: test_frem
    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
    ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
    ; CHECK-NEXT: $d0 = COPY [[COPY]](s64)
    ; CHECK-NEXT: $d1 = COPY [[COPY1]](s64)
    ; CHECK-NEXT: BL &fmod, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $d1, implicit-def $d0
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0
    ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
    ; CHECK-NEXT: $x0 = COPY [[COPY2]](s64)
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
    ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
    ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
    ; CHECK-NEXT: $s0 = COPY [[TRUNC]](s32)
    ; CHECK-NEXT: $s1 = COPY [[TRUNC1]](s32)
    ; CHECK-NEXT: BL &fmodf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
    ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
    ; CHECK-NEXT: $w0 = COPY [[COPY3]](s32)
    %0:_(s64) = COPY $x0
    %1:_(s64) = COPY $x1
    %2:_(s64) = G_FREM %0, %1
    $x0 = COPY %2(s64)
    %3:_(s32) = G_TRUNC %0(s64)
    %4:_(s32) = G_TRUNC %1(s64)
    %5:_(s32) = G_FREM %3, %4
    $w0 = COPY %5(s32)

...
---
name:            test_srem_v2s32
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: test_srem_v2s32
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
    ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
    ; CHECK-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[UV]], [[UV2]]
    ; CHECK-NEXT: [[SDIV1:%[0-9]+]]:_(s32) = G_SDIV [[UV1]], [[UV3]]
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SDIV]](s32), [[SDIV1]](s32)
    ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<2 x s32>) = G_MUL [[BUILD_VECTOR]], [[COPY1]]
    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<2 x s32>) = G_SUB [[COPY]], [[MUL]]
    ; CHECK-NEXT: $d0 = COPY [[SUB]](<2 x s32>)
    %0:_(<2 x s32>) = COPY $d0
    %1:_(<2 x s32>) = COPY $d1
    %2:_(<2 x s32>) = G_SREM %0, %1
    $d0 = COPY %2(<2 x s32>)

...
---
name:            test_srem_v4s32
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: test_srem_v4s32
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
    ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<4 x s32>)
    ; CHECK-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[UV]], [[UV4]]
    ; CHECK-NEXT: [[UDIV1:%[0-9]+]]:_(s32) = G_UDIV [[UV1]], [[UV5]]
    ; CHECK-NEXT: [[UDIV2:%[0-9]+]]:_(s32) = G_UDIV [[UV2]], [[UV6]]
    ; CHECK-NEXT: [[UDIV3:%[0-9]+]]:_(s32) = G_UDIV [[UV3]], [[UV7]]
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UDIV]](s32), [[UDIV1]](s32), [[UDIV2]](s32), [[UDIV3]](s32)
    ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<4 x s32>) = G_MUL [[BUILD_VECTOR]], [[COPY1]]
    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[COPY]], [[MUL]]
    ; CHECK-NEXT: $q0 = COPY [[SUB]](<4 x s32>)
    %0:_(<4 x s32>) = COPY $q0
    %1:_(<4 x s32>) = COPY $q1
    %2:_(<4 x s32>) = G_UREM %0, %1
    $q0 = COPY %2(<4 x s32>)

...
---
name:            test_srem_v2s64
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: test_srem_v2s64
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
    ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
    ; CHECK-NEXT: [[SDIV:%[0-9]+]]:_(s64) = G_SDIV [[UV]], [[UV2]]
    ; CHECK-NEXT: [[SDIV1:%[0-9]+]]:_(s64) = G_SDIV [[UV1]], [[UV3]]
    ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
    ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[SDIV]], [[UV4]]
    ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(s64) = G_MUL [[SDIV1]], [[UV5]]
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MUL]](s64), [[MUL1]](s64)
    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<2 x s64>) = G_SUB [[COPY]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: $q0 = COPY [[SUB]](<2 x s64>)
    %0:_(<2 x s64>) = COPY $q0
    %1:_(<2 x s64>) = COPY $q1
    %2:_(<2 x s64>) = G_SREM %0, %1
    $q0 = COPY %2(<2 x s64>)

...
---
name:            test_srem_v4s16
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: test_srem_v4s16
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[COPY]](<4 x s16>)
    ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[COPY1]](<4 x s16>)
    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ZEXT]](<4 x s32>)
    ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ZEXT1]](<4 x s32>)
    ; CHECK-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[UV]], [[UV4]]
    ; CHECK-NEXT: [[UDIV1:%[0-9]+]]:_(s32) = G_UDIV [[UV1]], [[UV5]]
    ; CHECK-NEXT: [[UDIV2:%[0-9]+]]:_(s32) = G_UDIV [[UV2]], [[UV6]]
    ; CHECK-NEXT: [[UDIV3:%[0-9]+]]:_(s32) = G_UDIV [[UV3]], [[UV7]]
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UDIV]](s32), [[UDIV1]](s32), [[UDIV2]](s32), [[UDIV3]](s32)
    ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<4 x s32>) = G_MUL [[BUILD_VECTOR]], [[ZEXT1]]
    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[ZEXT]], [[MUL]]
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[SUB]](<4 x s32>)
    ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<4 x s16>)
    %0:_(<4 x s16>) = COPY $d0
    %1:_(<4 x s16>) = COPY $d1
    %2:_(<4 x s16>) = G_UREM %0, %1
    $d0 = COPY %2(<4 x s16>)

...