| //===----------------------------------------------------------------------===// |
| // |
| // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| // See https://llvm.org/LICENSE.txt for license information. |
| // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| // |
| //===----------------------------------------------------------------------===// |
| // Automatically generated file, do not edit! |
| //===----------------------------------------------------------------------===// |
| |
| def A2_abs : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = abs($Rs32)", |
| tc_d61dfdc3, TypeS_2op>, Enc_5e2823 { |
| let Inst{13-5} = 0b000000100; |
| let Inst{31-21} = 0b10001100100; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A2_absp : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32), |
| "$Rdd32 = abs($Rss32)", |
| tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb { |
| let Inst{13-5} = 0b000000110; |
| let Inst{31-21} = 0b10000000100; |
| let prefersSlot3 = 1; |
| } |
| def A2_abssat : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = abs($Rs32):sat", |
| tc_d61dfdc3, TypeS_2op>, Enc_5e2823 { |
| let Inst{13-5} = 0b000000101; |
| let Inst{31-21} = 0b10001100100; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_add : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = add($Rs32,$Rt32)", |
| tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110011000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_add"; |
| let CextOpcode = "A2_add"; |
| let InputType = "reg"; |
| let isCommutable = 1; |
| let isPredicable = 1; |
| } |
| def A2_addh_h16_hh : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = add($Rt32.h,$Rs32.h):<<16", |
| tc_01d44cb2, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b011; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A2_addh_h16_hl : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = add($Rt32.h,$Rs32.l):<<16", |
| tc_01d44cb2, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A2_addh_h16_lh : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = add($Rt32.l,$Rs32.h):<<16", |
| tc_01d44cb2, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b001; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A2_addh_h16_ll : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = add($Rt32.l,$Rs32.l):<<16", |
| tc_01d44cb2, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A2_addh_h16_sat_hh : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = add($Rt32.h,$Rs32.h):sat:<<16", |
| tc_8a825db2, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b111; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_addh_h16_sat_hl : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = add($Rt32.h,$Rs32.l):sat:<<16", |
| tc_8a825db2, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b110; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_addh_h16_sat_lh : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = add($Rt32.l,$Rs32.h):sat:<<16", |
| tc_8a825db2, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b101; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_addh_h16_sat_ll : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = add($Rt32.l,$Rs32.l):sat:<<16", |
| tc_8a825db2, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_addh_l16_hl : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = add($Rt32.l,$Rs32.h)", |
| tc_f34c1c21, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A2_addh_l16_ll : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = add($Rt32.l,$Rs32.l)", |
| tc_f34c1c21, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A2_addh_l16_sat_hl : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = add($Rt32.l,$Rs32.h):sat", |
| tc_8a825db2, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b110; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_addh_l16_sat_ll : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = add($Rt32.l,$Rs32.l):sat", |
| tc_8a825db2, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_addi : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, s32_0Imm:$Ii), |
| "$Rd32 = add($Rs32,#$Ii)", |
| tc_713b66bf, TypeALU32_ADDI>, Enc_cb9321, PredNewRel, ImmRegRel { |
| let Inst{31-28} = 0b1011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_addi"; |
| let CextOpcode = "A2_add"; |
| let InputType = "imm"; |
| let isAdd = 1; |
| let isPredicable = 1; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 16; |
| let opExtentAlign = 0; |
| } |
| def A2_addp : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = add($Rss32,$Rtt32)", |
| tc_5da50c4b, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b111; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011000; |
| let isAdd = 1; |
| let isCommutable = 1; |
| } |
| def A2_addpsat : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = add($Rss32,$Rtt32):sat", |
| tc_8a825db2, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b101; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011011; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| let isCommutable = 1; |
| } |
| def A2_addsat : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = add($Rs32,$Rt32):sat", |
| tc_95a33176, TypeALU32_3op>, Enc_5ab2be { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110110010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| let InputType = "reg"; |
| let isCommutable = 1; |
| } |
| def A2_addsp : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins IntRegs:$Rs32, DoubleRegs:$Rtt32), |
| "$Rdd32 = add($Rs32,$Rtt32)", |
| tc_01d44cb2, TypeALU64> { |
| let isPseudo = 1; |
| } |
| def A2_addsph : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = add($Rss32,$Rtt32):raw:hi", |
| tc_01d44cb2, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b111; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011011; |
| let prefersSlot3 = 1; |
| } |
| def A2_addspl : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = add($Rss32,$Rtt32):raw:lo", |
| tc_01d44cb2, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b110; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011011; |
| let prefersSlot3 = 1; |
| } |
| def A2_and : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = and($Rs32,$Rt32)", |
| tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110001000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_and"; |
| let CextOpcode = "A2_and"; |
| let InputType = "reg"; |
| let isCommutable = 1; |
| let isPredicable = 1; |
| } |
| def A2_andir : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, s32_0Imm:$Ii), |
| "$Rd32 = and($Rs32,#$Ii)", |
| tc_713b66bf, TypeALU32_2op>, Enc_140c83, ImmRegRel { |
| let Inst{31-22} = 0b0111011000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let CextOpcode = "A2_and"; |
| let InputType = "imm"; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 10; |
| let opExtentAlign = 0; |
| } |
| def A2_andp : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = and($Rss32,$Rtt32)", |
| tc_5da50c4b, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011111; |
| let isCommutable = 1; |
| } |
| def A2_aslh : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = aslh($Rs32)", |
| tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-21} = 0b01110000000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_aslh"; |
| let isPredicable = 1; |
| } |
| def A2_asrh : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = asrh($Rs32)", |
| tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-21} = 0b01110000001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_asrh"; |
| let isPredicable = 1; |
| } |
| def A2_combine_hh : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = combine($Rt32.h,$Rs32.h)", |
| tc_713b66bf, TypeALU32_3op>, Enc_bd6011 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110011100; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let InputType = "reg"; |
| } |
| def A2_combine_hl : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = combine($Rt32.h,$Rs32.l)", |
| tc_713b66bf, TypeALU32_3op>, Enc_bd6011 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110011101; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let InputType = "reg"; |
| } |
| def A2_combine_lh : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = combine($Rt32.l,$Rs32.h)", |
| tc_713b66bf, TypeALU32_3op>, Enc_bd6011 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110011110; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let InputType = "reg"; |
| } |
| def A2_combine_ll : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = combine($Rt32.l,$Rs32.l)", |
| tc_713b66bf, TypeALU32_3op>, Enc_bd6011 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110011111; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let InputType = "reg"; |
| } |
| def A2_combineii : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins s32_0Imm:$Ii, s8_0Imm:$II), |
| "$Rdd32 = combine(#$Ii,#$II)", |
| tc_713b66bf, TypeALU32_2op>, Enc_18c338 { |
| let Inst{31-23} = 0b011111000; |
| let isAsCheapAsAMove = 1; |
| let isMoveImm = 1; |
| let isReMaterializable = 1; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 1; |
| let opExtentBits = 8; |
| let opExtentAlign = 0; |
| } |
| def A2_combinew : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rdd32 = combine($Rs32,$Rt32)", |
| tc_713b66bf, TypeALU32_3op>, Enc_be32a5, PredNewRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110101000; |
| let BaseOpcode = "A2_combinew"; |
| let InputType = "reg"; |
| let isPredicable = 1; |
| } |
| def A2_max : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = max($Rs32,$Rt32)", |
| tc_8a825db2, TypeALU64>, Enc_5ab2be { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101110; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A2_maxp : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = max($Rss32,$Rtt32)", |
| tc_8a825db2, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011110; |
| let prefersSlot3 = 1; |
| } |
| def A2_maxu : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = maxu($Rs32,$Rt32)", |
| tc_8a825db2, TypeALU64>, Enc_5ab2be { |
| let Inst{7-5} = 0b100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101110; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A2_maxup : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = maxu($Rss32,$Rtt32)", |
| tc_8a825db2, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b101; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011110; |
| let prefersSlot3 = 1; |
| } |
| def A2_min : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = min($Rt32,$Rs32)", |
| tc_8a825db2, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101101; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A2_minp : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = min($Rtt32,$Rss32)", |
| tc_8a825db2, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b110; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011101; |
| let prefersSlot3 = 1; |
| } |
| def A2_minu : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = minu($Rt32,$Rs32)", |
| tc_8a825db2, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101101; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A2_minup : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = minu($Rtt32,$Rss32)", |
| tc_8a825db2, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b111; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011101; |
| let prefersSlot3 = 1; |
| } |
| def A2_neg : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = neg($Rs32)", |
| tc_c57d9f39, TypeALU32_2op> { |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def A2_negp : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32), |
| "$Rdd32 = neg($Rss32)", |
| tc_9f6cd987, TypeS_2op>, Enc_b9c5fb { |
| let Inst{13-5} = 0b000000101; |
| let Inst{31-21} = 0b10000000100; |
| } |
| def A2_negsat : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = neg($Rs32):sat", |
| tc_d61dfdc3, TypeS_2op>, Enc_5e2823 { |
| let Inst{13-5} = 0b000000110; |
| let Inst{31-21} = 0b10001100100; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_nop : HInst< |
| (outs), |
| (ins), |
| "nop", |
| tc_b837298f, TypeALU32_2op>, Enc_e3b0c4 { |
| let Inst{13-0} = 0b00000000000000; |
| let Inst{31-16} = 0b0111111100000000; |
| } |
| def A2_not : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = not($Rs32)", |
| tc_c57d9f39, TypeALU32_2op> { |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def A2_notp : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32), |
| "$Rdd32 = not($Rss32)", |
| tc_9f6cd987, TypeS_2op>, Enc_b9c5fb { |
| let Inst{13-5} = 0b000000100; |
| let Inst{31-21} = 0b10000000100; |
| } |
| def A2_or : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = or($Rs32,$Rt32)", |
| tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110001001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_or"; |
| let CextOpcode = "A2_or"; |
| let InputType = "reg"; |
| let isCommutable = 1; |
| let isPredicable = 1; |
| } |
| def A2_orir : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, s32_0Imm:$Ii), |
| "$Rd32 = or($Rs32,#$Ii)", |
| tc_713b66bf, TypeALU32_2op>, Enc_140c83, ImmRegRel { |
| let Inst{31-22} = 0b0111011010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let CextOpcode = "A2_or"; |
| let InputType = "imm"; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 10; |
| let opExtentAlign = 0; |
| } |
| def A2_orp : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = or($Rss32,$Rtt32)", |
| tc_5da50c4b, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011111; |
| let isCommutable = 1; |
| } |
| def A2_paddf : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if (!$Pu4) $Rd32 = add($Rs32,$Rt32)", |
| tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { |
| let Inst{7-7} = 0b1; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11111011000; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_add"; |
| let CextOpcode = "A2_add"; |
| let InputType = "reg"; |
| } |
| def A2_paddfnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if (!$Pu4.new) $Rd32 = add($Rs32,$Rt32)", |
| tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { |
| let Inst{7-7} = 0b1; |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b11111011000; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_add"; |
| let CextOpcode = "A2_add"; |
| let InputType = "reg"; |
| } |
| def A2_paddif : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), |
| "if (!$Pu4) $Rd32 = add($Rs32,#$Ii)", |
| tc_1c2c7a4a, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { |
| let Inst{13-13} = 0b0; |
| let Inst{31-23} = 0b011101001; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_addi"; |
| let CextOpcode = "A2_add"; |
| let InputType = "imm"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 1; |
| let opExtentBits = 8; |
| let opExtentAlign = 0; |
| } |
| def A2_paddifnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), |
| "if (!$Pu4.new) $Rd32 = add($Rs32,#$Ii)", |
| tc_442395f3, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { |
| let Inst{13-13} = 0b1; |
| let Inst{31-23} = 0b011101001; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_addi"; |
| let CextOpcode = "A2_add"; |
| let InputType = "imm"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 1; |
| let opExtentBits = 8; |
| let opExtentAlign = 0; |
| } |
| def A2_paddit : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), |
| "if ($Pu4) $Rd32 = add($Rs32,#$Ii)", |
| tc_1c2c7a4a, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { |
| let Inst{13-13} = 0b0; |
| let Inst{31-23} = 0b011101000; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_addi"; |
| let CextOpcode = "A2_add"; |
| let InputType = "imm"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 1; |
| let opExtentBits = 8; |
| let opExtentAlign = 0; |
| } |
| def A2_padditnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), |
| "if ($Pu4.new) $Rd32 = add($Rs32,#$Ii)", |
| tc_442395f3, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { |
| let Inst{13-13} = 0b1; |
| let Inst{31-23} = 0b011101000; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_addi"; |
| let CextOpcode = "A2_add"; |
| let InputType = "imm"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 1; |
| let opExtentBits = 8; |
| let opExtentAlign = 0; |
| } |
| def A2_paddt : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if ($Pu4) $Rd32 = add($Rs32,$Rt32)", |
| tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { |
| let Inst{7-7} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11111011000; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_add"; |
| let CextOpcode = "A2_add"; |
| let InputType = "reg"; |
| } |
| def A2_paddtnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if ($Pu4.new) $Rd32 = add($Rs32,$Rt32)", |
| tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { |
| let Inst{7-7} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b11111011000; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_add"; |
| let CextOpcode = "A2_add"; |
| let InputType = "reg"; |
| } |
| def A2_pandf : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if (!$Pu4) $Rd32 = and($Rs32,$Rt32)", |
| tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel { |
| let Inst{7-7} = 0b1; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11111001000; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_and"; |
| } |
| def A2_pandfnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if (!$Pu4.new) $Rd32 = and($Rs32,$Rt32)", |
| tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel { |
| let Inst{7-7} = 0b1; |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b11111001000; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_and"; |
| } |
| def A2_pandt : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if ($Pu4) $Rd32 = and($Rs32,$Rt32)", |
| tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel { |
| let Inst{7-7} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11111001000; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_and"; |
| } |
| def A2_pandtnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if ($Pu4.new) $Rd32 = and($Rs32,$Rt32)", |
| tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel { |
| let Inst{7-7} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b11111001000; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_and"; |
| } |
| def A2_porf : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if (!$Pu4) $Rd32 = or($Rs32,$Rt32)", |
| tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel { |
| let Inst{7-7} = 0b1; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11111001001; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_or"; |
| } |
| def A2_porfnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if (!$Pu4.new) $Rd32 = or($Rs32,$Rt32)", |
| tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel { |
| let Inst{7-7} = 0b1; |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b11111001001; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_or"; |
| } |
| def A2_port : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if ($Pu4) $Rd32 = or($Rs32,$Rt32)", |
| tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel { |
| let Inst{7-7} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11111001001; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_or"; |
| } |
| def A2_portnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if ($Pu4.new) $Rd32 = or($Rs32,$Rt32)", |
| tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel { |
| let Inst{7-7} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b11111001001; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_or"; |
| } |
| def A2_psubf : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32), |
| "if (!$Pu4) $Rd32 = sub($Rt32,$Rs32)", |
| tc_1c2c7a4a, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { |
| let Inst{7-7} = 0b1; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11111011001; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_sub"; |
| } |
| def A2_psubfnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32), |
| "if (!$Pu4.new) $Rd32 = sub($Rt32,$Rs32)", |
| tc_442395f3, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { |
| let Inst{7-7} = 0b1; |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b11111011001; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_sub"; |
| } |
| def A2_psubt : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32), |
| "if ($Pu4) $Rd32 = sub($Rt32,$Rs32)", |
| tc_1c2c7a4a, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { |
| let Inst{7-7} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11111011001; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_sub"; |
| } |
| def A2_psubtnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32), |
| "if ($Pu4.new) $Rd32 = sub($Rt32,$Rs32)", |
| tc_442395f3, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { |
| let Inst{7-7} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b11111011001; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_sub"; |
| } |
| def A2_pxorf : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if (!$Pu4) $Rd32 = xor($Rs32,$Rt32)", |
| tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel { |
| let Inst{7-7} = 0b1; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11111001011; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_xor"; |
| } |
| def A2_pxorfnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if (!$Pu4.new) $Rd32 = xor($Rs32,$Rt32)", |
| tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel { |
| let Inst{7-7} = 0b1; |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b11111001011; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_xor"; |
| } |
| def A2_pxort : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if ($Pu4) $Rd32 = xor($Rs32,$Rt32)", |
| tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel { |
| let Inst{7-7} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11111001011; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_xor"; |
| } |
| def A2_pxortnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if ($Pu4.new) $Rd32 = xor($Rs32,$Rt32)", |
| tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel { |
| let Inst{7-7} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b11111001011; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_xor"; |
| } |
| def A2_roundsat : HInst< |
| (outs IntRegs:$Rd32), |
| (ins DoubleRegs:$Rss32), |
| "$Rd32 = round($Rss32):sat", |
| tc_d61dfdc3, TypeS_2op>, Enc_90cd8b { |
| let Inst{13-5} = 0b000000001; |
| let Inst{31-21} = 0b10001000110; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_sat : HInst< |
| (outs IntRegs:$Rd32), |
| (ins DoubleRegs:$Rss32), |
| "$Rd32 = sat($Rss32)", |
| tc_9f6cd987, TypeS_2op>, Enc_90cd8b { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-21} = 0b10001000110; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let Defs = [USR_OVF]; |
| } |
| def A2_satb : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = satb($Rs32)", |
| tc_9f6cd987, TypeS_2op>, Enc_5e2823 { |
| let Inst{13-5} = 0b000000111; |
| let Inst{31-21} = 0b10001100110; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let Defs = [USR_OVF]; |
| } |
| def A2_sath : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = sath($Rs32)", |
| tc_9f6cd987, TypeS_2op>, Enc_5e2823 { |
| let Inst{13-5} = 0b000000100; |
| let Inst{31-21} = 0b10001100110; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let Defs = [USR_OVF]; |
| } |
| def A2_satub : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = satub($Rs32)", |
| tc_9f6cd987, TypeS_2op>, Enc_5e2823 { |
| let Inst{13-5} = 0b000000110; |
| let Inst{31-21} = 0b10001100110; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let Defs = [USR_OVF]; |
| } |
| def A2_satuh : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = satuh($Rs32)", |
| tc_9f6cd987, TypeS_2op>, Enc_5e2823 { |
| let Inst{13-5} = 0b000000101; |
| let Inst{31-21} = 0b10001100110; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let Defs = [USR_OVF]; |
| } |
| def A2_sub : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = sub($Rt32,$Rs32)", |
| tc_713b66bf, TypeALU32_3op>, Enc_bd6011, PredNewRel, ImmRegRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110011001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_sub"; |
| let CextOpcode = "A2_sub"; |
| let InputType = "reg"; |
| let isPredicable = 1; |
| } |
| def A2_subh_h16_hh : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = sub($Rt32.h,$Rs32.h):<<16", |
| tc_01d44cb2, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b011; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A2_subh_h16_hl : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = sub($Rt32.h,$Rs32.l):<<16", |
| tc_01d44cb2, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A2_subh_h16_lh : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = sub($Rt32.l,$Rs32.h):<<16", |
| tc_01d44cb2, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b001; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A2_subh_h16_ll : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = sub($Rt32.l,$Rs32.l):<<16", |
| tc_01d44cb2, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A2_subh_h16_sat_hh : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = sub($Rt32.h,$Rs32.h):sat:<<16", |
| tc_8a825db2, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b111; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_subh_h16_sat_hl : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = sub($Rt32.h,$Rs32.l):sat:<<16", |
| tc_8a825db2, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b110; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_subh_h16_sat_lh : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = sub($Rt32.l,$Rs32.h):sat:<<16", |
| tc_8a825db2, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b101; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_subh_h16_sat_ll : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = sub($Rt32.l,$Rs32.l):sat:<<16", |
| tc_8a825db2, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_subh_l16_hl : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = sub($Rt32.l,$Rs32.h)", |
| tc_f34c1c21, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A2_subh_l16_ll : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = sub($Rt32.l,$Rs32.l)", |
| tc_f34c1c21, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A2_subh_l16_sat_hl : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = sub($Rt32.l,$Rs32.h):sat", |
| tc_8a825db2, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b110; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_subh_l16_sat_ll : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = sub($Rt32.l,$Rs32.l):sat", |
| tc_8a825db2, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_subp : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = sub($Rtt32,$Rss32)", |
| tc_5da50c4b, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b111; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011001; |
| } |
| def A2_subri : HInst< |
| (outs IntRegs:$Rd32), |
| (ins s32_0Imm:$Ii, IntRegs:$Rs32), |
| "$Rd32 = sub(#$Ii,$Rs32)", |
| tc_713b66bf, TypeALU32_2op>, Enc_140c83, PredNewRel, ImmRegRel { |
| let Inst{31-22} = 0b0111011001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let CextOpcode = "A2_sub"; |
| let InputType = "imm"; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 1; |
| let opExtentBits = 10; |
| let opExtentAlign = 0; |
| } |
| def A2_subsat : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = sub($Rt32,$Rs32):sat", |
| tc_95a33176, TypeALU32_3op>, Enc_bd6011 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110110110; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| let InputType = "reg"; |
| } |
| def A2_svaddh : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = vaddh($Rs32,$Rt32)", |
| tc_713b66bf, TypeALU32_3op>, Enc_5ab2be { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110110000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let InputType = "reg"; |
| let isCommutable = 1; |
| } |
| def A2_svaddhs : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = vaddh($Rs32,$Rt32):sat", |
| tc_95a33176, TypeALU32_3op>, Enc_5ab2be { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110110001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| let InputType = "reg"; |
| let isCommutable = 1; |
| } |
| def A2_svadduhs : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = vadduh($Rs32,$Rt32):sat", |
| tc_95a33176, TypeALU32_3op>, Enc_5ab2be { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110110011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| let InputType = "reg"; |
| let isCommutable = 1; |
| } |
| def A2_svavgh : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = vavgh($Rs32,$Rt32)", |
| tc_8b5bd4f5, TypeALU32_3op>, Enc_5ab2be { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110111000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let InputType = "reg"; |
| let isCommutable = 1; |
| } |
| def A2_svavghs : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = vavgh($Rs32,$Rt32):rnd", |
| tc_84a7500d, TypeALU32_3op>, Enc_5ab2be { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110111001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let InputType = "reg"; |
| let isCommutable = 1; |
| } |
| def A2_svnavgh : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = vnavgh($Rt32,$Rs32)", |
| tc_8b5bd4f5, TypeALU32_3op>, Enc_bd6011 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110111011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let InputType = "reg"; |
| } |
| def A2_svsubh : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = vsubh($Rt32,$Rs32)", |
| tc_713b66bf, TypeALU32_3op>, Enc_bd6011 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110110100; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let InputType = "reg"; |
| } |
| def A2_svsubhs : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = vsubh($Rt32,$Rs32):sat", |
| tc_95a33176, TypeALU32_3op>, Enc_bd6011 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110110101; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| let InputType = "reg"; |
| } |
| def A2_svsubuhs : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = vsubuh($Rt32,$Rs32):sat", |
| tc_95a33176, TypeALU32_3op>, Enc_bd6011 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110110111; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| let InputType = "reg"; |
| } |
| def A2_swiz : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = swiz($Rs32)", |
| tc_9f6cd987, TypeS_2op>, Enc_5e2823 { |
| let Inst{13-5} = 0b000000111; |
| let Inst{31-21} = 0b10001100100; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| } |
| def A2_sxtb : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = sxtb($Rs32)", |
| tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-21} = 0b01110000101; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_sxtb"; |
| let isPredicable = 1; |
| } |
| def A2_sxth : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = sxth($Rs32)", |
| tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-21} = 0b01110000111; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_sxth"; |
| let isPredicable = 1; |
| } |
| def A2_sxtw : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins IntRegs:$Rs32), |
| "$Rdd32 = sxtw($Rs32)", |
| tc_9f6cd987, TypeS_2op>, Enc_3a3d62 { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-21} = 0b10000100010; |
| } |
| def A2_tfr : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = $Rs32", |
| tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-21} = 0b01110000011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_tfr"; |
| let InputType = "reg"; |
| let isPredicable = 1; |
| } |
| def A2_tfrcrr : HInst< |
| (outs IntRegs:$Rd32), |
| (ins CtrRegs:$Cs32), |
| "$Rd32 = $Cs32", |
| tc_7476d766, TypeCR>, Enc_0cb018 { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-21} = 0b01101010000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| } |
| def A2_tfrf : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if (!$Pu4) $Rd32 = $Rs32", |
| tc_1c2c7a4a, TypeALU32_2op>, PredNewRel, ImmRegRel { |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_tfr"; |
| let CextOpcode = "A2_tfr"; |
| let InputType = "reg"; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def A2_tfrfnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if (!$Pu4.new) $Rd32 = $Rs32", |
| tc_442395f3, TypeALU32_2op>, PredNewRel, ImmRegRel { |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_tfr"; |
| let CextOpcode = "A2_tfr"; |
| let InputType = "reg"; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def A2_tfrih : HInst< |
| (outs IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, u16_0Imm:$Ii), |
| "$Rx32.h = #$Ii", |
| tc_713b66bf, TypeALU32_2op>, Enc_51436c { |
| let Inst{21-21} = 0b1; |
| let Inst{31-24} = 0b01110010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def A2_tfril : HInst< |
| (outs IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, u16_0Imm:$Ii), |
| "$Rx32.l = #$Ii", |
| tc_713b66bf, TypeALU32_2op>, Enc_51436c { |
| let Inst{21-21} = 0b1; |
| let Inst{31-24} = 0b01110001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def A2_tfrp : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32), |
| "$Rdd32 = $Rss32", |
| tc_713b66bf, TypeALU32_2op>, PredNewRel { |
| let BaseOpcode = "A2_tfrp"; |
| let isPredicable = 1; |
| let isPseudo = 1; |
| } |
| def A2_tfrpf : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins PredRegs:$Pu4, DoubleRegs:$Rss32), |
| "if (!$Pu4) $Rdd32 = $Rss32", |
| tc_713b66bf, TypeALU32_2op>, PredNewRel { |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let BaseOpcode = "A2_tfrp"; |
| let isPseudo = 1; |
| } |
| def A2_tfrpfnew : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins PredRegs:$Pu4, DoubleRegs:$Rss32), |
| "if (!$Pu4.new) $Rdd32 = $Rss32", |
| tc_86173609, TypeALU32_2op>, PredNewRel { |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_tfrp"; |
| let isPseudo = 1; |
| } |
| def A2_tfrpi : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins s8_0Imm:$Ii), |
| "$Rdd32 = #$Ii", |
| tc_713b66bf, TypeALU64> { |
| let isAsCheapAsAMove = 1; |
| let isMoveImm = 1; |
| let isReMaterializable = 1; |
| let isPseudo = 1; |
| } |
| def A2_tfrpt : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins PredRegs:$Pu4, DoubleRegs:$Rss32), |
| "if ($Pu4) $Rdd32 = $Rss32", |
| tc_713b66bf, TypeALU32_2op>, PredNewRel { |
| let isPredicated = 1; |
| let BaseOpcode = "A2_tfrp"; |
| let isPseudo = 1; |
| } |
| def A2_tfrptnew : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins PredRegs:$Pu4, DoubleRegs:$Rss32), |
| "if ($Pu4.new) $Rdd32 = $Rss32", |
| tc_86173609, TypeALU32_2op>, PredNewRel { |
| let isPredicated = 1; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_tfrp"; |
| let isPseudo = 1; |
| } |
| def A2_tfrrcr : HInst< |
| (outs CtrRegs:$Cd32), |
| (ins IntRegs:$Rs32), |
| "$Cd32 = $Rs32", |
| tc_49fdfd4b, TypeCR>, Enc_bd811a { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-21} = 0b01100010001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| } |
| def A2_tfrsi : HInst< |
| (outs IntRegs:$Rd32), |
| (ins s32_0Imm:$Ii), |
| "$Rd32 = #$Ii", |
| tc_c57d9f39, TypeALU32_2op>, Enc_5e87ce, PredNewRel, ImmRegRel { |
| let Inst{21-21} = 0b0; |
| let Inst{31-24} = 0b01111000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_tfrsi"; |
| let CextOpcode = "A2_tfr"; |
| let InputType = "imm"; |
| let isAsCheapAsAMove = 1; |
| let isMoveImm = 1; |
| let isPredicable = 1; |
| let isReMaterializable = 1; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 1; |
| let opExtentBits = 16; |
| let opExtentAlign = 0; |
| } |
| def A2_tfrt : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if ($Pu4) $Rd32 = $Rs32", |
| tc_1c2c7a4a, TypeALU32_2op>, PredNewRel, ImmRegRel { |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_tfr"; |
| let CextOpcode = "A2_tfr"; |
| let InputType = "reg"; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def A2_tfrtnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if ($Pu4.new) $Rd32 = $Rs32", |
| tc_442395f3, TypeALU32_2op>, PredNewRel, ImmRegRel { |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_tfr"; |
| let CextOpcode = "A2_tfr"; |
| let InputType = "reg"; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def A2_vabsh : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32), |
| "$Rdd32 = vabsh($Rss32)", |
| tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb { |
| let Inst{13-5} = 0b000000100; |
| let Inst{31-21} = 0b10000000010; |
| let prefersSlot3 = 1; |
| } |
| def A2_vabshsat : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32), |
| "$Rdd32 = vabsh($Rss32):sat", |
| tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb { |
| let Inst{13-5} = 0b000000101; |
| let Inst{31-21} = 0b10000000010; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_vabsw : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32), |
| "$Rdd32 = vabsw($Rss32)", |
| tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb { |
| let Inst{13-5} = 0b000000110; |
| let Inst{31-21} = 0b10000000010; |
| let prefersSlot3 = 1; |
| } |
| def A2_vabswsat : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32), |
| "$Rdd32 = vabsw($Rss32):sat", |
| tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb { |
| let Inst{13-5} = 0b000000111; |
| let Inst{31-21} = 0b10000000010; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_vaddb_map : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vaddb($Rss32,$Rtt32)", |
| tc_5da50c4b, TypeMAPPING> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def A2_vaddh : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vaddh($Rss32,$Rtt32)", |
| tc_5da50c4b, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011000; |
| } |
| def A2_vaddhs : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vaddh($Rss32,$Rtt32):sat", |
| tc_8a825db2, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b011; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011000; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_vaddub : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vaddub($Rss32,$Rtt32)", |
| tc_5da50c4b, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011000; |
| } |
| def A2_vaddubs : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vaddub($Rss32,$Rtt32):sat", |
| tc_8a825db2, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b001; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011000; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_vadduhs : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vadduh($Rss32,$Rtt32):sat", |
| tc_8a825db2, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011000; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_vaddw : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vaddw($Rss32,$Rtt32)", |
| tc_5da50c4b, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b101; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011000; |
| } |
| def A2_vaddws : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vaddw($Rss32,$Rtt32):sat", |
| tc_8a825db2, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b110; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011000; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_vavgh : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vavgh($Rss32,$Rtt32)", |
| tc_f098b237, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011010; |
| let prefersSlot3 = 1; |
| } |
| def A2_vavghcr : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vavgh($Rss32,$Rtt32):crnd", |
| tc_0dfac0a7, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011010; |
| let prefersSlot3 = 1; |
| } |
| def A2_vavghr : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vavgh($Rss32,$Rtt32):rnd", |
| tc_20131976, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b011; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011010; |
| let prefersSlot3 = 1; |
| } |
| def A2_vavgub : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vavgub($Rss32,$Rtt32)", |
| tc_f098b237, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011010; |
| let prefersSlot3 = 1; |
| } |
| def A2_vavgubr : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vavgub($Rss32,$Rtt32):rnd", |
| tc_20131976, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b001; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011010; |
| let prefersSlot3 = 1; |
| } |
| def A2_vavguh : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vavguh($Rss32,$Rtt32)", |
| tc_f098b237, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b101; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011010; |
| let prefersSlot3 = 1; |
| } |
| def A2_vavguhr : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vavguh($Rss32,$Rtt32):rnd", |
| tc_20131976, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b110; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011010; |
| let prefersSlot3 = 1; |
| } |
| def A2_vavguw : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vavguw($Rss32,$Rtt32)", |
| tc_f098b237, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b011; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011011; |
| let prefersSlot3 = 1; |
| } |
| def A2_vavguwr : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vavguw($Rss32,$Rtt32):rnd", |
| tc_20131976, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011011; |
| let prefersSlot3 = 1; |
| } |
| def A2_vavgw : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vavgw($Rss32,$Rtt32)", |
| tc_f098b237, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011011; |
| let prefersSlot3 = 1; |
| } |
| def A2_vavgwcr : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vavgw($Rss32,$Rtt32):crnd", |
| tc_0dfac0a7, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011011; |
| let prefersSlot3 = 1; |
| } |
| def A2_vavgwr : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vavgw($Rss32,$Rtt32):rnd", |
| tc_20131976, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b001; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011011; |
| let prefersSlot3 = 1; |
| } |
| def A2_vcmpbeq : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Pd4 = vcmpb.eq($Rss32,$Rtt32)", |
| tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { |
| let Inst{7-2} = 0b110000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010010000; |
| } |
| def A2_vcmpbgtu : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Pd4 = vcmpb.gtu($Rss32,$Rtt32)", |
| tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { |
| let Inst{7-2} = 0b111000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010010000; |
| } |
| def A2_vcmpheq : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Pd4 = vcmph.eq($Rss32,$Rtt32)", |
| tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { |
| let Inst{7-2} = 0b011000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010010000; |
| } |
| def A2_vcmphgt : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Pd4 = vcmph.gt($Rss32,$Rtt32)", |
| tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { |
| let Inst{7-2} = 0b100000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010010000; |
| } |
| def A2_vcmphgtu : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Pd4 = vcmph.gtu($Rss32,$Rtt32)", |
| tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { |
| let Inst{7-2} = 0b101000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010010000; |
| } |
| def A2_vcmpweq : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Pd4 = vcmpw.eq($Rss32,$Rtt32)", |
| tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { |
| let Inst{7-2} = 0b000000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010010000; |
| } |
| def A2_vcmpwgt : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Pd4 = vcmpw.gt($Rss32,$Rtt32)", |
| tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { |
| let Inst{7-2} = 0b001000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010010000; |
| } |
| def A2_vcmpwgtu : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Pd4 = vcmpw.gtu($Rss32,$Rtt32)", |
| tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { |
| let Inst{7-2} = 0b010000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010010000; |
| } |
| def A2_vconj : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32), |
| "$Rdd32 = vconj($Rss32):sat", |
| tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb { |
| let Inst{13-5} = 0b000000111; |
| let Inst{31-21} = 0b10000000100; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_vmaxb : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vmaxb($Rtt32,$Rss32)", |
| tc_8a825db2, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b110; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011110; |
| let prefersSlot3 = 1; |
| } |
| def A2_vmaxh : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vmaxh($Rtt32,$Rss32)", |
| tc_8a825db2, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b001; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011110; |
| let prefersSlot3 = 1; |
| } |
| def A2_vmaxub : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vmaxub($Rtt32,$Rss32)", |
| tc_8a825db2, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011110; |
| let prefersSlot3 = 1; |
| } |
| def A2_vmaxuh : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vmaxuh($Rtt32,$Rss32)", |
| tc_8a825db2, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011110; |
| let prefersSlot3 = 1; |
| } |
| def A2_vmaxuw : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vmaxuw($Rtt32,$Rss32)", |
| tc_8a825db2, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b101; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011101; |
| let prefersSlot3 = 1; |
| } |
| def A2_vmaxw : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vmaxw($Rtt32,$Rss32)", |
| tc_8a825db2, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b011; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011110; |
| let prefersSlot3 = 1; |
| } |
| def A2_vminb : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vminb($Rtt32,$Rss32)", |
| tc_8a825db2, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b111; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011110; |
| let prefersSlot3 = 1; |
| } |
| def A2_vminh : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vminh($Rtt32,$Rss32)", |
| tc_8a825db2, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b001; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011101; |
| let prefersSlot3 = 1; |
| } |
| def A2_vminub : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vminub($Rtt32,$Rss32)", |
| tc_8a825db2, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011101; |
| let prefersSlot3 = 1; |
| } |
| def A2_vminuh : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vminuh($Rtt32,$Rss32)", |
| tc_8a825db2, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011101; |
| let prefersSlot3 = 1; |
| } |
| def A2_vminuw : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vminuw($Rtt32,$Rss32)", |
| tc_8a825db2, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011101; |
| let prefersSlot3 = 1; |
| } |
| def A2_vminw : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vminw($Rtt32,$Rss32)", |
| tc_8a825db2, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b011; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011101; |
| let prefersSlot3 = 1; |
| } |
| def A2_vnavgh : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vnavgh($Rtt32,$Rss32)", |
| tc_f098b237, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011100; |
| let prefersSlot3 = 1; |
| } |
| def A2_vnavghcr : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vnavgh($Rtt32,$Rss32):crnd:sat", |
| tc_0dfac0a7, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011100; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_vnavghr : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vnavgh($Rtt32,$Rss32):rnd:sat", |
| tc_0dfac0a7, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b001; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011100; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_vnavgw : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vnavgw($Rtt32,$Rss32)", |
| tc_f098b237, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b011; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011100; |
| let prefersSlot3 = 1; |
| } |
| def A2_vnavgwcr : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vnavgw($Rtt32,$Rss32):crnd:sat", |
| tc_0dfac0a7, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b110; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011100; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_vnavgwr : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vnavgw($Rtt32,$Rss32):rnd:sat", |
| tc_0dfac0a7, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011100; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_vraddub : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vraddub($Rss32,$Rtt32)", |
| tc_c21d7447, TypeM>, Enc_a56825 { |
| let Inst{7-5} = 0b001; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11101000010; |
| let prefersSlot3 = 1; |
| } |
| def A2_vraddub_acc : HInst< |
| (outs DoubleRegs:$Rxx32), |
| (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rxx32 += vraddub($Rss32,$Rtt32)", |
| tc_7f8ae742, TypeM>, Enc_88c16c { |
| let Inst{7-5} = 0b001; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11101010010; |
| let prefersSlot3 = 1; |
| let Constraints = "$Rxx32 = $Rxx32in"; |
| } |
| def A2_vrsadub : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vrsadub($Rss32,$Rtt32)", |
| tc_c21d7447, TypeM>, Enc_a56825 { |
| let Inst{7-5} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11101000010; |
| let prefersSlot3 = 1; |
| } |
| def A2_vrsadub_acc : HInst< |
| (outs DoubleRegs:$Rxx32), |
| (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rxx32 += vrsadub($Rss32,$Rtt32)", |
| tc_7f8ae742, TypeM>, Enc_88c16c { |
| let Inst{7-5} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11101010010; |
| let prefersSlot3 = 1; |
| let Constraints = "$Rxx32 = $Rxx32in"; |
| } |
| def A2_vsubb_map : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vsubb($Rss32,$Rtt32)", |
| tc_5da50c4b, TypeMAPPING> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def A2_vsubh : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vsubh($Rtt32,$Rss32)", |
| tc_5da50c4b, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011001; |
| } |
| def A2_vsubhs : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vsubh($Rtt32,$Rss32):sat", |
| tc_8a825db2, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b011; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011001; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_vsubub : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vsubub($Rtt32,$Rss32)", |
| tc_5da50c4b, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011001; |
| } |
| def A2_vsububs : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vsubub($Rtt32,$Rss32):sat", |
| tc_8a825db2, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b001; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011001; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_vsubuhs : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vsubuh($Rtt32,$Rss32):sat", |
| tc_8a825db2, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011001; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_vsubw : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vsubw($Rtt32,$Rss32)", |
| tc_5da50c4b, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b101; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011001; |
| } |
| def A2_vsubws : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vsubw($Rtt32,$Rss32):sat", |
| tc_8a825db2, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b110; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011001; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_xor : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = xor($Rs32,$Rt32)", |
| tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, PredNewRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110001011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_xor"; |
| let InputType = "reg"; |
| let isCommutable = 1; |
| let isPredicable = 1; |
| } |
| def A2_xorp : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = xor($Rss32,$Rtt32)", |
| tc_5da50c4b, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011111; |
| let isCommutable = 1; |
| } |
| def A2_zxtb : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = zxtb($Rs32)", |
| tc_713b66bf, TypeALU32_2op>, PredNewRel { |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_zxtb"; |
| let isPredicable = 1; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def A2_zxth : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = zxth($Rs32)", |
| tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-21} = 0b01110000110; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_zxth"; |
| let isPredicable = 1; |
| } |
| def A4_addp_c : HInst< |
| (outs DoubleRegs:$Rdd32, PredRegs:$Px4), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Px4in), |
| "$Rdd32 = add($Rss32,$Rtt32,$Px4):carry", |
| tc_1d41f8b7, TypeS_3op>, Enc_2b3f60 { |
| let Inst{7-7} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11000010110; |
| let isPredicateLate = 1; |
| let Constraints = "$Px4 = $Px4in"; |
| } |
| def A4_andn : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = and($Rt32,~$Rs32)", |
| tc_713b66bf, TypeALU32_3op>, Enc_bd6011 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110001100; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let InputType = "reg"; |
| } |
| def A4_andnp : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = and($Rtt32,~$Rss32)", |
| tc_5da50c4b, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b001; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011111; |
| } |
| def A4_bitsplit : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rdd32 = bitsplit($Rs32,$Rt32)", |
| tc_f34c1c21, TypeALU64>, Enc_be32a5 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010100001; |
| let prefersSlot3 = 1; |
| } |
| def A4_bitspliti : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins IntRegs:$Rs32, u5_0Imm:$Ii), |
| "$Rdd32 = bitsplit($Rs32,#$Ii)", |
| tc_f34c1c21, TypeS_2op>, Enc_311abd { |
| let Inst{7-5} = 0b100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b10001000110; |
| let prefersSlot3 = 1; |
| } |
| def A4_boundscheck : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, DoubleRegs:$Rtt32), |
| "$Pd4 = boundscheck($Rs32,$Rtt32)", |
| tc_4a55d03c, TypeALU64> { |
| let isPseudo = 1; |
| } |
| def A4_boundscheck_hi : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Pd4 = boundscheck($Rss32,$Rtt32):raw:hi", |
| tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { |
| let Inst{7-2} = 0b101000; |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b11010010000; |
| } |
| def A4_boundscheck_lo : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Pd4 = boundscheck($Rss32,$Rtt32):raw:lo", |
| tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { |
| let Inst{7-2} = 0b100000; |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b11010010000; |
| } |
| def A4_cmpbeq : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Pd4 = cmpb.eq($Rs32,$Rt32)", |
| tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel { |
| let Inst{7-2} = 0b110000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11000111110; |
| let CextOpcode = "A4_cmpbeq"; |
| let InputType = "reg"; |
| let isCommutable = 1; |
| let isCompare = 1; |
| } |
| def A4_cmpbeqi : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, u8_0Imm:$Ii), |
| "$Pd4 = cmpb.eq($Rs32,#$Ii)", |
| tc_a1297125, TypeALU64>, Enc_08d755, ImmRegRel { |
| let Inst{4-2} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11011101000; |
| let CextOpcode = "A4_cmpbeq"; |
| let InputType = "imm"; |
| let isCommutable = 1; |
| let isCompare = 1; |
| } |
| def A4_cmpbgt : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Pd4 = cmpb.gt($Rs32,$Rt32)", |
| tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel { |
| let Inst{7-2} = 0b010000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11000111110; |
| let CextOpcode = "A4_cmpbgt"; |
| let InputType = "reg"; |
| let isCompare = 1; |
| } |
| def A4_cmpbgti : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, s8_0Imm:$Ii), |
| "$Pd4 = cmpb.gt($Rs32,#$Ii)", |
| tc_a1297125, TypeALU64>, Enc_08d755, ImmRegRel { |
| let Inst{4-2} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11011101001; |
| let CextOpcode = "A4_cmpbgt"; |
| let InputType = "imm"; |
| let isCompare = 1; |
| } |
| def A4_cmpbgtu : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Pd4 = cmpb.gtu($Rs32,$Rt32)", |
| tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel { |
| let Inst{7-2} = 0b111000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11000111110; |
| let CextOpcode = "A4_cmpbgtu"; |
| let InputType = "reg"; |
| let isCompare = 1; |
| } |
| def A4_cmpbgtui : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, u32_0Imm:$Ii), |
| "$Pd4 = cmpb.gtu($Rs32,#$Ii)", |
| tc_a1297125, TypeALU64>, Enc_02553a, ImmRegRel { |
| let Inst{4-2} = 0b000; |
| let Inst{13-12} = 0b00; |
| let Inst{31-21} = 0b11011101010; |
| let CextOpcode = "A4_cmpbgtu"; |
| let InputType = "imm"; |
| let isCompare = 1; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 0; |
| let opExtentBits = 7; |
| let opExtentAlign = 0; |
| } |
| def A4_cmpheq : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Pd4 = cmph.eq($Rs32,$Rt32)", |
| tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel { |
| let Inst{7-2} = 0b011000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11000111110; |
| let CextOpcode = "A4_cmpheq"; |
| let InputType = "reg"; |
| let isCommutable = 1; |
| let isCompare = 1; |
| } |
| def A4_cmpheqi : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, s32_0Imm:$Ii), |
| "$Pd4 = cmph.eq($Rs32,#$Ii)", |
| tc_a1297125, TypeALU64>, Enc_08d755, ImmRegRel { |
| let Inst{4-2} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11011101000; |
| let CextOpcode = "A4_cmpheq"; |
| let InputType = "imm"; |
| let isCommutable = 1; |
| let isCompare = 1; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 8; |
| let opExtentAlign = 0; |
| } |
| def A4_cmphgt : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Pd4 = cmph.gt($Rs32,$Rt32)", |
| tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel { |
| let Inst{7-2} = 0b100000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11000111110; |
| let CextOpcode = "A4_cmphgt"; |
| let InputType = "reg"; |
| let isCompare = 1; |
| } |
| def A4_cmphgti : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, s32_0Imm:$Ii), |
| "$Pd4 = cmph.gt($Rs32,#$Ii)", |
| tc_a1297125, TypeALU64>, Enc_08d755, ImmRegRel { |
| let Inst{4-2} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11011101001; |
| let CextOpcode = "A4_cmphgt"; |
| let InputType = "imm"; |
| let isCompare = 1; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 8; |
| let opExtentAlign = 0; |
| } |
| def A4_cmphgtu : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Pd4 = cmph.gtu($Rs32,$Rt32)", |
| tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel { |
| let Inst{7-2} = 0b101000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11000111110; |
| let CextOpcode = "A4_cmphgtu"; |
| let InputType = "reg"; |
| let isCompare = 1; |
| } |
| def A4_cmphgtui : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, u32_0Imm:$Ii), |
| "$Pd4 = cmph.gtu($Rs32,#$Ii)", |
| tc_a1297125, TypeALU64>, Enc_02553a, ImmRegRel { |
| let Inst{4-2} = 0b010; |
| let Inst{13-12} = 0b00; |
| let Inst{31-21} = 0b11011101010; |
| let CextOpcode = "A4_cmphgtu"; |
| let InputType = "imm"; |
| let isCompare = 1; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 0; |
| let opExtentBits = 7; |
| let opExtentAlign = 0; |
| } |
| def A4_combineii : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins s8_0Imm:$Ii, u32_0Imm:$II), |
| "$Rdd32 = combine(#$Ii,#$II)", |
| tc_713b66bf, TypeALU32_2op>, Enc_f0cca7 { |
| let Inst{31-21} = 0b01111100100; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def A4_combineir : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins s32_0Imm:$Ii, IntRegs:$Rs32), |
| "$Rdd32 = combine(#$Ii,$Rs32)", |
| tc_713b66bf, TypeALU32_2op>, Enc_9cdba7 { |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b01110011001; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 1; |
| let opExtentBits = 8; |
| let opExtentAlign = 0; |
| } |
| def A4_combineri : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins IntRegs:$Rs32, s32_0Imm:$Ii), |
| "$Rdd32 = combine($Rs32,#$Ii)", |
| tc_713b66bf, TypeALU32_2op>, Enc_9cdba7 { |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b01110011000; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 8; |
| let opExtentAlign = 0; |
| } |
| def A4_cround_ri : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, u5_0Imm:$Ii), |
| "$Rd32 = cround($Rs32,#$Ii)", |
| tc_0dfac0a7, TypeS_2op>, Enc_a05677 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b10001100111; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A4_cround_rr : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = cround($Rs32,$Rt32)", |
| tc_0dfac0a7, TypeS_3op>, Enc_5ab2be { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11000110110; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A4_ext : HInst< |
| (outs), |
| (ins u26_6Imm:$Ii), |
| "immext(#$Ii)", |
| tc_112d30d6, TypeEXTENDER>, Enc_2b518f { |
| let Inst{31-28} = 0b0000; |
| } |
| def A4_modwrapu : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = modwrap($Rs32,$Rt32)", |
| tc_8a825db2, TypeALU64>, Enc_5ab2be { |
| let Inst{7-5} = 0b111; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011111; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A4_orn : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = or($Rt32,~$Rs32)", |
| tc_713b66bf, TypeALU32_3op>, Enc_bd6011 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110001101; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let InputType = "reg"; |
| } |
| def A4_ornp : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = or($Rtt32,~$Rss32)", |
| tc_5da50c4b, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b011; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011111; |
| } |
| def A4_paslhf : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if (!$Pu4) $Rd32 = aslh($Rs32)", |
| tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-10} = 0b1010; |
| let Inst{31-21} = 0b01110000000; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_aslh"; |
| } |
| def A4_paslhfnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if (!$Pu4.new) $Rd32 = aslh($Rs32)", |
| tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-10} = 0b1011; |
| let Inst{31-21} = 0b01110000000; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_aslh"; |
| } |
| def A4_paslht : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if ($Pu4) $Rd32 = aslh($Rs32)", |
| tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-10} = 0b1000; |
| let Inst{31-21} = 0b01110000000; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_aslh"; |
| } |
| def A4_paslhtnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if ($Pu4.new) $Rd32 = aslh($Rs32)", |
| tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-10} = 0b1001; |
| let Inst{31-21} = 0b01110000000; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_aslh"; |
| } |
| def A4_pasrhf : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if (!$Pu4) $Rd32 = asrh($Rs32)", |
| tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-10} = 0b1010; |
| let Inst{31-21} = 0b01110000001; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_asrh"; |
| } |
| def A4_pasrhfnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if (!$Pu4.new) $Rd32 = asrh($Rs32)", |
| tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-10} = 0b1011; |
| let Inst{31-21} = 0b01110000001; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_asrh"; |
| } |
| def A4_pasrht : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if ($Pu4) $Rd32 = asrh($Rs32)", |
| tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-10} = 0b1000; |
| let Inst{31-21} = 0b01110000001; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_asrh"; |
| } |
| def A4_pasrhtnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if ($Pu4.new) $Rd32 = asrh($Rs32)", |
| tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-10} = 0b1001; |
| let Inst{31-21} = 0b01110000001; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_asrh"; |
| } |
| def A4_psxtbf : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if (!$Pu4) $Rd32 = sxtb($Rs32)", |
| tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-10} = 0b1010; |
| let Inst{31-21} = 0b01110000101; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_sxtb"; |
| } |
| def A4_psxtbfnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if (!$Pu4.new) $Rd32 = sxtb($Rs32)", |
| tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-10} = 0b1011; |
| let Inst{31-21} = 0b01110000101; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_sxtb"; |
| } |
| def A4_psxtbt : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if ($Pu4) $Rd32 = sxtb($Rs32)", |
| tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-10} = 0b1000; |
| let Inst{31-21} = 0b01110000101; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_sxtb"; |
| } |
| def A4_psxtbtnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if ($Pu4.new) $Rd32 = sxtb($Rs32)", |
| tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-10} = 0b1001; |
| let Inst{31-21} = 0b01110000101; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_sxtb"; |
| } |
| def A4_psxthf : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if (!$Pu4) $Rd32 = sxth($Rs32)", |
| tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-10} = 0b1010; |
| let Inst{31-21} = 0b01110000111; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_sxth"; |
| } |
| def A4_psxthfnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if (!$Pu4.new) $Rd32 = sxth($Rs32)", |
| tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-10} = 0b1011; |
| let Inst{31-21} = 0b01110000111; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_sxth"; |
| } |
| def A4_psxtht : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if ($Pu4) $Rd32 = sxth($Rs32)", |
| tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-10} = 0b1000; |
| let Inst{31-21} = 0b01110000111; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_sxth"; |
| } |
| def A4_psxthtnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if ($Pu4.new) $Rd32 = sxth($Rs32)", |
| tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-10} = 0b1001; |
| let Inst{31-21} = 0b01110000111; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_sxth"; |
| } |
| def A4_pzxtbf : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if (!$Pu4) $Rd32 = zxtb($Rs32)", |
| tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-10} = 0b1010; |
| let Inst{31-21} = 0b01110000100; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_zxtb"; |
| } |
| def A4_pzxtbfnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if (!$Pu4.new) $Rd32 = zxtb($Rs32)", |
| tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-10} = 0b1011; |
| let Inst{31-21} = 0b01110000100; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_zxtb"; |
| } |
| def A4_pzxtbt : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if ($Pu4) $Rd32 = zxtb($Rs32)", |
| tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-10} = 0b1000; |
| let Inst{31-21} = 0b01110000100; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_zxtb"; |
| } |
| def A4_pzxtbtnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if ($Pu4.new) $Rd32 = zxtb($Rs32)", |
| tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-10} = 0b1001; |
| let Inst{31-21} = 0b01110000100; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_zxtb"; |
| } |
| def A4_pzxthf : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if (!$Pu4) $Rd32 = zxth($Rs32)", |
| tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-10} = 0b1010; |
| let Inst{31-21} = 0b01110000110; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_zxth"; |
| } |
| def A4_pzxthfnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if (!$Pu4.new) $Rd32 = zxth($Rs32)", |
| tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-10} = 0b1011; |
| let Inst{31-21} = 0b01110000110; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_zxth"; |
| } |
| def A4_pzxtht : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if ($Pu4) $Rd32 = zxth($Rs32)", |
| tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-10} = 0b1000; |
| let Inst{31-21} = 0b01110000110; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_zxth"; |
| } |
| def A4_pzxthtnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if ($Pu4.new) $Rd32 = zxth($Rs32)", |
| tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-10} = 0b1001; |
| let Inst{31-21} = 0b01110000110; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_zxth"; |
| } |
| def A4_rcmpeq : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = cmp.eq($Rs32,$Rt32)", |
| tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, ImmRegRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110011010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let CextOpcode = "A4_rcmpeq"; |
| let InputType = "reg"; |
| let isCommutable = 1; |
| } |
| def A4_rcmpeqi : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, s32_0Imm:$Ii), |
| "$Rd32 = cmp.eq($Rs32,#$Ii)", |
| tc_713b66bf, TypeALU32_2op>, Enc_b8c967, ImmRegRel { |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b01110011010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let CextOpcode = "A4_rcmpeqi"; |
| let InputType = "imm"; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 8; |
| let opExtentAlign = 0; |
| } |
| def A4_rcmpneq : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = !cmp.eq($Rs32,$Rt32)", |
| tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, ImmRegRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110011011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let CextOpcode = "A4_rcmpneq"; |
| let InputType = "reg"; |
| let isCommutable = 1; |
| } |
| def A4_rcmpneqi : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, s32_0Imm:$Ii), |
| "$Rd32 = !cmp.eq($Rs32,#$Ii)", |
| tc_713b66bf, TypeALU32_2op>, Enc_b8c967, ImmRegRel { |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b01110011011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let CextOpcode = "A4_rcmpeqi"; |
| let InputType = "imm"; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 8; |
| let opExtentAlign = 0; |
| } |
| def A4_round_ri : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, u5_0Imm:$Ii), |
| "$Rd32 = round($Rs32,#$Ii)", |
| tc_0dfac0a7, TypeS_2op>, Enc_a05677 { |
| let Inst{7-5} = 0b100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b10001100111; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A4_round_ri_sat : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, u5_0Imm:$Ii), |
| "$Rd32 = round($Rs32,#$Ii):sat", |
| tc_0dfac0a7, TypeS_2op>, Enc_a05677 { |
| let Inst{7-5} = 0b110; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b10001100111; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A4_round_rr : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = round($Rs32,$Rt32)", |
| tc_0dfac0a7, TypeS_3op>, Enc_5ab2be { |
| let Inst{7-5} = 0b100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11000110110; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A4_round_rr_sat : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = round($Rs32,$Rt32):sat", |
| tc_0dfac0a7, TypeS_3op>, Enc_5ab2be { |
| let Inst{7-5} = 0b110; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11000110110; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A4_subp_c : HInst< |
| (outs DoubleRegs:$Rdd32, PredRegs:$Px4), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Px4in), |
| "$Rdd32 = sub($Rss32,$Rtt32,$Px4):carry", |
| tc_1d41f8b7, TypeS_3op>, Enc_2b3f60 { |
| let Inst{7-7} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11000010111; |
| let isPredicateLate = 1; |
| let Constraints = "$Px4 = $Px4in"; |
| } |
| def A4_tfrcpp : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins CtrRegs64:$Css32), |
| "$Rdd32 = $Css32", |
| tc_7476d766, TypeCR>, Enc_667b39 { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-21} = 0b01101000000; |
| } |
| def A4_tfrpcp : HInst< |
| (outs CtrRegs64:$Cdd32), |
| (ins DoubleRegs:$Rss32), |
| "$Cdd32 = $Rss32", |
| tc_49fdfd4b, TypeCR>, Enc_0ed752 { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-21} = 0b01100011001; |
| } |
| def A4_tlbmatch : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, IntRegs:$Rt32), |
| "$Pd4 = tlbmatch($Rss32,$Rt32)", |
| tc_d68dca5c, TypeALU64>, Enc_03833b { |
| let Inst{7-2} = 0b011000; |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b11010010000; |
| let isPredicateLate = 1; |
| } |
| def A4_vcmpbeq_any : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Pd4 = any8(vcmpb.eq($Rss32,$Rtt32))", |
| tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { |
| let Inst{7-2} = 0b000000; |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b11010010000; |
| } |
| def A4_vcmpbeqi : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, u8_0Imm:$Ii), |
| "$Pd4 = vcmpb.eq($Rss32,#$Ii)", |
| tc_a1297125, TypeALU64>, Enc_0d8adb { |
| let Inst{4-2} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11011100000; |
| } |
| def A4_vcmpbgt : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Pd4 = vcmpb.gt($Rss32,$Rtt32)", |
| tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { |
| let Inst{7-2} = 0b010000; |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b11010010000; |
| } |
| def A4_vcmpbgti : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, s8_0Imm:$Ii), |
| "$Pd4 = vcmpb.gt($Rss32,#$Ii)", |
| tc_a1297125, TypeALU64>, Enc_0d8adb { |
| let Inst{4-2} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11011100001; |
| } |
| def A4_vcmpbgtui : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, u7_0Imm:$Ii), |
| "$Pd4 = vcmpb.gtu($Rss32,#$Ii)", |
| tc_a1297125, TypeALU64>, Enc_3680c2 { |
| let Inst{4-2} = 0b000; |
| let Inst{13-12} = 0b00; |
| let Inst{31-21} = 0b11011100010; |
| } |
| def A4_vcmpheqi : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, s8_0Imm:$Ii), |
| "$Pd4 = vcmph.eq($Rss32,#$Ii)", |
| tc_a1297125, TypeALU64>, Enc_0d8adb { |
| let Inst{4-2} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11011100000; |
| } |
| def A4_vcmphgti : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, s8_0Imm:$Ii), |
| "$Pd4 = vcmph.gt($Rss32,#$Ii)", |
| tc_a1297125, TypeALU64>, Enc_0d8adb { |
| let Inst{4-2} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11011100001; |
| } |
| def A4_vcmphgtui : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, u7_0Imm:$Ii), |
| "$Pd4 = vcmph.gtu($Rss32,#$Ii)", |
| tc_a1297125, TypeALU64>, Enc_3680c2 { |
| let Inst{4-2} = 0b010; |
| let Inst{13-12} = 0b00; |
| let Inst{31-21} = 0b11011100010; |
| } |
| def A4_vcmpweqi : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, s8_0Imm:$Ii), |
| "$Pd4 = vcmpw.eq($Rss32,#$Ii)", |
| tc_a1297125, TypeALU64>, Enc_0d8adb { |
| let Inst{4-2} = 0b100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11011100000; |
| } |
| def A4_vcmpwgti : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, s8_0Imm:$Ii), |
| "$Pd4 = vcmpw.gt($Rss32,#$Ii)", |
| tc_a1297125, TypeALU64>, Enc_0d8adb { |
| let Inst{4-2} = 0b100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11011100001; |
| } |
| def A4_vcmpwgtui : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, u7_0Imm:$Ii), |
| "$Pd4 = vcmpw.gtu($Rss32,#$Ii)", |
| tc_a1297125, TypeALU64>, Enc_3680c2 { |
| let Inst{4-2} = 0b100; |
| let Inst{13-12} = 0b00; |
| let Inst{31-21} = 0b11011100010; |
| } |
| def A4_vrmaxh : HInst< |
| (outs DoubleRegs:$Rxx32), |
| (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), |
| "$Rxx32 = vrmaxh($Rss32,$Ru32)", |
| tc_788b1d09, TypeS_3op>, Enc_412ff0 { |
| let Inst{7-5} = 0b001; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11001011001; |
| let prefersSlot3 = 1; |
| let Constraints = "$Rxx32 = $Rxx32in"; |
| } |
| def A4_vrmaxuh : HInst< |
| (outs DoubleRegs:$Rxx32), |
| (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), |
| "$Rxx32 = vrmaxuh($Rss32,$Ru32)", |
| tc_788b1d09, TypeS_3op>, Enc_412ff0 { |
| let Inst{7-5} = 0b001; |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b11001011001; |
| let prefersSlot3 = 1; |
| let Constraints = "$Rxx32 = $Rxx32in"; |
| } |
| def A4_vrmaxuw : HInst< |
| (outs DoubleRegs:$Rxx32), |
| (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), |
| "$Rxx32 = vrmaxuw($Rss32,$Ru32)", |
| tc_788b1d09, TypeS_3op>, Enc_412ff0 { |
| let Inst{7-5} = 0b010; |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b11001011001; |
| let prefersSlot3 = 1; |
| let Constraints = "$Rxx32 = $Rxx32in"; |
| } |
| def A4_vrmaxw : HInst< |
| (outs DoubleRegs:$Rxx32), |
| (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), |
| "$Rxx32 = vrmaxw($Rss32,$Ru32)", |
| tc_788b1d09, TypeS_3op>, Enc_412ff0 { |
| let Inst{7-5} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11001011001; |
| let prefersSlot3 = 1; |
| let Constraints = "$Rxx32 = $Rxx32in"; |
| } |
| def A4_vrminh : HInst< |
| (outs DoubleRegs:$Rxx32), |
| (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), |
| "$Rxx32 = vrminh($Rss32,$Ru32)", |
| tc_788b1d09, TypeS_3op>, Enc_412ff0 { |
| let Inst{7-5} = 0b101; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11001011001; |
| let prefersSlot3 = 1; |
| let Constraints = "$Rxx32 = $Rxx32in"; |
| } |
| def A4_vrminuh : HInst< |
| (outs DoubleRegs:$Rxx32), |
| (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), |
| "$Rxx32 = vrminuh($Rss32,$Ru32)", |
| tc_788b1d09, TypeS_3op>, Enc_412ff0 { |
| let Inst{7-5} = 0b101; |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b11001011001; |
| let prefersSlot3 = 1; |
| let Constraints = "$Rxx32 = $Rxx32in"; |
| } |
| def A4_vrminuw : HInst< |
| (outs DoubleRegs:$Rxx32), |
| (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), |
| "$Rxx32 = vrminuw($Rss32,$Ru32)", |
| tc_788b1d09, TypeS_3op>, Enc_412ff0 { |
| let Inst{7-5} = 0b110; |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b11001011001; |
| let prefersSlot3 = 1; |
| let Constraints = "$Rxx32 = $Rxx32in"; |
| } |
| def A4_vrminw : HInst< |
| (outs DoubleRegs:$Rxx32), |
| (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), |
| "$Rxx32 = vrminw($Rss32,$Ru32)", |
| tc_788b1d09, TypeS_3op>, Enc_412ff0 { |
| let Inst{7-5} = 0b110; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11001011001; |
| let prefersSlot3 = 1; |
| let Constraints = "$Rxx32 = $Rxx32in"; |
| } |
| def A5_ACS : HInst< |
| (outs DoubleRegs:$Rxx32, PredRegs:$Pe4), |
| (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rxx32,$Pe4 = vacsh($Rss32,$Rtt32)", |
| tc_38e0bae9, TypeM>, Enc_831a7d, Requires<[HasV55]> { |
| let Inst{7-7} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11101010101; |
| let isPredicateLate = 1; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| let Constraints = "$Rxx32 = $Rxx32in"; |
| } |
| def A5_vaddhubs : HInst< |
| (outs IntRegs:$Rd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rd32 = vaddhub($Rss32,$Rtt32):sat", |
| tc_0dfac0a7, TypeS_3op>, Enc_d2216a { |
| let Inst{7-5} = 0b001; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11000001010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A6_vcmpbeq_notany : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Pd4 = !any8(vcmpb.eq($Rss32,$Rtt32))", |
| tc_407e96f9, TypeALU64>, Enc_fcf7a7, Requires<[HasV65]> { |
| let Inst{7-2} = 0b001000; |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b11010010000; |
| } |
| def A6_vminub_RdP : HInst< |
| (outs DoubleRegs:$Rdd32, PredRegs:$Pe4), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32,$Pe4 = vminub($Rtt32,$Rss32)", |
| tc_7401744f, TypeM>, Enc_d2c7f1, Requires<[HasV62]> { |
| let Inst{7-7} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11101010111; |
| let isPredicateLate = 1; |
| let prefersSlot3 = 1; |
| } |
| def A7_clip : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, u5_0Imm:$Ii), |
| "$Rd32 = clip($Rs32,#$Ii)", |
| tc_407e96f9, TypeS_2op>, Enc_a05677, Requires<[HasV67,UseAudio]> { |
| let Inst{7-5} = 0b101; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b10001000110; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| } |
| def A7_croundd_ri : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, u6_0Imm:$Ii), |
| "$Rdd32 = cround($Rss32,#$Ii)", |
| tc_9b3c0462, TypeS_2op>, Enc_5eac98, Requires<[HasV67,UseAudio]> { |
| let Inst{7-5} = 0b010; |
| let Inst{31-21} = 0b10001100111; |
| let prefersSlot3 = 1; |
| } |
| def A7_croundd_rr : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, IntRegs:$Rt32), |
| "$Rdd32 = cround($Rss32,$Rt32)", |
| tc_9b3c0462, TypeS_3op>, Enc_927852, Requires<[HasV67,UseAudio]> { |
| let Inst{7-5} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11000110110; |
| let prefersSlot3 = 1; |
| } |
| def A7_vclip : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, u5_0Imm:$Ii), |
| "$Rdd32 = vclip($Rss32,#$Ii)", |
| tc_407e96f9, TypeS_2op>, Enc_7e5a82, Requires<[HasV67,UseAudio]> { |
| let Inst{7-5} = 0b110; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b10001000110; |
| } |
| def C2_all8 : HInst< |
| (outs PredRegs:$Pd4), |
| (ins PredRegs:$Ps4), |
| "$Pd4 = all8($Ps4)", |
| tc_151bf368, TypeCR>, Enc_65d691 { |
| let Inst{13-2} = 0b000000000000; |
| let Inst{31-18} = 0b01101011101000; |
| } |
| def C2_and : HInst< |
| (outs PredRegs:$Pd4), |
| (ins PredRegs:$Pt4, PredRegs:$Ps4), |
| "$Pd4 = and($Pt4,$Ps4)", |
| tc_651cbe02, TypeCR>, Enc_454a26 { |
| let Inst{7-2} = 0b000000; |
| let Inst{13-10} = 0b0000; |
| let Inst{31-18} = 0b01101011000000; |
| } |
| def C2_andn : HInst< |
| (outs PredRegs:$Pd4), |
| (ins PredRegs:$Pt4, PredRegs:$Ps4), |
| "$Pd4 = and($Pt4,!$Ps4)", |
| tc_651cbe02, TypeCR>, Enc_454a26 { |
| let Inst{7-2} = 0b000000; |
| let Inst{13-10} = 0b0000; |
| let Inst{31-18} = 0b01101011011000; |
| } |
| def C2_any8 : HInst< |
| (outs PredRegs:$Pd4), |
| (ins PredRegs:$Ps4), |
| "$Pd4 = any8($Ps4)", |
| tc_151bf368, TypeCR>, Enc_65d691 { |
| let Inst{13-2} = 0b000000000000; |
| let Inst{31-18} = 0b01101011100000; |
| } |
| def C2_bitsclr : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Pd4 = bitsclr($Rs32,$Rt32)", |
| tc_4a55d03c, TypeS_3op>, Enc_c2b48e { |
| let Inst{7-2} = 0b000000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11000111100; |
| } |
| def C2_bitsclri : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, u6_0Imm:$Ii), |
| "$Pd4 = bitsclr($Rs32,#$Ii)", |
| tc_a1297125, TypeS_2op>, Enc_5d6c34 { |
| let Inst{7-2} = 0b000000; |
| let Inst{31-21} = 0b10000101100; |
| } |
| def C2_bitsset : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Pd4 = bitsset($Rs32,$Rt32)", |
| tc_4a55d03c, TypeS_3op>, Enc_c2b48e { |
| let Inst{7-2} = 0b000000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11000111010; |
| } |
| def C2_ccombinewf : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if (!$Pu4) $Rdd32 = combine($Rs32,$Rt32)", |
| tc_1c2c7a4a, TypeALU32_3op>, Enc_cb4b4e, PredNewRel { |
| let Inst{7-7} = 0b1; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11111101000; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let BaseOpcode = "A2_combinew"; |
| } |
| def C2_ccombinewnewf : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if (!$Pu4.new) $Rdd32 = combine($Rs32,$Rt32)", |
| tc_442395f3, TypeALU32_3op>, Enc_cb4b4e, PredNewRel { |
| let Inst{7-7} = 0b1; |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b11111101000; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_combinew"; |
| } |
| def C2_ccombinewnewt : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if ($Pu4.new) $Rdd32 = combine($Rs32,$Rt32)", |
| tc_442395f3, TypeALU32_3op>, Enc_cb4b4e, PredNewRel { |
| let Inst{7-7} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b11111101000; |
| let isPredicated = 1; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_combinew"; |
| } |
| def C2_ccombinewt : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if ($Pu4) $Rdd32 = combine($Rs32,$Rt32)", |
| tc_1c2c7a4a, TypeALU32_3op>, Enc_cb4b4e, PredNewRel { |
| let Inst{7-7} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11111101000; |
| let isPredicated = 1; |
| let BaseOpcode = "A2_combinew"; |
| } |
| def C2_cmoveif : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, s32_0Imm:$Ii), |
| "if (!$Pu4) $Rd32 = #$Ii", |
| tc_713b66bf, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel { |
| let Inst{13-13} = 0b0; |
| let Inst{20-20} = 0b0; |
| let Inst{31-23} = 0b011111101; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_tfrsi"; |
| let CextOpcode = "A2_tfr"; |
| let InputType = "imm"; |
| let isMoveImm = 1; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 12; |
| let opExtentAlign = 0; |
| } |
| def C2_cmoveit : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, s32_0Imm:$Ii), |
| "if ($Pu4) $Rd32 = #$Ii", |
| tc_713b66bf, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel { |
| let Inst{13-13} = 0b0; |
| let Inst{20-20} = 0b0; |
| let Inst{31-23} = 0b011111100; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_tfrsi"; |
| let CextOpcode = "A2_tfr"; |
| let InputType = "imm"; |
| let isMoveImm = 1; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 12; |
| let opExtentAlign = 0; |
| } |
| def C2_cmovenewif : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, s32_0Imm:$Ii), |
| "if (!$Pu4.new) $Rd32 = #$Ii", |
| tc_86173609, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel { |
| let Inst{13-13} = 0b1; |
| let Inst{20-20} = 0b0; |
| let Inst{31-23} = 0b011111101; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_tfrsi"; |
| let CextOpcode = "A2_tfr"; |
| let InputType = "imm"; |
| let isMoveImm = 1; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 12; |
| let opExtentAlign = 0; |
| } |
| def C2_cmovenewit : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, s32_0Imm:$Ii), |
| "if ($Pu4.new) $Rd32 = #$Ii", |
| tc_86173609, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel { |
| let Inst{13-13} = 0b1; |
| let Inst{20-20} = 0b0; |
| let Inst{31-23} = 0b011111100; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_tfrsi"; |
| let CextOpcode = "A2_tfr"; |
| let InputType = "imm"; |
| let isMoveImm = 1; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 12; |
| let opExtentAlign = 0; |
| } |
| def C2_cmpeq : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Pd4 = cmp.eq($Rs32,$Rt32)", |
| tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { |
| let Inst{7-2} = 0b000000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110010000; |
| let CextOpcode = "C2_cmpeq"; |
| let InputType = "reg"; |
| let isCommutable = 1; |
| let isCompare = 1; |
| } |
| def C2_cmpeqi : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, s32_0Imm:$Ii), |
| "$Pd4 = cmp.eq($Rs32,#$Ii)", |
| tc_d33e5eee, TypeALU32_2op>, Enc_bd0b33, ImmRegRel { |
| let Inst{4-2} = 0b000; |
| let Inst{31-22} = 0b0111010100; |
| let CextOpcode = "C2_cmpeq"; |
| let InputType = "imm"; |
| let isCompare = 1; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 10; |
| let opExtentAlign = 0; |
| } |
| def C2_cmpeqp : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Pd4 = cmp.eq($Rss32,$Rtt32)", |
| tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { |
| let Inst{7-2} = 0b000000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010010100; |
| let isCommutable = 1; |
| let isCompare = 1; |
| } |
| def C2_cmpgei : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, s8_0Imm:$Ii), |
| "$Pd4 = cmp.ge($Rs32,#$Ii)", |
| tc_d33e5eee, TypeALU32_2op> { |
| let isCompare = 1; |
| let isPseudo = 1; |
| } |
| def C2_cmpgeui : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, u8_0Imm:$Ii), |
| "$Pd4 = cmp.geu($Rs32,#$Ii)", |
| tc_d33e5eee, TypeALU32_2op> { |
| let isCompare = 1; |
| let isPseudo = 1; |
| } |
| def C2_cmpgt : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Pd4 = cmp.gt($Rs32,$Rt32)", |
| tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { |
| let Inst{7-2} = 0b000000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110010010; |
| let CextOpcode = "C2_cmpgt"; |
| let InputType = "reg"; |
| let isCompare = 1; |
| } |
| def C2_cmpgti : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, s32_0Imm:$Ii), |
| "$Pd4 = cmp.gt($Rs32,#$Ii)", |
| tc_d33e5eee, TypeALU32_2op>, Enc_bd0b33, ImmRegRel { |
| let Inst{4-2} = 0b000; |
| let Inst{31-22} = 0b0111010101; |
| let CextOpcode = "C2_cmpgt"; |
| let InputType = "imm"; |
| let isCompare = 1; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 10; |
| let opExtentAlign = 0; |
| } |
| def C2_cmpgtp : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Pd4 = cmp.gt($Rss32,$Rtt32)", |
| tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { |
| let Inst{7-2} = 0b010000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010010100; |
| let isCompare = 1; |
| } |
| def C2_cmpgtu : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Pd4 = cmp.gtu($Rs32,$Rt32)", |
| tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { |
| let Inst{7-2} = 0b000000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110010011; |
| let CextOpcode = "C2_cmpgtu"; |
| let InputType = "reg"; |
| let isCompare = 1; |
| } |
| def C2_cmpgtui : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, u32_0Imm:$Ii), |
| "$Pd4 = cmp.gtu($Rs32,#$Ii)", |
| tc_d33e5eee, TypeALU32_2op>, Enc_c0cdde, ImmRegRel { |
| let Inst{4-2} = 0b000; |
| let Inst{31-21} = 0b01110101100; |
| let CextOpcode = "C2_cmpgtu"; |
| let InputType = "imm"; |
| let isCompare = 1; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 0; |
| let opExtentBits = 9; |
| let opExtentAlign = 0; |
| } |
| def C2_cmpgtup : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Pd4 = cmp.gtu($Rss32,$Rtt32)", |
| tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { |
| let Inst{7-2} = 0b100000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010010100; |
| let isCompare = 1; |
| } |
| def C2_cmplt : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Pd4 = cmp.lt($Rs32,$Rt32)", |
| tc_d33e5eee, TypeALU32_3op> { |
| let isCompare = 1; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def C2_cmpltu : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Pd4 = cmp.ltu($Rs32,$Rt32)", |
| tc_d33e5eee, TypeALU32_3op> { |
| let isCompare = 1; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def C2_mask : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins PredRegs:$Pt4), |
| "$Rdd32 = mask($Pt4)", |
| tc_9f6cd987, TypeS_2op>, Enc_78e566 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-10} = 0b0000; |
| let Inst{31-16} = 0b1000011000000000; |
| } |
| def C2_mux : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = mux($Pu4,$Rs32,$Rt32)", |
| tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54 { |
| let Inst{7-7} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110100000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let InputType = "reg"; |
| } |
| def C2_muxii : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, s32_0Imm:$Ii, s8_0Imm:$II), |
| "$Rd32 = mux($Pu4,#$Ii,#$II)", |
| tc_1c2c7a4a, TypeALU32_2op>, Enc_830e5d { |
| let Inst{31-25} = 0b0111101; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 8; |
| let opExtentAlign = 0; |
| } |
| def C2_muxir : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), |
| "$Rd32 = mux($Pu4,$Rs32,#$Ii)", |
| tc_1c2c7a4a, TypeALU32_2op>, Enc_e38e1f { |
| let Inst{13-13} = 0b0; |
| let Inst{31-23} = 0b011100110; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let InputType = "imm"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 1; |
| let opExtentBits = 8; |
| let opExtentAlign = 0; |
| } |
| def C2_muxri : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, s32_0Imm:$Ii, IntRegs:$Rs32), |
| "$Rd32 = mux($Pu4,#$Ii,$Rs32)", |
| tc_1c2c7a4a, TypeALU32_2op>, Enc_e38e1f { |
| let Inst{13-13} = 0b0; |
| let Inst{31-23} = 0b011100111; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let InputType = "imm"; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 8; |
| let opExtentAlign = 0; |
| } |
| def C2_not : HInst< |
| (outs PredRegs:$Pd4), |
| (ins PredRegs:$Ps4), |
| "$Pd4 = not($Ps4)", |
| tc_151bf368, TypeCR>, Enc_65d691 { |
| let Inst{13-2} = 0b000000000000; |
| let Inst{31-18} = 0b01101011110000; |
| } |
| def C2_or : HInst< |
| (outs PredRegs:$Pd4), |
| (ins PredRegs:$Pt4, PredRegs:$Ps4), |
| "$Pd4 = or($Pt4,$Ps4)", |
| tc_651cbe02, TypeCR>, Enc_454a26 { |
| let Inst{7-2} = 0b000000; |
| let Inst{13-10} = 0b0000; |
| let Inst{31-18} = 0b01101011001000; |
| } |
| def C2_orn : HInst< |
| (outs PredRegs:$Pd4), |
| (ins PredRegs:$Pt4, PredRegs:$Ps4), |
| "$Pd4 = or($Pt4,!$Ps4)", |
| tc_651cbe02, TypeCR>, Enc_454a26 { |
| let Inst{7-2} = 0b000000; |
| let Inst{13-10} = 0b0000; |
| let Inst{31-18} = 0b01101011111000; |
| } |
| def C2_pxfer_map : HInst< |
| (outs PredRegs:$Pd4), |
| (ins PredRegs:$Ps4), |
| "$Pd4 = $Ps4", |
| tc_651cbe02, TypeMAPPING> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def C2_tfrpr : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Ps4), |
| "$Rd32 = $Ps4", |
| tc_9f6cd987, TypeS_2op>, Enc_f5e933 { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-18} = 0b10001001010000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| } |
| def C2_tfrrp : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32), |
| "$Pd4 = $Rs32", |
| tc_55b33fda, TypeS_2op>, Enc_48b75f { |
| let Inst{13-2} = 0b000000000000; |
| let Inst{31-21} = 0b10000101010; |
| } |
| def C2_vitpack : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Ps4, PredRegs:$Pt4), |
| "$Rd32 = vitpack($Ps4,$Pt4)", |
| tc_f34c1c21, TypeS_2op>, Enc_527412 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-10} = 0b0000; |
| let Inst{31-18} = 0b10001001000000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def C2_vmux : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins PredRegs:$Pu4, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vmux($Pu4,$Rss32,$Rtt32)", |
| tc_6fc5dbea, TypeALU64>, Enc_329361 { |
| let Inst{7-7} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010001000; |
| } |
| def C2_xor : HInst< |
| (outs PredRegs:$Pd4), |
| (ins PredRegs:$Ps4, PredRegs:$Pt4), |
| "$Pd4 = xor($Ps4,$Pt4)", |
| tc_651cbe02, TypeCR>, Enc_284ebb { |
| let Inst{7-2} = 0b000000; |
| let Inst{13-10} = 0b0000; |
| let Inst{31-18} = 0b01101011010000; |
| } |
| def C4_addipc : HInst< |
| (outs IntRegs:$Rd32), |
| (ins u32_0Imm:$Ii), |
| "$Rd32 = add(pc,#$Ii)", |
| tc_3edca78f, TypeCR>, Enc_607661 { |
| let Inst{6-5} = 0b00; |
| let Inst{13-13} = 0b0; |
| let Inst{31-16} = 0b0110101001001001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def C4_and_and : HInst< |
| (outs PredRegs:$Pd4), |
| (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), |
| "$Pd4 = and($Ps4,and($Pt4,$Pu4))", |
| tc_a7a13fac, TypeCR>, Enc_9ac432 { |
| let Inst{5-2} = 0b0000; |
| let Inst{13-10} = 0b0000; |
| let Inst{31-18} = 0b01101011000100; |
| } |
| def C4_and_andn : HInst< |
| (outs PredRegs:$Pd4), |
| (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), |
| "$Pd4 = and($Ps4,and($Pt4,!$Pu4))", |
| tc_a7a13fac, TypeCR>, Enc_9ac432 { |
| let Inst{5-2} = 0b0000; |
| let Inst{13-10} = 0b0000; |
| let Inst{31-18} = 0b01101011100100; |
| } |
| def C4_and_or : HInst< |
| (outs PredRegs:$Pd4), |
| (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), |
| "$Pd4 = and($Ps4,or($Pt4,$Pu4))", |
| tc_a7a13fac, TypeCR>, Enc_9ac432 { |
| let Inst{5-2} = 0b0000; |
| let Inst{13-10} = 0b0000; |
| let Inst{31-18} = 0b01101011001100; |
| } |
| def C4_and_orn : HInst< |
| (outs PredRegs:$Pd4), |
| (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), |
| "$Pd4 = and($Ps4,or($Pt4,!$Pu4))", |
| tc_a7a13fac, TypeCR>, Enc_9ac432 { |
| let Inst{5-2} = 0b0000; |
| let Inst{13-10} = 0b0000; |
| let Inst{31-18} = 0b01101011101100; |
| } |
| def C4_cmplte : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Pd4 = !cmp.gt($Rs32,$Rt32)", |
| tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { |
| let Inst{7-2} = 0b000100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110010010; |
| let CextOpcode = "C4_cmplte"; |
| let InputType = "reg"; |
| let isCompare = 1; |
| } |
| def C4_cmpltei : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, s32_0Imm:$Ii), |
| "$Pd4 = !cmp.gt($Rs32,#$Ii)", |
| tc_d33e5eee, TypeALU32_2op>, Enc_bd0b33, ImmRegRel { |
| let Inst{4-2} = 0b100; |
| let Inst{31-22} = 0b0111010101; |
| let CextOpcode = "C4_cmplte"; |
| let InputType = "imm"; |
| let isCompare = 1; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 10; |
| let opExtentAlign = 0; |
| } |
| def C4_cmplteu : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Pd4 = !cmp.gtu($Rs32,$Rt32)", |
| tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { |
| let Inst{7-2} = 0b000100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110010011; |
| let CextOpcode = "C4_cmplteu"; |
| let InputType = "reg"; |
| let isCompare = 1; |
| } |
| def C4_cmplteui : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, u32_0Imm:$Ii), |
| "$Pd4 = !cmp.gtu($Rs32,#$Ii)", |
| tc_d33e5eee, TypeALU32_2op>, Enc_c0cdde, ImmRegRel { |
| let Inst{4-2} = 0b100; |
| let Inst{31-21} = 0b01110101100; |
| let CextOpcode = "C4_cmplteu"; |
| let InputType = "imm"; |
| let isCompare = 1; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 0; |
| let opExtentBits = 9; |
| let opExtentAlign = 0; |
| } |
| def C4_cmpneq : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Pd4 = !cmp.eq($Rs32,$Rt32)", |
| tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { |
| let Inst{7-2} = 0b000100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110010000; |
| let CextOpcode = "C4_cmpneq"; |
| let InputType = "reg"; |
| let isCommutable = 1; |
| let isCompare = 1; |
| } |
| def C4_cmpneqi : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, s32_0Imm:$Ii), |
| "$Pd4 = !cmp.eq($Rs32,#$Ii)", |
| tc_d33e5eee, TypeALU32_2op>, Enc_bd0b33, ImmRegRel { |
| let Inst{4-2} = 0b100; |
| let Inst{31-22} = 0b0111010100; |
| let CextOpcode = "C4_cmpneq"; |
| let InputType = "imm"; |
| let isCompare = 1; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 10; |
| let opExtentAlign = 0; |
| } |
| def C4_fastcorner9 : HInst< |
| (outs PredRegs:$Pd4), |
| (ins PredRegs:$Ps4, PredRegs:$Pt4), |
| "$Pd4 = fastcorner9($Ps4,$Pt4)", |
| tc_651cbe02, TypeCR>, Enc_284ebb { |
| let Inst{7-2} = 0b100100; |
| let Inst{13-10} = 0b1000; |
| let Inst{31-18} = 0b01101011000000; |
| } |
| def C4_fastcorner9_not : HInst< |
| (outs PredRegs:$Pd4), |
| (ins PredRegs:$Ps4, PredRegs:$Pt4), |
| "$Pd4 = !fastcorner9($Ps4,$Pt4)", |
| tc_651cbe02, TypeCR>, Enc_284ebb { |
| let Inst{7-2} = 0b100100; |
| let Inst{13-10} = 0b1000; |
| let Inst{31-18} = 0b01101011000100; |
| } |
| def C4_nbitsclr : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Pd4 = !bitsclr($Rs32,$Rt32)", |
| tc_4a55d03c, TypeS_3op>, Enc_c2b48e { |
| let Inst{7-2} = 0b000000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11000111101; |
| } |
| def C4_nbitsclri : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, u6_0Imm:$Ii), |
| "$Pd4 = !bitsclr($Rs32,#$Ii)", |
| tc_a1297125, TypeS_2op>, Enc_5d6c34 { |
| let Inst{7-2} = 0b000000; |
| let Inst{31-21} = 0b10000101101; |
| } |
| def C4_nbitsset : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Pd4 = !bitsset($Rs32,$Rt32)", |
| tc_4a55d03c, TypeS_3op>, Enc_c2b48e { |
| let Inst{7-2} = 0b000000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11000111011; |
| } |
| def C4_or_and : HInst< |
| (outs PredRegs:$Pd4), |
| (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), |
| "$Pd4 = or($Ps4,and($Pt4,$Pu4))", |
| tc_a7a13fac, TypeCR>, Enc_9ac432 { |
| let Inst{5-2} = 0b0000; |
| let Inst{13-10} = 0b0000; |
| let Inst{31-18} = 0b01101011010100; |
| } |
| def C4_or_andn : HInst< |
| (outs PredRegs:$Pd4), |
| (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), |
| "$Pd4 = or($Ps4,and($Pt4,!$Pu4))", |
| tc_a7a13fac, TypeCR>, Enc_9ac432 { |
| let Inst{5-2} = 0b0000; |
| let Inst{13-10} = 0b0000; |
| let Inst{31-18} = 0b01101011110100; |
| } |
| def C4_or_or : HInst< |
| (outs PredRegs:$Pd4), |
| (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), |
| "$Pd4 = or($Ps4,or($Pt4,$Pu4))", |
| tc_a7a13fac, TypeCR>, Enc_9ac432 { |
| let Inst{5-2} = 0b0000; |
| let Inst{13-10} = 0b0000; |
| let Inst{31-18} = 0b01101011011100; |
| } |
| def C4_or_orn : HInst< |
| (outs PredRegs:$Pd4), |
| (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), |
| "$Pd4 = or($Ps4,or($Pt4,!$Pu4))", |
| tc_a7a13fac, TypeCR>, Enc_9ac432 { |
| let Inst{5-2} = 0b0000; |
| let Inst{13-10} = 0b0000; |
| let Inst{31-18} = 0b01101011111100; |
| } |
| def F2_conv_d2df : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32), |
| "$Rdd32 = convert_d2df($Rss32)", |
| tc_9783714b, TypeS_2op>, Enc_b9c5fb { |
| let Inst{13-5} = 0b000000011; |
| let Inst{31-21} = 0b10000000111; |
| let isFP = 1; |
| let Uses = [USR]; |
| } |
| def F2_conv_d2sf : HInst< |
| (outs IntRegs:$Rd32), |
| (ins DoubleRegs:$Rss32), |
| "$Rd32 = convert_d2sf($Rss32)", |
| tc_9783714b, TypeS_2op>, Enc_90cd8b { |
| let Inst{13-5} = 0b000000001; |
| let Inst{31-21} = 0b10001000010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isFP = 1; |
| let Uses = [USR]; |
| } |
| def F2_conv_df2d : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32), |
| "$Rdd32 = convert_df2d($Rss32)", |
| tc_9783714b, TypeS_2op>, Enc_b9c5fb { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-21} = 0b10000000111; |
| let isFP = 1; |
| let Uses = [USR]; |
| } |
| def F2_conv_df2d_chop : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32), |
| "$Rdd32 = convert_df2d($Rss32):chop", |
| tc_9783714b, TypeS_2op>, Enc_b9c5fb { |
| let Inst{13-5} = 0b000000110; |
| let Inst{31-21} = 0b10000000111; |
| let isFP = 1; |
| let Uses = [USR]; |
| } |
| def F2_conv_df2sf : HInst< |
| (outs IntRegs:$Rd32), |
| (ins DoubleRegs:$Rss32), |
| "$Rd32 = convert_df2sf($Rss32)", |
| tc_9783714b, TypeS_2op>, Enc_90cd8b { |
| let Inst{13-5} = 0b000000001; |
| let Inst{31-21} = 0b10001000000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isFP = 1; |
| let Uses = [USR]; |
| } |
| def F2_conv_df2ud : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32), |
| "$Rdd32 = convert_df2ud($Rss32)", |
| tc_9783714b, TypeS_2op>, Enc_b9c5fb { |
| let Inst{13-5} = 0b000000001; |
| let Inst{31-21} = 0b10000000111; |
| let isFP = 1; |
| let Uses = [USR]; |
| } |
| def F2_conv_df2ud_chop : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32), |
| "$Rdd32 = convert_df2ud($Rss32):chop", |
| tc_9783714b, TypeS_2op>, Enc_b9c5fb { |
| let Inst{13-5} = 0b000000111; |
| let Inst{31-21} = 0b10000000111; |
| let isFP = 1; |
| let Uses = [USR]; |
| } |
| def F2_conv_df2uw : HInst< |
| (outs IntRegs:$Rd32), |
| (ins DoubleRegs:$Rss32), |
| "$Rd32 = convert_df2uw($Rss32)", |
| tc_9783714b, TypeS_2op>, Enc_90cd8b { |
| let Inst{13-5} = 0b000000001; |
| let Inst{31-21} = 0b10001000011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isFP = 1; |
| let Uses = [USR]; |
| } |
| def F2_conv_df2uw_chop : HInst< |
| (outs IntRegs:$Rd32), |
| (ins DoubleRegs:$Rss32), |
| "$Rd32 = convert_df2uw($Rss32):chop", |
| tc_9783714b, TypeS_2op>, Enc_90cd8b { |
| let Inst{13-5} = 0b000000001; |
| let Inst{31-21} = 0b10001000101; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isFP = 1; |
| let Uses = [USR]; |
| } |
| def F2_conv_df2w : HInst< |
| (outs IntRegs:$Rd32), |
| (ins DoubleRegs:$Rss32), |
| "$Rd32 = convert_df2w($Rss32)", |
| tc_9783714b, TypeS_2op>, Enc_90cd8b { |
| let Inst{13-5} = 0b000000001; |
| let Inst{31-21} = 0b10001000100; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isFP = 1; |
| let Uses = [USR]; |
| } |
| def F2_conv_df2w_chop : HInst< |
| (outs IntRegs:$Rd32), |
| (ins DoubleRegs:$Rss32), |
| "$Rd32 = convert_df2w($Rss32):chop", |
| tc_9783714b, TypeS_2op>, Enc_90cd8b { |
| let Inst{13-5} = 0b000000001; |
| let Inst{31-21} = 0b10001000111; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isFP = 1; |
| let Uses = [USR]; |
| } |
| def F2_conv_sf2d : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins IntRegs:$Rs32), |
| "$Rdd32 = convert_sf2d($Rs32)", |
| tc_9783714b, TypeS_2op>, Enc_3a3d62 { |
| let Inst{13-5} = 0b000000100; |
| let Inst{31-21} = 0b10000100100; |
| let isFP = 1; |
| let Uses = [USR]; |
| } |
| def F2_conv_sf2d_chop : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins IntRegs:$Rs32), |
| "$Rdd32 = convert_sf2d($Rs32):chop", |
| tc_9783714b, TypeS_2op>, Enc_3a3d62 { |
| let Inst{13-5} = 0b000000110; |
| let Inst{31-21} = 0b10000100100; |
| let isFP = 1; |
| let Uses = [USR]; |
| } |
| def F2_conv_sf2df : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins IntRegs:$Rs32), |
| "$Rdd32 = convert_sf2df($Rs32)", |
| tc_9783714b, TypeS_2op>, Enc_3a3d62 { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-21} = 0b10000100100; |
| let isFP = 1; |
| let Uses = [USR]; |
| } |
| def F2_conv_sf2ud : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins IntRegs:$Rs32), |
| "$Rdd32 = convert_sf2ud($Rs32)", |
| tc_9783714b, TypeS_2op>, Enc_3a3d62 { |
| let Inst{13-5} = 0b000000011; |
| let Inst{31-21} = 0b10000100100; |
| let isFP = 1; |
| let Uses = [USR]; |
| } |
| def F2_conv_sf2ud_chop : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins IntRegs:$Rs32), |
| "$Rdd32 = convert_sf2ud($Rs32):chop", |
| tc_9783714b, TypeS_2op>, Enc_3a3d62 { |
| let Inst{13-5} = 0b000000101; |
| let Inst{31-21} = 0b10000100100; |
| let isFP = 1; |
| let Uses = [USR]; |
| } |
| def F2_conv_sf2uw : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = convert_sf2uw($Rs32)", |
| tc_9783714b, TypeS_2op>, Enc_5e2823 { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-21} = 0b10001011011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isFP = 1; |
| let Uses = [USR]; |
| } |
| def F2_conv_sf2uw_chop : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = convert_sf2uw($Rs32):chop", |
| tc_9783714b, TypeS_2op>, Enc_5e2823 { |
| let Inst{13-5} = 0b000000001; |
| let Inst{31-21} = 0b10001011011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isFP = 1; |
| let Uses = [USR]; |
| } |
| def F2_conv_sf2w : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = convert_sf2w($Rs32)", |
| tc_9783714b, TypeS_2op>, Enc_5e2823 { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-21} = 0b10001011100; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isFP = 1; |
| let Uses = [USR]; |
| } |
| def F2_conv_sf2w_chop : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = convert_sf2w($Rs32):chop", |
| tc_9783714b, TypeS_2op>, Enc_5e2823 { |
| let Inst{13-5} = 0b000000001; |
| let Inst{31-21} = 0b10001011100; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isFP = 1; |
| let Uses = [USR]; |
| } |
| def F2_conv_ud2df : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32), |
| "$Rdd32 = convert_ud2df($Rss32)", |
| tc_9783714b, TypeS_2op>, Enc_b9c5fb { |
| let Inst{13-5} = 0b000000010; |
| let Inst{31-21} = 0b10000000111; |
| let isFP = 1; |
| let Uses = [USR]; |
| } |
| def F2_conv_ud2sf : HInst< |
| (outs IntRegs:$Rd32), |
| (ins DoubleRegs:$Rss32), |
| "$Rd32 = convert_ud2sf($Rss32)", |
| tc_9783714b, TypeS_2op>, Enc_90cd8b { |
| let Inst{13-5} = 0b000000001; |
| let Inst{31-21} = 0b10001000001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isFP = 1; |
| let Uses = [USR]; |
| } |
| def F2_conv_uw2df : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins IntRegs:$Rs32), |
| "$Rdd32 = convert_uw2df($Rs32)", |
| tc_9783714b, TypeS_2op>, Enc_3a3d62 { |
| let Inst{13-5} = 0b000000001; |
| let Inst{31-21} = 0b10000100100; |
| let isFP = 1; |
| let Uses = [USR]; |
| } |
| def F2_conv_uw2sf : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = convert_uw2sf($Rs32)", |
| tc_9783714b, TypeS_2op>, Enc_5e2823 { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-21} = 0b10001011001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isFP = 1; |
| let Uses = [USR]; |
| } |
| def F2_conv_w2df : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins IntRegs:$Rs32), |
| "$Rdd32 = convert_w2df($Rs32)", |
| tc_9783714b, TypeS_2op>, Enc_3a3d62 { |
| let Inst{13-5} = 0b000000010; |
| let Inst{31-21} = 0b10000100100; |
| let isFP = 1; |
| let Uses = [USR]; |
| } |
| def F2_conv_w2sf : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = convert_w2sf($Rs32)", |
| tc_9783714b, TypeS_2op>, Enc_5e2823 { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-21} = 0b10001011010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isFP = 1; |
| let Uses = [USR]; |
| } |
| def F2_dfadd : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = dfadd($Rss32,$Rtt32)", |
| tc_f0e8e832, TypeM>, Enc_a56825, Requires<[HasV66]> { |
| let Inst{7-5} = 0b011; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11101000000; |
| let isFP = 1; |
| let Uses = [USR]; |
| } |
| def F2_dfclass : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, u5_0Imm:$Ii), |
| "$Pd4 = dfclass($Rss32,#$Ii)", |
| tc_a1297125, TypeALU64>, Enc_1f19b5 { |
| let Inst{4-2} = 0b100; |
| let Inst{13-10} = 0b0000; |
| let Inst{31-21} = 0b11011100100; |
| let isFP = 1; |
| let Uses = [USR]; |
| } |
| def F2_dfcmpeq : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Pd4 = dfcmp.eq($Rss32,$Rtt32)", |
| tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { |
| let Inst{7-2} = 0b000000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010010111; |
| let isFP = 1; |
| let Uses = [USR]; |
| let isCompare = 1; |
| } |
| def F2_dfcmpge : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Pd4 = dfcmp.ge($Rss32,$Rtt32)", |
| tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { |
| let Inst{7-2} = 0b010000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010010111; |
| let isFP = 1; |
| let Uses = [USR]; |
| let isCompare = 1; |
| } |
| def F2_dfcmpgt : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Pd4 = dfcmp.gt($Rss32,$Rtt32)", |
| tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { |
| let Inst{7-2} = 0b001000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010010111; |
| let isFP = 1; |
| let Uses = [USR]; |
| let isCompare = 1; |
| } |
| def F2_dfcmpuo : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Pd4 = dfcmp.uo($Rss32,$Rtt32)", |
| tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { |
| let Inst{7-2} = 0b011000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010010111; |
| let isFP = 1; |
| let Uses = [USR]; |
| let isCompare = 1; |
| } |
| def F2_dfimm_n : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins u10_0Imm:$Ii), |
| "$Rdd32 = dfmake(#$Ii):neg", |
| tc_65279839, TypeALU64>, Enc_e6c957 { |
| let Inst{20-16} = 0b00000; |
| let Inst{31-22} = 0b1101100101; |
| let prefersSlot3 = 1; |
| } |
| def F2_dfimm_p : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins u10_0Imm:$Ii), |
| "$Rdd32 = dfmake(#$Ii):pos", |
| tc_65279839, TypeALU64>, Enc_e6c957 { |
| let Inst{20-16} = 0b00000; |
| let Inst{31-22} = 0b1101100100; |
| let prefersSlot3 = 1; |
| } |
| def F2_dfmax : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = dfmax($Rss32,$Rtt32)", |
| tc_9b3c0462, TypeM>, Enc_a56825, Requires<[HasV67]> { |
| let Inst{7-5} = 0b011; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11101000001; |
| let isFP = 1; |
| let prefersSlot3 = 1; |
| let Uses = [USR]; |
| } |
| def F2_dfmin : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = dfmin($Rss32,$Rtt32)", |
| tc_9b3c0462, TypeM>, Enc_a56825, Requires<[HasV67]> { |
| let Inst{7-5} = 0b011; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11101000110; |
| let isFP = 1; |
| let prefersSlot3 = 1; |
| let Uses = [USR]; |
| } |
| def F2_dfmpyfix : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = dfmpyfix($Rss32,$Rtt32)", |
| tc_f0e8e832, TypeM>, Enc_a56825, Requires<[HasV67]> { |
| let Inst{7-5} = 0b011; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11101000010; |
| let isFP = 1; |
| let Uses = [USR]; |
| } |
| def F2_dfmpyhh : HInst< |
| (outs DoubleRegs:$Rxx32), |
| (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rxx32 += dfmpyhh($Rss32,$Rtt32)", |
| tc_0a195f2c, TypeM>, Enc_88c16c, Requires<[HasV67]> { |
| let Inst{7-5} = 0b011; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11101010100; |
| let isFP = 1; |
| let Uses = [USR]; |
| let Constraints = "$Rxx32 = $Rxx32in"; |
| } |
| def F2_dfmpylh : HInst< |
| (outs DoubleRegs:$Rxx32), |
| (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rxx32 += dfmpylh($Rss32,$Rtt32)", |
| tc_01e1be3b, TypeM>, Enc_88c16c, Requires<[HasV67]> { |
| let Inst{7-5} = 0b011; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11101010000; |
| let prefersSlot3 = 1; |
| let Constraints = "$Rxx32 = $Rxx32in"; |
| } |
| def F2_dfmpyll : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = dfmpyll($Rss32,$Rtt32)", |
| tc_556f6577, TypeM>, Enc_a56825, Requires<[HasV67]> { |
| let Inst{7-5} = 0b011; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11101000101; |
| let prefersSlot3 = 1; |
| } |
| def F2_dfsub : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = dfsub($Rss32,$Rtt32)", |
| tc_f0e8e832, TypeM>, Enc_a56825, Requires<[HasV66]> { |
| let Inst{7-5} = 0b011; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11101000100; |
| let isFP = 1; |
| let Uses = [USR]; |
| } |
| def F2_sfadd : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = sfadd($Rs32,$Rt32)", |
| tc_02fe1c65, TypeM>, Enc_5ab2be { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11101011000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isFP = 1; |
| let Uses = [USR]; |
| let isCommutable = 1; |
| } |
| def F2_sfclass : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, u5_0Imm:$Ii), |
| "$Pd4 = sfclass($Rs32,#$Ii)", |
| tc_a1297125, TypeS_2op>, Enc_83ee64 { |
| let Inst{7-2} = 0b000000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b10000101111; |
| let isFP = 1; |
| let Uses = [USR]; |
| } |
| def F2_sfcmpeq : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Pd4 = sfcmp.eq($Rs32,$Rt32)", |
| tc_4a55d03c, TypeS_3op>, Enc_c2b48e { |
| let Inst{7-2} = 0b011000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11000111111; |
| let isFP = 1; |
| let Uses = [USR]; |
| let isCompare = 1; |
| } |
| def F2_sfcmpge : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Pd4 = sfcmp.ge($Rs32,$Rt32)", |
| tc_4a55d03c, TypeS_3op>, Enc_c2b48e { |
| let Inst{7-2} = 0b000000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11000111111; |
| let isFP = 1; |
| let Uses = [USR]; |
| let isCompare = 1; |
| } |
| def F2_sfcmpgt : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Pd4 = sfcmp.gt($Rs32,$Rt32)", |
| tc_4a55d03c, TypeS_3op>, Enc_c2b48e { |
| let Inst{7-2} = 0b100000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11000111111; |
| let isFP = 1; |
| let Uses = [USR]; |
| let isCompare = 1; |
| } |
| def F2_sfcmpuo : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Pd4 = sfcmp.uo($Rs32,$Rt32)", |
| tc_4a55d03c, TypeS_3op>, Enc_c2b48e { |
| let Inst{7-2} = 0b001000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11000111111; |
| let isFP = 1; |
| let Uses = [USR]; |
| let isCompare = 1; |
| } |
| def F2_sffixupd : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = sffixupd($Rs32,$Rt32)", |
| tc_02fe1c65, TypeM>, Enc_5ab2be { |
| let Inst{7-5} = 0b001; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11101011110; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isFP = 1; |
| } |
| def F2_sffixupn : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = sffixupn($Rs32,$Rt32)", |
| tc_02fe1c65, TypeM>, Enc_5ab2be { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11101011110; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isFP = 1; |
| } |
| def F2_sffixupr : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = sffixupr($Rs32)", |
| tc_9783714b, TypeS_2op>, Enc_5e2823 { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-21} = 0b10001011101; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isFP = 1; |
| } |
| def F2_sffma : HInst< |
| (outs IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rx32 += sfmpy($Rs32,$Rt32)", |
| tc_9e72dc89, TypeM>, Enc_2ae154 { |
| let Inst{7-5} = 0b100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11101111000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isFP = 1; |
| let Uses = [USR]; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def F2_sffma_lib : HInst< |
| (outs IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rx32 += sfmpy($Rs32,$Rt32):lib", |
| tc_9e72dc89, TypeM>, Enc_2ae154 { |
| let Inst{7-5} = 0b110; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11101111000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isFP = 1; |
| let Uses = [USR]; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def F2_sffma_sc : HInst< |
| (outs IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32, PredRegs:$Pu4), |
| "$Rx32 += sfmpy($Rs32,$Rt32,$Pu4):scale", |
| tc_9edb7c77, TypeM>, Enc_437f33 { |
| let Inst{7-7} = 0b1; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11101111011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isFP = 1; |
| let Uses = [USR]; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def F2_sffms : HInst< |
| (outs IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rx32 -= sfmpy($Rs32,$Rt32)", |
| tc_9e72dc89, TypeM>, Enc_2ae154 { |
| let Inst{7-5} = 0b101; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11101111000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isFP = 1; |
| let Uses = [USR]; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def F2_sffms_lib : HInst< |
| (outs IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rx32 -= sfmpy($Rs32,$Rt32):lib", |
| tc_9e72dc89, TypeM>, Enc_2ae154 { |
| let Inst{7-5} = 0b111; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11101111000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isFP = 1; |
| let Uses = [USR]; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def F2_sfimm_n : HInst< |
| (outs IntRegs:$Rd32), |
| (ins u10_0Imm:$Ii), |
| "$Rd32 = sfmake(#$Ii):neg", |
| tc_65279839, TypeALU64>, Enc_6c9440 { |
| let Inst{20-16} = 0b00000; |
| let Inst{31-22} = 0b1101011001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def F2_sfimm_p : HInst< |
| (outs IntRegs:$Rd32), |
| (ins u10_0Imm:$Ii), |
| "$Rd32 = sfmake(#$Ii):pos", |
| tc_65279839, TypeALU64>, Enc_6c9440 { |
| let Inst{20-16} = 0b00000; |
| let Inst{31-22} = 0b1101011000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def F2_sfinvsqrta : HInst< |
| (outs IntRegs:$Rd32, PredRegs:$Pe4), |
| (ins IntRegs:$Rs32), |
| "$Rd32,$Pe4 = sfinvsqrta($Rs32)", |
| tc_7f7f45f5, TypeS_2op>, Enc_890909 { |
| let Inst{13-7} = 0b0000000; |
| let Inst{31-21} = 0b10001011111; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isFP = 1; |
| let isPredicateLate = 1; |
| } |
| def F2_sfmax : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = sfmax($Rs32,$Rt32)", |
| tc_c20701f0, TypeM>, Enc_5ab2be { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11101011100; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isFP = 1; |
| let prefersSlot3 = 1; |
| let Uses = [USR]; |
| } |
| def F2_sfmin : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = sfmin($Rs32,$Rt32)", |
| tc_c20701f0, TypeM>, Enc_5ab2be { |
| let Inst{7-5} = 0b001; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11101011100; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isFP = 1; |
| let prefersSlot3 = 1; |
| let Uses = [USR]; |
| } |
| def F2_sfmpy : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = sfmpy($Rs32,$Rt32)", |
| tc_02fe1c65, TypeM>, Enc_5ab2be { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11101011010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isFP = 1; |
| let Uses = [USR]; |
| let isCommutable = 1; |
| } |
| def F2_sfrecipa : HInst< |
| (outs IntRegs:$Rd32, PredRegs:$Pe4), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32,$Pe4 = sfrecipa($Rs32,$Rt32)", |
| tc_f7569068, TypeM>, Enc_a94f3b { |
| let Inst{7-7} = 0b1; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11101011111; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isFP = 1; |
| let isPredicateLate = 1; |
| } |
| def F2_sfsub : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = sfsub($Rs32,$Rt32)", |
| tc_02fe1c65, TypeM>, Enc_5ab2be { |
| let Inst{7-5} = 0b001; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11101011000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isFP = 1; |
| let Uses = [USR]; |
| } |
| def G4_tfrgcpp : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins GuestRegs64:$Gss32), |
| "$Rdd32 = $Gss32", |
| tc_fae9dfa5, TypeCR>, Enc_0aa344 { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-21} = 0b01101000001; |
| } |
| def G4_tfrgcrr : HInst< |
| (outs IntRegs:$Rd32), |
| (ins GuestRegs:$Gs32), |
| "$Rd32 = $Gs32", |
| tc_fae9dfa5, TypeCR>, Enc_44271f { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-21} = 0b01101010001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| } |
| def G4_tfrgpcp : HInst< |
| (outs GuestRegs64:$Gdd32), |
| (ins DoubleRegs:$Rss32), |
| "$Gdd32 = $Rss32", |
| tc_6ae3426b, TypeCR>, Enc_ed5027 { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-21} = 0b01100011000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| } |
| def G4_tfrgrcr : HInst< |
| (outs GuestRegs:$Gd32), |
| (ins IntRegs:$Rs32), |
| "$Gd32 = $Rs32", |
| tc_6ae3426b, TypeCR>, Enc_621fba { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-21} = 0b01100010000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| } |
| def J2_call : HInst< |
| (outs), |
| (ins a30_2Imm:$Ii), |
| "call $Ii", |
| tc_44fffc58, TypeJ>, Enc_81ac1d, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{31-25} = 0b0101101; |
| let isCall = 1; |
| let prefersSlot3 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [R29]; |
| let Defs = [PC, R31]; |
| let BaseOpcode = "J2_call"; |
| let hasSideEffects = 1; |
| let isPredicable = 1; |
| let isExtendable = 1; |
| let opExtendable = 0; |
| let isExtentSigned = 1; |
| let opExtentBits = 24; |
| let opExtentAlign = 2; |
| } |
| def J2_callf : HInst< |
| (outs), |
| (ins PredRegs:$Pu4, a30_2Imm:$Ii), |
| "if (!$Pu4) call $Ii", |
| tc_69bfb303, TypeJ>, Enc_daea09, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{12-10} = 0b000; |
| let Inst{21-21} = 0b1; |
| let Inst{31-24} = 0b01011101; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isCall = 1; |
| let prefersSlot3 = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [R29]; |
| let Defs = [PC, R31]; |
| let BaseOpcode = "J2_call"; |
| let hasSideEffects = 1; |
| let isTaken = Inst{12}; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 1; |
| let opExtentBits = 17; |
| let opExtentAlign = 2; |
| } |
| def J2_callr : HInst< |
| (outs), |
| (ins IntRegs:$Rs32), |
| "callr $Rs32", |
| tc_362b0be2, TypeJ>, Enc_ecbcc8 { |
| let Inst{13-0} = 0b00000000000000; |
| let Inst{31-21} = 0b01010000101; |
| let isCall = 1; |
| let prefersSlot3 = 1; |
| let cofMax1 = 1; |
| let Uses = [R29]; |
| let Defs = [PC, R31]; |
| let hasSideEffects = 1; |
| } |
| def J2_callrf : HInst< |
| (outs), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if (!$Pu4) callr $Rs32", |
| tc_dc51281d, TypeJ>, Enc_88d4d9 { |
| let Inst{7-0} = 0b00000000; |
| let Inst{13-10} = 0b0000; |
| let Inst{31-21} = 0b01010001001; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isCall = 1; |
| let prefersSlot3 = 1; |
| let cofMax1 = 1; |
| let Uses = [R29]; |
| let Defs = [PC, R31]; |
| let hasSideEffects = 1; |
| let isTaken = Inst{12}; |
| } |
| def J2_callrt : HInst< |
| (outs), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if ($Pu4) callr $Rs32", |
| tc_dc51281d, TypeJ>, Enc_88d4d9 { |
| let Inst{7-0} = 0b00000000; |
| let Inst{13-10} = 0b0000; |
| let Inst{31-21} = 0b01010001000; |
| let isPredicated = 1; |
| let isCall = 1; |
| let prefersSlot3 = 1; |
| let cofMax1 = 1; |
| let Uses = [R29]; |
| let Defs = [PC, R31]; |
| let hasSideEffects = 1; |
| let isTaken = Inst{12}; |
| } |
| def J2_callt : HInst< |
| (outs), |
| (ins PredRegs:$Pu4, a30_2Imm:$Ii), |
| "if ($Pu4) call $Ii", |
| tc_69bfb303, TypeJ>, Enc_daea09, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{12-10} = 0b000; |
| let Inst{21-21} = 0b0; |
| let Inst{31-24} = 0b01011101; |
| let isPredicated = 1; |
| let isCall = 1; |
| let prefersSlot3 = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [R29]; |
| let Defs = [PC, R31]; |
| let BaseOpcode = "J2_call"; |
| let hasSideEffects = 1; |
| let isTaken = Inst{12}; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 1; |
| let opExtentBits = 17; |
| let opExtentAlign = 2; |
| } |
| def J2_endloop0 : HInst< |
| (outs), |
| (ins), |
| "endloop0", |
| tc_23708a21, TypeJ> { |
| let Uses = [LC0, SA0]; |
| let Defs = [LC0, P3, PC, USR]; |
| let isBranch = 1; |
| let isTerminator = 1; |
| let isPseudo = 1; |
| } |
| def J2_endloop01 : HInst< |
| (outs), |
| (ins), |
| "endloop01", |
| tc_23708a21, TypeJ> { |
| let Uses = [LC0, LC1, SA0, SA1]; |
| let Defs = [LC0, LC1, P3, PC, USR]; |
| let isPseudo = 1; |
| } |
| def J2_endloop1 : HInst< |
| (outs), |
| (ins), |
| "endloop1", |
| tc_23708a21, TypeJ> { |
| let Uses = [LC1, SA1]; |
| let Defs = [LC1, PC]; |
| let isBranch = 1; |
| let isTerminator = 1; |
| let isPseudo = 1; |
| } |
| def J2_jump : HInst< |
| (outs), |
| (ins b30_2Imm:$Ii), |
| "jump $Ii", |
| tc_decdde8a, TypeJ>, Enc_81ac1d, PredNewRel { |
| let Inst{0-0} = 0b0; |
| let Inst{31-25} = 0b0101100; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J2_jump"; |
| let InputType = "imm"; |
| let isBarrier = 1; |
| let isPredicable = 1; |
| let isExtendable = 1; |
| let opExtendable = 0; |
| let isExtentSigned = 1; |
| let opExtentBits = 24; |
| let opExtentAlign = 2; |
| } |
| def J2_jumpf : HInst< |
| (outs), |
| (ins PredRegs:$Pu4, b30_2Imm:$Ii), |
| "if (!$Pu4) jump:nt $Ii", |
| tc_56a124a7, TypeJ>, Enc_daea09, PredNewRel { |
| let Inst{0-0} = 0b0; |
| let Inst{12-10} = 0b000; |
| let Inst{21-21} = 0b1; |
| let Inst{31-24} = 0b01011100; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J2_jump"; |
| let InputType = "imm"; |
| let isTaken = Inst{12}; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 1; |
| let opExtentBits = 17; |
| let opExtentAlign = 2; |
| } |
| def J2_jumpf_nopred_map : HInst< |
| (outs), |
| (ins PredRegs:$Pu4, b15_2Imm:$Ii), |
| "if (!$Pu4) jump $Ii", |
| tc_56a124a7, TypeMAPPING>, Requires<[HasV60]> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def J2_jumpfnew : HInst< |
| (outs), |
| (ins PredRegs:$Pu4, b30_2Imm:$Ii), |
| "if (!$Pu4.new) jump:nt $Ii", |
| tc_eeda4109, TypeJ>, Enc_daea09, PredNewRel { |
| let Inst{0-0} = 0b0; |
| let Inst{12-10} = 0b010; |
| let Inst{21-21} = 0b1; |
| let Inst{31-24} = 0b01011100; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J2_jump"; |
| let InputType = "imm"; |
| let isTaken = Inst{12}; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 1; |
| let opExtentBits = 17; |
| let opExtentAlign = 2; |
| } |
| def J2_jumpfnewpt : HInst< |
| (outs), |
| (ins PredRegs:$Pu4, b30_2Imm:$Ii), |
| "if (!$Pu4.new) jump:t $Ii", |
| tc_eeda4109, TypeJ>, Enc_daea09, PredNewRel { |
| let Inst{0-0} = 0b0; |
| let Inst{12-10} = 0b110; |
| let Inst{21-21} = 0b1; |
| let Inst{31-24} = 0b01011100; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J2_jump"; |
| let InputType = "imm"; |
| let isTaken = Inst{12}; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 1; |
| let opExtentBits = 17; |
| let opExtentAlign = 2; |
| } |
| def J2_jumpfpt : HInst< |
| (outs), |
| (ins PredRegs:$Pu4, b30_2Imm:$Ii), |
| "if (!$Pu4) jump:t $Ii", |
| tc_711c805f, TypeJ>, Enc_daea09, Requires<[HasV60]>, PredNewRel { |
| let Inst{0-0} = 0b0; |
| let Inst{12-10} = 0b100; |
| let Inst{21-21} = 0b1; |
| let Inst{31-24} = 0b01011100; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J2_jump"; |
| let InputType = "imm"; |
| let isTaken = Inst{12}; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 1; |
| let opExtentBits = 17; |
| let opExtentAlign = 2; |
| } |
| def J2_jumpr : HInst< |
| (outs), |
| (ins IntRegs:$Rs32), |
| "jumpr $Rs32", |
| tc_60e324ff, TypeJ>, Enc_ecbcc8, PredNewRel { |
| let Inst{13-0} = 0b00000000000000; |
| let Inst{31-21} = 0b01010010100; |
| let isTerminator = 1; |
| let isIndirectBranch = 1; |
| let isBranch = 1; |
| let cofMax1 = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J2_jumpr"; |
| let InputType = "reg"; |
| let isBarrier = 1; |
| let isPredicable = 1; |
| } |
| def J2_jumprf : HInst< |
| (outs), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if (!$Pu4) jumpr:nt $Rs32", |
| tc_2f573607, TypeJ>, Enc_88d4d9, PredNewRel { |
| let Inst{7-0} = 0b00000000; |
| let Inst{13-10} = 0b0000; |
| let Inst{31-21} = 0b01010011011; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isIndirectBranch = 1; |
| let isBranch = 1; |
| let cofMax1 = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J2_jumpr"; |
| let InputType = "reg"; |
| let isTaken = Inst{12}; |
| } |
| def J2_jumprf_nopred_map : HInst< |
| (outs), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if (!$Pu4) jumpr $Rs32", |
| tc_2f573607, TypeMAPPING>, Requires<[HasV60]> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def J2_jumprfnew : HInst< |
| (outs), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if (!$Pu4.new) jumpr:nt $Rs32", |
| tc_ed03645c, TypeJ>, Enc_88d4d9, PredNewRel { |
| let Inst{7-0} = 0b00000000; |
| let Inst{13-10} = 0b0010; |
| let Inst{31-21} = 0b01010011011; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isIndirectBranch = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofMax1 = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J2_jumpr"; |
| let InputType = "reg"; |
| let isTaken = Inst{12}; |
| } |
| def J2_jumprfnewpt : HInst< |
| (outs), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if (!$Pu4.new) jumpr:t $Rs32", |
| tc_ed03645c, TypeJ>, Enc_88d4d9, PredNewRel { |
| let Inst{7-0} = 0b00000000; |
| let Inst{13-10} = 0b0110; |
| let Inst{31-21} = 0b01010011011; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isIndirectBranch = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofMax1 = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J2_jumpr"; |
| let InputType = "reg"; |
| let isTaken = Inst{12}; |
| } |
| def J2_jumprfpt : HInst< |
| (outs), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if (!$Pu4) jumpr:t $Rs32", |
| tc_42ff66ba, TypeJ>, Enc_88d4d9, Requires<[HasV60]>, PredNewRel { |
| let Inst{7-0} = 0b00000000; |
| let Inst{13-10} = 0b0100; |
| let Inst{31-21} = 0b01010011011; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isIndirectBranch = 1; |
| let isBranch = 1; |
| let cofMax1 = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J2_jumpr"; |
| let InputType = "reg"; |
| let isTaken = Inst{12}; |
| } |
| def J2_jumprgtez : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, b13_2Imm:$Ii), |
| "if ($Rs32>=#0) jump:nt $Ii", |
| tc_57a55b54, TypeCR>, Enc_0fa531 { |
| let Inst{0-0} = 0b0; |
| let Inst{12-12} = 0b0; |
| let Inst{31-22} = 0b0110000101; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Defs = [PC]; |
| let isTaken = Inst{12}; |
| } |
| def J2_jumprgtezpt : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, b13_2Imm:$Ii), |
| "if ($Rs32>=#0) jump:t $Ii", |
| tc_57a55b54, TypeCR>, Enc_0fa531 { |
| let Inst{0-0} = 0b0; |
| let Inst{12-12} = 0b1; |
| let Inst{31-22} = 0b0110000101; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Defs = [PC]; |
| let isTaken = Inst{12}; |
| } |
| def J2_jumprltez : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, b13_2Imm:$Ii), |
| "if ($Rs32<=#0) jump:nt $Ii", |
| tc_57a55b54, TypeCR>, Enc_0fa531 { |
| let Inst{0-0} = 0b0; |
| let Inst{12-12} = 0b0; |
| let Inst{31-22} = 0b0110000111; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Defs = [PC]; |
| let isTaken = Inst{12}; |
| } |
| def J2_jumprltezpt : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, b13_2Imm:$Ii), |
| "if ($Rs32<=#0) jump:t $Ii", |
| tc_57a55b54, TypeCR>, Enc_0fa531 { |
| let Inst{0-0} = 0b0; |
| let Inst{12-12} = 0b1; |
| let Inst{31-22} = 0b0110000111; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Defs = [PC]; |
| let isTaken = Inst{12}; |
| } |
| def J2_jumprnz : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, b13_2Imm:$Ii), |
| "if ($Rs32==#0) jump:nt $Ii", |
| tc_57a55b54, TypeCR>, Enc_0fa531 { |
| let Inst{0-0} = 0b0; |
| let Inst{12-12} = 0b0; |
| let Inst{31-22} = 0b0110000110; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Defs = [PC]; |
| let isTaken = Inst{12}; |
| } |
| def J2_jumprnzpt : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, b13_2Imm:$Ii), |
| "if ($Rs32==#0) jump:t $Ii", |
| tc_57a55b54, TypeCR>, Enc_0fa531 { |
| let Inst{0-0} = 0b0; |
| let Inst{12-12} = 0b1; |
| let Inst{31-22} = 0b0110000110; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Defs = [PC]; |
| let isTaken = Inst{12}; |
| } |
| def J2_jumprt : HInst< |
| (outs), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if ($Pu4) jumpr:nt $Rs32", |
| tc_2f573607, TypeJ>, Enc_88d4d9, PredNewRel { |
| let Inst{7-0} = 0b00000000; |
| let Inst{13-10} = 0b0000; |
| let Inst{31-21} = 0b01010011010; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isIndirectBranch = 1; |
| let isBranch = 1; |
| let cofMax1 = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J2_jumpr"; |
| let InputType = "reg"; |
| let isTaken = Inst{12}; |
| } |
| def J2_jumprt_nopred_map : HInst< |
| (outs), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if ($Pu4) jumpr $Rs32", |
| tc_2f573607, TypeMAPPING>, Requires<[HasV60]> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def J2_jumprtnew : HInst< |
| (outs), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if ($Pu4.new) jumpr:nt $Rs32", |
| tc_ed03645c, TypeJ>, Enc_88d4d9, PredNewRel { |
| let Inst{7-0} = 0b00000000; |
| let Inst{13-10} = 0b0010; |
| let Inst{31-21} = 0b01010011010; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isIndirectBranch = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofMax1 = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J2_jumpr"; |
| let InputType = "reg"; |
| let isTaken = Inst{12}; |
| } |
| def J2_jumprtnewpt : HInst< |
| (outs), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if ($Pu4.new) jumpr:t $Rs32", |
| tc_ed03645c, TypeJ>, Enc_88d4d9, PredNewRel { |
| let Inst{7-0} = 0b00000000; |
| let Inst{13-10} = 0b0110; |
| let Inst{31-21} = 0b01010011010; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isIndirectBranch = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofMax1 = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J2_jumpr"; |
| let InputType = "reg"; |
| let isTaken = Inst{12}; |
| } |
| def J2_jumprtpt : HInst< |
| (outs), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if ($Pu4) jumpr:t $Rs32", |
| tc_42ff66ba, TypeJ>, Enc_88d4d9, Requires<[HasV60]>, PredNewRel { |
| let Inst{7-0} = 0b00000000; |
| let Inst{13-10} = 0b0100; |
| let Inst{31-21} = 0b01010011010; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isIndirectBranch = 1; |
| let isBranch = 1; |
| let cofMax1 = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J2_jumpr"; |
| let InputType = "reg"; |
| let isTaken = Inst{12}; |
| } |
| def J2_jumprz : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, b13_2Imm:$Ii), |
| "if ($Rs32!=#0) jump:nt $Ii", |
| tc_57a55b54, TypeCR>, Enc_0fa531 { |
| let Inst{0-0} = 0b0; |
| let Inst{12-12} = 0b0; |
| let Inst{31-22} = 0b0110000100; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Defs = [PC]; |
| let isTaken = Inst{12}; |
| } |
| def J2_jumprzpt : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, b13_2Imm:$Ii), |
| "if ($Rs32!=#0) jump:t $Ii", |
| tc_57a55b54, TypeCR>, Enc_0fa531 { |
| let Inst{0-0} = 0b0; |
| let Inst{12-12} = 0b1; |
| let Inst{31-22} = 0b0110000100; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Defs = [PC]; |
| let isTaken = Inst{12}; |
| } |
| def J2_jumpt : HInst< |
| (outs), |
| (ins PredRegs:$Pu4, b30_2Imm:$Ii), |
| "if ($Pu4) jump:nt $Ii", |
| tc_56a124a7, TypeJ>, Enc_daea09, PredNewRel { |
| let Inst{0-0} = 0b0; |
| let Inst{12-10} = 0b000; |
| let Inst{21-21} = 0b0; |
| let Inst{31-24} = 0b01011100; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J2_jump"; |
| let InputType = "imm"; |
| let isTaken = Inst{12}; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 1; |
| let opExtentBits = 17; |
| let opExtentAlign = 2; |
| } |
| def J2_jumpt_nopred_map : HInst< |
| (outs), |
| (ins PredRegs:$Pu4, b15_2Imm:$Ii), |
| "if ($Pu4) jump $Ii", |
| tc_56a124a7, TypeMAPPING>, Requires<[HasV60]> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def J2_jumptnew : HInst< |
| (outs), |
| (ins PredRegs:$Pu4, b30_2Imm:$Ii), |
| "if ($Pu4.new) jump:nt $Ii", |
| tc_eeda4109, TypeJ>, Enc_daea09, PredNewRel { |
| let Inst{0-0} = 0b0; |
| let Inst{12-10} = 0b010; |
| let Inst{21-21} = 0b0; |
| let Inst{31-24} = 0b01011100; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J2_jump"; |
| let InputType = "imm"; |
| let isTaken = Inst{12}; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 1; |
| let opExtentBits = 17; |
| let opExtentAlign = 2; |
| } |
| def J2_jumptnewpt : HInst< |
| (outs), |
| (ins PredRegs:$Pu4, b30_2Imm:$Ii), |
| "if ($Pu4.new) jump:t $Ii", |
| tc_eeda4109, TypeJ>, Enc_daea09, PredNewRel { |
| let Inst{0-0} = 0b0; |
| let Inst{12-10} = 0b110; |
| let Inst{21-21} = 0b0; |
| let Inst{31-24} = 0b01011100; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J2_jump"; |
| let InputType = "imm"; |
| let isTaken = Inst{12}; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 1; |
| let opExtentBits = 17; |
| let opExtentAlign = 2; |
| } |
| def J2_jumptpt : HInst< |
| (outs), |
| (ins PredRegs:$Pu4, b30_2Imm:$Ii), |
| "if ($Pu4) jump:t $Ii", |
| tc_711c805f, TypeJ>, Enc_daea09, Requires<[HasV60]>, PredNewRel { |
| let Inst{0-0} = 0b0; |
| let Inst{12-10} = 0b100; |
| let Inst{21-21} = 0b0; |
| let Inst{31-24} = 0b01011100; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J2_jump"; |
| let InputType = "imm"; |
| let isTaken = Inst{12}; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 1; |
| let opExtentBits = 17; |
| let opExtentAlign = 2; |
| } |
| def J2_loop0i : HInst< |
| (outs), |
| (ins b30_2Imm:$Ii, u10_0Imm:$II), |
| "loop0($Ii,#$II)", |
| tc_1248597c, TypeCR>, Enc_4dc228 { |
| let Inst{2-2} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b01101001000; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let Defs = [LC0, SA0, USR]; |
| let isExtendable = 1; |
| let opExtendable = 0; |
| let isExtentSigned = 1; |
| let opExtentBits = 9; |
| let opExtentAlign = 2; |
| } |
| def J2_loop0r : HInst< |
| (outs), |
| (ins b30_2Imm:$Ii, IntRegs:$Rs32), |
| "loop0($Ii,$Rs32)", |
| tc_9406230a, TypeCR>, Enc_864a5a { |
| let Inst{2-0} = 0b000; |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b01100000000; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let Defs = [LC0, SA0, USR]; |
| let isExtendable = 1; |
| let opExtendable = 0; |
| let isExtentSigned = 1; |
| let opExtentBits = 9; |
| let opExtentAlign = 2; |
| } |
| def J2_loop1i : HInst< |
| (outs), |
| (ins b30_2Imm:$Ii, u10_0Imm:$II), |
| "loop1($Ii,#$II)", |
| tc_1248597c, TypeCR>, Enc_4dc228 { |
| let Inst{2-2} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b01101001001; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let Defs = [LC1, SA1]; |
| let isExtendable = 1; |
| let opExtendable = 0; |
| let isExtentSigned = 1; |
| let opExtentBits = 9; |
| let opExtentAlign = 2; |
| } |
| def J2_loop1r : HInst< |
| (outs), |
| (ins b30_2Imm:$Ii, IntRegs:$Rs32), |
| "loop1($Ii,$Rs32)", |
| tc_9406230a, TypeCR>, Enc_864a5a { |
| let Inst{2-0} = 0b000; |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b01100000001; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let Defs = [LC1, SA1]; |
| let isExtendable = 1; |
| let opExtendable = 0; |
| let isExtentSigned = 1; |
| let opExtentBits = 9; |
| let opExtentAlign = 2; |
| } |
| def J2_pause : HInst< |
| (outs), |
| (ins u8_0Imm:$Ii), |
| "pause(#$Ii)", |
| tc_d57d649c, TypeJ>, Enc_a51a9a { |
| let Inst{1-0} = 0b00; |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-16} = 0b0101010001000000; |
| let isSolo = 1; |
| } |
| def J2_ploop1si : HInst< |
| (outs), |
| (ins b30_2Imm:$Ii, u10_0Imm:$II), |
| "p3 = sp1loop0($Ii,#$II)", |
| tc_4abdbdc6, TypeCR>, Enc_4dc228 { |
| let Inst{2-2} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b01101001101; |
| let isPredicateLate = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let Defs = [LC0, P3, SA0, USR]; |
| let isExtendable = 1; |
| let opExtendable = 0; |
| let isExtentSigned = 1; |
| let opExtentBits = 9; |
| let opExtentAlign = 2; |
| } |
| def J2_ploop1sr : HInst< |
| (outs), |
| (ins b30_2Imm:$Ii, IntRegs:$Rs32), |
| "p3 = sp1loop0($Ii,$Rs32)", |
| tc_6d861a95, TypeCR>, Enc_864a5a { |
| let Inst{2-0} = 0b000; |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b01100000101; |
| let isPredicateLate = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let Defs = [LC0, P3, SA0, USR]; |
| let isExtendable = 1; |
| let opExtendable = 0; |
| let isExtentSigned = 1; |
| let opExtentBits = 9; |
| let opExtentAlign = 2; |
| } |
| def J2_ploop2si : HInst< |
| (outs), |
| (ins b30_2Imm:$Ii, u10_0Imm:$II), |
| "p3 = sp2loop0($Ii,#$II)", |
| tc_4abdbdc6, TypeCR>, Enc_4dc228 { |
| let Inst{2-2} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b01101001110; |
| let isPredicateLate = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let Defs = [LC0, P3, SA0, USR]; |
| let isExtendable = 1; |
| let opExtendable = 0; |
| let isExtentSigned = 1; |
| let opExtentBits = 9; |
| let opExtentAlign = 2; |
| } |
| def J2_ploop2sr : HInst< |
| (outs), |
| (ins b30_2Imm:$Ii, IntRegs:$Rs32), |
| "p3 = sp2loop0($Ii,$Rs32)", |
| tc_6d861a95, TypeCR>, Enc_864a5a { |
| let Inst{2-0} = 0b000; |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b01100000110; |
| let isPredicateLate = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let Defs = [LC0, P3, SA0, USR]; |
| let isExtendable = 1; |
| let opExtendable = 0; |
| let isExtentSigned = 1; |
| let opExtentBits = 9; |
| let opExtentAlign = 2; |
| } |
| def J2_ploop3si : HInst< |
| (outs), |
| (ins b30_2Imm:$Ii, u10_0Imm:$II), |
| "p3 = sp3loop0($Ii,#$II)", |
| tc_4abdbdc6, TypeCR>, Enc_4dc228 { |
| let Inst{2-2} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b01101001111; |
| let isPredicateLate = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let Defs = [LC0, P3, SA0, USR]; |
| let isExtendable = 1; |
| let opExtendable = 0; |
| let isExtentSigned = 1; |
| let opExtentBits = 9; |
| let opExtentAlign = 2; |
| } |
| def J2_ploop3sr : HInst< |
| (outs), |
| (ins b30_2Imm:$Ii, IntRegs:$Rs32), |
| "p3 = sp3loop0($Ii,$Rs32)", |
| tc_6d861a95, TypeCR>, Enc_864a5a { |
| let Inst{2-0} = 0b000; |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b01100000111; |
| let isPredicateLate = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let Defs = [LC0, P3, SA0, USR]; |
| let isExtendable = 1; |
| let opExtendable = 0; |
| let isExtentSigned = 1; |
| let opExtentBits = 9; |
| let opExtentAlign = 2; |
| } |
| def J2_trap0 : HInst< |
| (outs), |
| (ins u8_0Imm:$Ii), |
| "trap0(#$Ii)", |
| tc_45f9d1be, TypeJ>, Enc_a51a9a { |
| let Inst{1-0} = 0b00; |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-16} = 0b0101010000000000; |
| let isSolo = 1; |
| let hasSideEffects = 1; |
| } |
| def J2_trap1 : HInst< |
| (outs IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, u8_0Imm:$Ii), |
| "trap1($Rx32,#$Ii)", |
| tc_53c851ab, TypeJ>, Enc_33f8ba, Requires<[HasV65]> { |
| let Inst{1-0} = 0b00; |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b01010100100; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isSolo = 1; |
| let Uses = [GOSP]; |
| let Defs = [GOSP, PC]; |
| let hasSideEffects = 1; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def J2_trap1_noregmap : HInst< |
| (outs), |
| (ins u8_0Imm:$Ii), |
| "trap1(#$Ii)", |
| tc_53c851ab, TypeMAPPING>, Requires<[HasV65]> { |
| let hasSideEffects = 1; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def J4_cmpeq_f_jumpnv_nt : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), |
| "if (!cmp.eq($Ns8.new,$Rt32)) jump:nt $Ii", |
| tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010000001; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpeqr"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_cmpeq_f_jumpnv_t : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), |
| "if (!cmp.eq($Ns8.new,$Rt32)) jump:t $Ii", |
| tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010000001; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpeqr"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_cmpeq_fp0_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), |
| "p0 = cmp.eq($Rs16,$Rt16); if (!p0.new) jump:nt $Ii", |
| tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-12} = 0b00; |
| let Inst{31-22} = 0b0001010001; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let BaseOpcode = "J4_cmpeqp0"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpeq_fp0_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), |
| "p0 = cmp.eq($Rs16,$Rt16); if (!p0.new) jump:t $Ii", |
| tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-12} = 0b10; |
| let Inst{31-22} = 0b0001010001; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let BaseOpcode = "J4_cmpeqp0"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpeq_fp1_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), |
| "p1 = cmp.eq($Rs16,$Rt16); if (!p1.new) jump:nt $Ii", |
| tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-12} = 0b01; |
| let Inst{31-22} = 0b0001010001; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let BaseOpcode = "J4_cmpeqp1"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpeq_fp1_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), |
| "p1 = cmp.eq($Rs16,$Rt16); if (!p1.new) jump:t $Ii", |
| tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-12} = 0b11; |
| let Inst{31-22} = 0b0001010001; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let BaseOpcode = "J4_cmpeqp1"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpeq_t_jumpnv_nt : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), |
| "if (cmp.eq($Ns8.new,$Rt32)) jump:nt $Ii", |
| tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010000000; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpeqr"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_cmpeq_t_jumpnv_t : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), |
| "if (cmp.eq($Ns8.new,$Rt32)) jump:t $Ii", |
| tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010000000; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpeqr"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_cmpeq_tp0_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), |
| "p0 = cmp.eq($Rs16,$Rt16); if (p0.new) jump:nt $Ii", |
| tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-12} = 0b00; |
| let Inst{31-22} = 0b0001010000; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let BaseOpcode = "J4_cmpeqp0"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpeq_tp0_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), |
| "p0 = cmp.eq($Rs16,$Rt16); if (p0.new) jump:t $Ii", |
| tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-12} = 0b10; |
| let Inst{31-22} = 0b0001010000; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let BaseOpcode = "J4_cmpeqp0"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpeq_tp1_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), |
| "p1 = cmp.eq($Rs16,$Rt16); if (p1.new) jump:nt $Ii", |
| tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-12} = 0b01; |
| let Inst{31-22} = 0b0001010000; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let BaseOpcode = "J4_cmpeqp1"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpeq_tp1_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), |
| "p1 = cmp.eq($Rs16,$Rt16); if (p1.new) jump:t $Ii", |
| tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-12} = 0b11; |
| let Inst{31-22} = 0b0001010000; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let BaseOpcode = "J4_cmpeqp1"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpeqi_f_jumpnv_nt : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), |
| "if (!cmp.eq($Ns8.new,#$II)) jump:nt $Ii", |
| tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010010001; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpeqi"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_cmpeqi_f_jumpnv_t : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), |
| "if (!cmp.eq($Ns8.new,#$II)) jump:t $Ii", |
| tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010010001; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpeqi"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_cmpeqi_fp0_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), |
| "p0 = cmp.eq($Rs16,#$II); if (!p0.new) jump:nt $Ii", |
| tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{31-22} = 0b0001000001; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let BaseOpcode = "J4_cmpeqip0"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpeqi_fp0_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), |
| "p0 = cmp.eq($Rs16,#$II); if (!p0.new) jump:t $Ii", |
| tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{31-22} = 0b0001000001; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let BaseOpcode = "J4_cmpeqip0"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpeqi_fp1_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), |
| "p1 = cmp.eq($Rs16,#$II); if (!p1.new) jump:nt $Ii", |
| tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{31-22} = 0b0001001001; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let BaseOpcode = "J4_cmpeqip1"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpeqi_fp1_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), |
| "p1 = cmp.eq($Rs16,#$II); if (!p1.new) jump:t $Ii", |
| tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{31-22} = 0b0001001001; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let BaseOpcode = "J4_cmpeqip1"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpeqi_t_jumpnv_nt : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), |
| "if (cmp.eq($Ns8.new,#$II)) jump:nt $Ii", |
| tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010010000; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpeqi"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_cmpeqi_t_jumpnv_t : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), |
| "if (cmp.eq($Ns8.new,#$II)) jump:t $Ii", |
| tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010010000; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpeqi"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_cmpeqi_tp0_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), |
| "p0 = cmp.eq($Rs16,#$II); if (p0.new) jump:nt $Ii", |
| tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{31-22} = 0b0001000000; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let BaseOpcode = "J4_cmpeqip0"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpeqi_tp0_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), |
| "p0 = cmp.eq($Rs16,#$II); if (p0.new) jump:t $Ii", |
| tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{31-22} = 0b0001000000; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let BaseOpcode = "J4_cmpeqip0"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpeqi_tp1_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), |
| "p1 = cmp.eq($Rs16,#$II); if (p1.new) jump:nt $Ii", |
| tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{31-22} = 0b0001001000; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let BaseOpcode = "J4_cmpeqip1"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpeqi_tp1_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), |
| "p1 = cmp.eq($Rs16,#$II); if (p1.new) jump:t $Ii", |
| tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{31-22} = 0b0001001000; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let BaseOpcode = "J4_cmpeqip1"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpeqn1_f_jumpnv_nt : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), |
| "if (!cmp.eq($Ns8.new,#$n1)) jump:nt $Ii", |
| tc_f6e2aff9, TypeNCJ>, Enc_e90a15, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b000000; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010011001; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpeqn1r"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_cmpeqn1_f_jumpnv_t : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), |
| "if (!cmp.eq($Ns8.new,#$n1)) jump:t $Ii", |
| tc_f6e2aff9, TypeNCJ>, Enc_5a18b3, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b100000; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010011001; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpeqn1r"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_cmpeqn1_fp0_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), |
| "p0 = cmp.eq($Rs16,#$n1); if (!p0.new) jump:nt $Ii", |
| tc_24f426ab, TypeCJ>, Enc_1de724, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b000000; |
| let Inst{31-22} = 0b0001000111; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let BaseOpcode = "J4_cmpeqn1p0"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpeqn1_fp0_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), |
| "p0 = cmp.eq($Rs16,#$n1); if (!p0.new) jump:t $Ii", |
| tc_24f426ab, TypeCJ>, Enc_14640c, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b100000; |
| let Inst{31-22} = 0b0001000111; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let BaseOpcode = "J4_cmpeqn1p0"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpeqn1_fp1_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), |
| "p1 = cmp.eq($Rs16,#$n1); if (!p1.new) jump:nt $Ii", |
| tc_24f426ab, TypeCJ>, Enc_668704, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b000000; |
| let Inst{31-22} = 0b0001001111; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let BaseOpcode = "J4_cmpeqn1p1"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpeqn1_fp1_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), |
| "p1 = cmp.eq($Rs16,#$n1); if (!p1.new) jump:t $Ii", |
| tc_24f426ab, TypeCJ>, Enc_800e04, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b100000; |
| let Inst{31-22} = 0b0001001111; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let BaseOpcode = "J4_cmpeqn1p1"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpeqn1_t_jumpnv_nt : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), |
| "if (cmp.eq($Ns8.new,#$n1)) jump:nt $Ii", |
| tc_f6e2aff9, TypeNCJ>, Enc_4aca3a, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b000000; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010011000; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpeqn1r"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_cmpeqn1_t_jumpnv_t : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), |
| "if (cmp.eq($Ns8.new,#$n1)) jump:t $Ii", |
| tc_f6e2aff9, TypeNCJ>, Enc_f7ea77, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b100000; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010011000; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpeqn1r"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_cmpeqn1_tp0_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), |
| "p0 = cmp.eq($Rs16,#$n1); if (p0.new) jump:nt $Ii", |
| tc_24f426ab, TypeCJ>, Enc_405228, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b000000; |
| let Inst{31-22} = 0b0001000110; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let BaseOpcode = "J4_cmpeqn1p0"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpeqn1_tp0_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), |
| "p0 = cmp.eq($Rs16,#$n1); if (p0.new) jump:t $Ii", |
| tc_24f426ab, TypeCJ>, Enc_3a2484, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b100000; |
| let Inst{31-22} = 0b0001000110; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let BaseOpcode = "J4_cmpeqn1p0"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpeqn1_tp1_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), |
| "p1 = cmp.eq($Rs16,#$n1); if (p1.new) jump:nt $Ii", |
| tc_24f426ab, TypeCJ>, Enc_736575, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b000000; |
| let Inst{31-22} = 0b0001001110; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let BaseOpcode = "J4_cmpeqn1p1"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpeqn1_tp1_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), |
| "p1 = cmp.eq($Rs16,#$n1); if (p1.new) jump:t $Ii", |
| tc_24f426ab, TypeCJ>, Enc_8e583a, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b100000; |
| let Inst{31-22} = 0b0001001110; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let BaseOpcode = "J4_cmpeqn1p1"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgt_f_jumpnv_nt : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), |
| "if (!cmp.gt($Ns8.new,$Rt32)) jump:nt $Ii", |
| tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010000011; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpgtr"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_cmpgt_f_jumpnv_t : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), |
| "if (!cmp.gt($Ns8.new,$Rt32)) jump:t $Ii", |
| tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010000011; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpgtr"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_cmpgt_fp0_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), |
| "p0 = cmp.gt($Rs16,$Rt16); if (!p0.new) jump:nt $Ii", |
| tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-12} = 0b00; |
| let Inst{31-22} = 0b0001010011; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let BaseOpcode = "J4_cmpgtp0"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgt_fp0_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), |
| "p0 = cmp.gt($Rs16,$Rt16); if (!p0.new) jump:t $Ii", |
| tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-12} = 0b10; |
| let Inst{31-22} = 0b0001010011; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let BaseOpcode = "J4_cmpgtp0"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgt_fp1_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), |
| "p1 = cmp.gt($Rs16,$Rt16); if (!p1.new) jump:nt $Ii", |
| tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-12} = 0b01; |
| let Inst{31-22} = 0b0001010011; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let BaseOpcode = "J4_cmpgtp1"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgt_fp1_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), |
| "p1 = cmp.gt($Rs16,$Rt16); if (!p1.new) jump:t $Ii", |
| tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-12} = 0b11; |
| let Inst{31-22} = 0b0001010011; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let BaseOpcode = "J4_cmpgtp1"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgt_t_jumpnv_nt : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), |
| "if (cmp.gt($Ns8.new,$Rt32)) jump:nt $Ii", |
| tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010000010; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpgtr"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_cmpgt_t_jumpnv_t : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), |
| "if (cmp.gt($Ns8.new,$Rt32)) jump:t $Ii", |
| tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010000010; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpgtr"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_cmpgt_tp0_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), |
| "p0 = cmp.gt($Rs16,$Rt16); if (p0.new) jump:nt $Ii", |
| tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-12} = 0b00; |
| let Inst{31-22} = 0b0001010010; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let BaseOpcode = "J4_cmpgtp0"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgt_tp0_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), |
| "p0 = cmp.gt($Rs16,$Rt16); if (p0.new) jump:t $Ii", |
| tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-12} = 0b10; |
| let Inst{31-22} = 0b0001010010; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let BaseOpcode = "J4_cmpgtp0"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgt_tp1_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), |
| "p1 = cmp.gt($Rs16,$Rt16); if (p1.new) jump:nt $Ii", |
| tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-12} = 0b01; |
| let Inst{31-22} = 0b0001010010; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let BaseOpcode = "J4_cmpgtp1"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgt_tp1_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), |
| "p1 = cmp.gt($Rs16,$Rt16); if (p1.new) jump:t $Ii", |
| tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-12} = 0b11; |
| let Inst{31-22} = 0b0001010010; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let BaseOpcode = "J4_cmpgtp1"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgti_f_jumpnv_nt : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), |
| "if (!cmp.gt($Ns8.new,#$II)) jump:nt $Ii", |
| tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010010011; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpgtir"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_cmpgti_f_jumpnv_t : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), |
| "if (!cmp.gt($Ns8.new,#$II)) jump:t $Ii", |
| tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010010011; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpgtir"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_cmpgti_fp0_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), |
| "p0 = cmp.gt($Rs16,#$II); if (!p0.new) jump:nt $Ii", |
| tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{31-22} = 0b0001000011; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let BaseOpcode = "J4_cmpgtip0"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgti_fp0_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), |
| "p0 = cmp.gt($Rs16,#$II); if (!p0.new) jump:t $Ii", |
| tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{31-22} = 0b0001000011; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let BaseOpcode = "J4_cmpgtip0"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgti_fp1_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), |
| "p1 = cmp.gt($Rs16,#$II); if (!p1.new) jump:nt $Ii", |
| tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{31-22} = 0b0001001011; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let BaseOpcode = "J4_cmpgtip1"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgti_fp1_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), |
| "p1 = cmp.gt($Rs16,#$II); if (!p1.new) jump:t $Ii", |
| tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{31-22} = 0b0001001011; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let BaseOpcode = "J4_cmpgtip1"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgti_t_jumpnv_nt : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), |
| "if (cmp.gt($Ns8.new,#$II)) jump:nt $Ii", |
| tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010010010; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpgtir"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_cmpgti_t_jumpnv_t : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), |
| "if (cmp.gt($Ns8.new,#$II)) jump:t $Ii", |
| tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010010010; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpgtir"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_cmpgti_tp0_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), |
| "p0 = cmp.gt($Rs16,#$II); if (p0.new) jump:nt $Ii", |
| tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{31-22} = 0b0001000010; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let BaseOpcode = "J4_cmpgtip0"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgti_tp0_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), |
| "p0 = cmp.gt($Rs16,#$II); if (p0.new) jump:t $Ii", |
| tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{31-22} = 0b0001000010; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let BaseOpcode = "J4_cmpgtip0"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgti_tp1_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), |
| "p1 = cmp.gt($Rs16,#$II); if (p1.new) jump:nt $Ii", |
| tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{31-22} = 0b0001001010; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let BaseOpcode = "J4_cmpgtip1"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgti_tp1_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), |
| "p1 = cmp.gt($Rs16,#$II); if (p1.new) jump:t $Ii", |
| tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{31-22} = 0b0001001010; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let BaseOpcode = "J4_cmpgtip1"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgtn1_f_jumpnv_nt : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), |
| "if (!cmp.gt($Ns8.new,#$n1)) jump:nt $Ii", |
| tc_f6e2aff9, TypeNCJ>, Enc_3694bd, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b000000; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010011011; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpgtn1r"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_cmpgtn1_f_jumpnv_t : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), |
| "if (!cmp.gt($Ns8.new,#$n1)) jump:t $Ii", |
| tc_f6e2aff9, TypeNCJ>, Enc_a6853f, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b100000; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010011011; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpgtn1r"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_cmpgtn1_fp0_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), |
| "p0 = cmp.gt($Rs16,#$n1); if (!p0.new) jump:nt $Ii", |
| tc_24f426ab, TypeCJ>, Enc_a42857, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b000001; |
| let Inst{31-22} = 0b0001000111; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let BaseOpcode = "J4_cmpgtn1p0"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgtn1_fp0_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), |
| "p0 = cmp.gt($Rs16,#$n1); if (!p0.new) jump:t $Ii", |
| tc_24f426ab, TypeCJ>, Enc_f6fe0b, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b100001; |
| let Inst{31-22} = 0b0001000111; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let BaseOpcode = "J4_cmpgtn1p0"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgtn1_fp1_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), |
| "p1 = cmp.gt($Rs16,#$n1); if (!p1.new) jump:nt $Ii", |
| tc_24f426ab, TypeCJ>, Enc_3e3989, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b000001; |
| let Inst{31-22} = 0b0001001111; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let BaseOpcode = "J4_cmpgtn1p1"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgtn1_fp1_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), |
| "p1 = cmp.gt($Rs16,#$n1); if (!p1.new) jump:t $Ii", |
| tc_24f426ab, TypeCJ>, Enc_b909d2, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b100001; |
| let Inst{31-22} = 0b0001001111; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let BaseOpcode = "J4_cmpgtn1p1"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgtn1_t_jumpnv_nt : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), |
| "if (cmp.gt($Ns8.new,#$n1)) jump:nt $Ii", |
| tc_f6e2aff9, TypeNCJ>, Enc_f82302, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b000000; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010011010; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpgtn1r"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_cmpgtn1_t_jumpnv_t : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), |
| "if (cmp.gt($Ns8.new,#$n1)) jump:t $Ii", |
| tc_f6e2aff9, TypeNCJ>, Enc_6413b6, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b100000; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010011010; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpgtn1r"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_cmpgtn1_tp0_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), |
| "p0 = cmp.gt($Rs16,#$n1); if (p0.new) jump:nt $Ii", |
| tc_24f426ab, TypeCJ>, Enc_b78edd, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b000001; |
| let Inst{31-22} = 0b0001000110; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let BaseOpcode = "J4_cmpgtn1p0"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgtn1_tp0_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), |
| "p0 = cmp.gt($Rs16,#$n1); if (p0.new) jump:t $Ii", |
| tc_24f426ab, TypeCJ>, Enc_041d7b, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b100001; |
| let Inst{31-22} = 0b0001000110; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let BaseOpcode = "J4_cmpgtn1p0"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgtn1_tp1_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), |
| "p1 = cmp.gt($Rs16,#$n1); if (p1.new) jump:nt $Ii", |
| tc_24f426ab, TypeCJ>, Enc_b1e1fb, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b000001; |
| let Inst{31-22} = 0b0001001110; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let BaseOpcode = "J4_cmpgtn1p1"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgtn1_tp1_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), |
| "p1 = cmp.gt($Rs16,#$n1); if (p1.new) jump:t $Ii", |
| tc_24f426ab, TypeCJ>, Enc_178717, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b100001; |
| let Inst{31-22} = 0b0001001110; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let BaseOpcode = "J4_cmpgtn1p1"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgtu_f_jumpnv_nt : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), |
| "if (!cmp.gtu($Ns8.new,$Rt32)) jump:nt $Ii", |
| tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010000101; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpgtur"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_cmpgtu_f_jumpnv_t : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), |
| "if (!cmp.gtu($Ns8.new,$Rt32)) jump:t $Ii", |
| tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010000101; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpgtur"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_cmpgtu_fp0_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), |
| "p0 = cmp.gtu($Rs16,$Rt16); if (!p0.new) jump:nt $Ii", |
| tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-12} = 0b00; |
| let Inst{31-22} = 0b0001010101; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let BaseOpcode = "J4_cmpgtup0"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgtu_fp0_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), |
| "p0 = cmp.gtu($Rs16,$Rt16); if (!p0.new) jump:t $Ii", |
| tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-12} = 0b10; |
| let Inst{31-22} = 0b0001010101; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let BaseOpcode = "J4_cmpgtup0"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgtu_fp1_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), |
| "p1 = cmp.gtu($Rs16,$Rt16); if (!p1.new) jump:nt $Ii", |
| tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-12} = 0b01; |
| let Inst{31-22} = 0b0001010101; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let BaseOpcode = "J4_cmpgtup1"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgtu_fp1_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), |
| "p1 = cmp.gtu($Rs16,$Rt16); if (!p1.new) jump:t $Ii", |
| tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-12} = 0b11; |
| let Inst{31-22} = 0b0001010101; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let BaseOpcode = "J4_cmpgtup1"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgtu_t_jumpnv_nt : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), |
| "if (cmp.gtu($Ns8.new,$Rt32)) jump:nt $Ii", |
| tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010000100; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpgtur"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_cmpgtu_t_jumpnv_t : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), |
| "if (cmp.gtu($Ns8.new,$Rt32)) jump:t $Ii", |
| tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010000100; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpgtur"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_cmpgtu_tp0_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), |
| "p0 = cmp.gtu($Rs16,$Rt16); if (p0.new) jump:nt $Ii", |
| tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-12} = 0b00; |
| let Inst{31-22} = 0b0001010100; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let BaseOpcode = "J4_cmpgtup0"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgtu_tp0_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), |
| "p0 = cmp.gtu($Rs16,$Rt16); if (p0.new) jump:t $Ii", |
| tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-12} = 0b10; |
| let Inst{31-22} = 0b0001010100; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let BaseOpcode = "J4_cmpgtup0"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgtu_tp1_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), |
| "p1 = cmp.gtu($Rs16,$Rt16); if (p1.new) jump:nt $Ii", |
| tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-12} = 0b01; |
| let Inst{31-22} = 0b0001010100; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let BaseOpcode = "J4_cmpgtup1"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgtu_tp1_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), |
| "p1 = cmp.gtu($Rs16,$Rt16); if (p1.new) jump:t $Ii", |
| tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-12} = 0b11; |
| let Inst{31-22} = 0b0001010100; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let BaseOpcode = "J4_cmpgtup1"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgtui_f_jumpnv_nt : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), |
| "if (!cmp.gtu($Ns8.new,#$II)) jump:nt $Ii", |
| tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010010101; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpgtuir"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_cmpgtui_f_jumpnv_t : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), |
| "if (!cmp.gtu($Ns8.new,#$II)) jump:t $Ii", |
| tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010010101; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpgtuir"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_cmpgtui_fp0_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), |
| "p0 = cmp.gtu($Rs16,#$II); if (!p0.new) jump:nt $Ii", |
| tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{31-22} = 0b0001000101; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let BaseOpcode = "J4_cmpgtuip0"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgtui_fp0_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), |
| "p0 = cmp.gtu($Rs16,#$II); if (!p0.new) jump:t $Ii", |
| tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{31-22} = 0b0001000101; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let BaseOpcode = "J4_cmpgtuip0"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgtui_fp1_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), |
| "p1 = cmp.gtu($Rs16,#$II); if (!p1.new) jump:nt $Ii", |
| tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{31-22} = 0b0001001101; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let BaseOpcode = "J4_cmpgtuip1"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgtui_fp1_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), |
| "p1 = cmp.gtu($Rs16,#$II); if (!p1.new) jump:t $Ii", |
| tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{31-22} = 0b0001001101; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let BaseOpcode = "J4_cmpgtuip1"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgtui_t_jumpnv_nt : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), |
| "if (cmp.gtu($Ns8.new,#$II)) jump:nt $Ii", |
| tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010010100; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpgtuir"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_cmpgtui_t_jumpnv_t : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), |
| "if (cmp.gtu($Ns8.new,#$II)) jump:t $Ii", |
| tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010010100; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpgtuir"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_cmpgtui_tp0_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), |
| "p0 = cmp.gtu($Rs16,#$II); if (p0.new) jump:nt $Ii", |
| tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{31-22} = 0b0001000100; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let BaseOpcode = "J4_cmpgtuip0"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgtui_tp0_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), |
| "p0 = cmp.gtu($Rs16,#$II); if (p0.new) jump:t $Ii", |
| tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{31-22} = 0b0001000100; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let BaseOpcode = "J4_cmpgtuip0"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgtui_tp1_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), |
| "p1 = cmp.gtu($Rs16,#$II); if (p1.new) jump:nt $Ii", |
| tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{31-22} = 0b0001001100; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let BaseOpcode = "J4_cmpgtuip1"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmpgtui_tp1_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), |
| "p1 = cmp.gtu($Rs16,#$II); if (p1.new) jump:t $Ii", |
| tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{31-22} = 0b0001001100; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let BaseOpcode = "J4_cmpgtuip1"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_cmplt_f_jumpnv_nt : HInst< |
| (outs), |
| (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), |
| "if (!cmp.gt($Rt32,$Ns8.new)) jump:nt $Ii", |
| tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010000111; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpltr"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 1; |
| } |
| def J4_cmplt_f_jumpnv_t : HInst< |
| (outs), |
| (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), |
| "if (!cmp.gt($Rt32,$Ns8.new)) jump:t $Ii", |
| tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010000111; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpltr"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 1; |
| } |
| def J4_cmplt_t_jumpnv_nt : HInst< |
| (outs), |
| (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), |
| "if (cmp.gt($Rt32,$Ns8.new)) jump:nt $Ii", |
| tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010000110; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpltr"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 1; |
| } |
| def J4_cmplt_t_jumpnv_t : HInst< |
| (outs), |
| (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), |
| "if (cmp.gt($Rt32,$Ns8.new)) jump:t $Ii", |
| tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010000110; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpltr"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 1; |
| } |
| def J4_cmpltu_f_jumpnv_nt : HInst< |
| (outs), |
| (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), |
| "if (!cmp.gtu($Rt32,$Ns8.new)) jump:nt $Ii", |
| tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010001001; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpltur"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 1; |
| } |
| def J4_cmpltu_f_jumpnv_t : HInst< |
| (outs), |
| (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), |
| "if (!cmp.gtu($Rt32,$Ns8.new)) jump:t $Ii", |
| tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010001001; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpltur"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 1; |
| } |
| def J4_cmpltu_t_jumpnv_nt : HInst< |
| (outs), |
| (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), |
| "if (cmp.gtu($Rt32,$Ns8.new)) jump:nt $Ii", |
| tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010001000; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpltur"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 1; |
| } |
| def J4_cmpltu_t_jumpnv_t : HInst< |
| (outs), |
| (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), |
| "if (cmp.gtu($Rt32,$Ns8.new)) jump:t $Ii", |
| tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel { |
| let Inst{0-0} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010001000; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let BaseOpcode = "J4_cmpltur"; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 1; |
| } |
| def J4_hintjumpr : HInst< |
| (outs), |
| (ins IntRegs:$Rs32), |
| "hintjr($Rs32)", |
| tc_60e324ff, TypeJ>, Enc_ecbcc8 { |
| let Inst{13-0} = 0b00000000000000; |
| let Inst{31-21} = 0b01010010101; |
| let isTerminator = 1; |
| let isIndirectBranch = 1; |
| let isBranch = 1; |
| let cofMax1 = 1; |
| } |
| def J4_jumpseti : HInst< |
| (outs GeneralSubRegs:$Rd16), |
| (ins u6_0Imm:$II, b30_2Imm:$Ii), |
| "$Rd16 = #$II ; jump $Ii", |
| tc_5502c366, TypeCJ>, Enc_9e4c3f { |
| let Inst{0-0} = 0b0; |
| let Inst{31-22} = 0b0001011000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Defs = [PC]; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_jumpsetr : HInst< |
| (outs GeneralSubRegs:$Rd16), |
| (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), |
| "$Rd16 = $Rs16 ; jump $Ii", |
| tc_5502c366, TypeCJ>, Enc_66bce1 { |
| let Inst{0-0} = 0b0; |
| let Inst{13-12} = 0b00; |
| let Inst{31-22} = 0b0001011100; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Defs = [PC]; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_tstbit0_f_jumpnv_nt : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, b30_2Imm:$Ii), |
| "if (!tstbit($Ns8.new,#0)) jump:nt $Ii", |
| tc_7b9187d3, TypeNCJ>, Enc_69d63b { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b000000; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010010111; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_tstbit0_f_jumpnv_t : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, b30_2Imm:$Ii), |
| "if (!tstbit($Ns8.new,#0)) jump:t $Ii", |
| tc_7b9187d3, TypeNCJ>, Enc_69d63b { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b100000; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010010111; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_tstbit0_fp0_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), |
| "p0 = tstbit($Rs16,#0); if (!p0.new) jump:nt $Ii", |
| tc_f999c66e, TypeCJ>, Enc_ad1c74 { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b000011; |
| let Inst{31-22} = 0b0001000111; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_tstbit0_fp0_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), |
| "p0 = tstbit($Rs16,#0); if (!p0.new) jump:t $Ii", |
| tc_f999c66e, TypeCJ>, Enc_ad1c74 { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b100011; |
| let Inst{31-22} = 0b0001000111; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_tstbit0_fp1_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), |
| "p1 = tstbit($Rs16,#0); if (!p1.new) jump:nt $Ii", |
| tc_f999c66e, TypeCJ>, Enc_ad1c74 { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b000011; |
| let Inst{31-22} = 0b0001001111; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_tstbit0_fp1_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), |
| "p1 = tstbit($Rs16,#0); if (!p1.new) jump:t $Ii", |
| tc_f999c66e, TypeCJ>, Enc_ad1c74 { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b100011; |
| let Inst{31-22} = 0b0001001111; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_tstbit0_t_jumpnv_nt : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, b30_2Imm:$Ii), |
| "if (tstbit($Ns8.new,#0)) jump:nt $Ii", |
| tc_7b9187d3, TypeNCJ>, Enc_69d63b { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b000000; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010010110; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_tstbit0_t_jumpnv_t : HInst< |
| (outs), |
| (ins IntRegs:$Ns8, b30_2Imm:$Ii), |
| "if (tstbit($Ns8.new,#0)) jump:t $Ii", |
| tc_7b9187d3, TypeNCJ>, Enc_69d63b { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b100000; |
| let Inst{19-19} = 0b0; |
| let Inst{31-22} = 0b0010010110; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isNewValue = 1; |
| let cofMax1 = 1; |
| let isRestrictNoSlot1Store = 1; |
| let Defs = [PC]; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| let opNewValue = 0; |
| } |
| def J4_tstbit0_tp0_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), |
| "p0 = tstbit($Rs16,#0); if (p0.new) jump:nt $Ii", |
| tc_f999c66e, TypeCJ>, Enc_ad1c74 { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b000011; |
| let Inst{31-22} = 0b0001000110; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_tstbit0_tp0_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), |
| "p0 = tstbit($Rs16,#0); if (p0.new) jump:t $Ii", |
| tc_f999c66e, TypeCJ>, Enc_ad1c74 { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b100011; |
| let Inst{31-22} = 0b0001000110; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P0]; |
| let Defs = [P0, PC]; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_tstbit0_tp1_jump_nt : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), |
| "p1 = tstbit($Rs16,#0); if (p1.new) jump:nt $Ii", |
| tc_f999c66e, TypeCJ>, Enc_ad1c74 { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b000011; |
| let Inst{31-22} = 0b0001001110; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def J4_tstbit0_tp1_jump_t : HInst< |
| (outs), |
| (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), |
| "p1 = tstbit($Rs16,#0); if (p1.new) jump:t $Ii", |
| tc_f999c66e, TypeCJ>, Enc_ad1c74 { |
| let Inst{0-0} = 0b0; |
| let Inst{13-8} = 0b100011; |
| let Inst{31-22} = 0b0001001110; |
| let isPredicated = 1; |
| let isTerminator = 1; |
| let isBranch = 1; |
| let isPredicatedNew = 1; |
| let cofRelax1 = 1; |
| let cofRelax2 = 1; |
| let cofMax1 = 1; |
| let Uses = [P1]; |
| let Defs = [P1, PC]; |
| let isTaken = Inst{13}; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 2; |
| } |
| def L2_deallocframe : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins IntRegs:$Rs32), |
| "$Rdd32 = deallocframe($Rs32):raw", |
| tc_e9170fb7, TypeLD>, Enc_3a3d62 { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-21} = 0b10010000000; |
| let accessSize = DoubleWordAccess; |
| let mayLoad = 1; |
| let Uses = [FRAMEKEY]; |
| let Defs = [R29]; |
| } |
| def L2_loadalignb_io : HInst< |
| (outs DoubleRegs:$Ryy32), |
| (ins DoubleRegs:$Ryy32in, IntRegs:$Rs32, s32_0Imm:$Ii), |
| "$Ryy32 = memb_fifo($Rs32+#$Ii)", |
| tc_fedb7e19, TypeLD>, Enc_a27588 { |
| let Inst{24-21} = 0b0100; |
| let Inst{31-27} = 0b10010; |
| let addrMode = BaseImmOffset; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 0; |
| let Constraints = "$Ryy32 = $Ryy32in"; |
| } |
| def L2_loadalignb_pbr : HInst< |
| (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), |
| (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Ryy32 = memb_fifo($Rx32++$Mu2:brev)", |
| tc_1c7522a8, TypeLD>, Enc_1f5d8f { |
| let Inst{12-5} = 0b00000000; |
| let Inst{31-21} = 0b10011110100; |
| let addrMode = PostInc; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; |
| } |
| def L2_loadalignb_pci : HInst< |
| (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), |
| (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2), |
| "$Ryy32 = memb_fifo($Rx32++#$Ii:circ($Mu2))", |
| tc_76bb5435, TypeLD>, Enc_74aef2 { |
| let Inst{12-9} = 0b0000; |
| let Inst{31-21} = 0b10011000100; |
| let addrMode = PostInc; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let Uses = [CS]; |
| let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; |
| } |
| def L2_loadalignb_pcr : HInst< |
| (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), |
| (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Ryy32 = memb_fifo($Rx32++I:circ($Mu2))", |
| tc_1c7522a8, TypeLD>, Enc_1f5d8f { |
| let Inst{12-5} = 0b00010000; |
| let Inst{31-21} = 0b10011000100; |
| let addrMode = PostInc; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let Uses = [CS]; |
| let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; |
| } |
| def L2_loadalignb_pi : HInst< |
| (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), |
| (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_0Imm:$Ii), |
| "$Ryy32 = memb_fifo($Rx32++#$Ii)", |
| tc_1c7522a8, TypeLD>, Enc_6b197f { |
| let Inst{13-9} = 0b00000; |
| let Inst{31-21} = 0b10011010100; |
| let addrMode = PostInc; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; |
| } |
| def L2_loadalignb_pr : HInst< |
| (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), |
| (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Ryy32 = memb_fifo($Rx32++$Mu2)", |
| tc_1c7522a8, TypeLD>, Enc_1f5d8f { |
| let Inst{12-5} = 0b00000000; |
| let Inst{31-21} = 0b10011100100; |
| let addrMode = PostInc; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; |
| } |
| def L2_loadalignb_zomap : HInst< |
| (outs DoubleRegs:$Ryy32), |
| (ins DoubleRegs:$Ryy32in, IntRegs:$Rs32), |
| "$Ryy32 = memb_fifo($Rs32)", |
| tc_fedb7e19, TypeMAPPING> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| let Constraints = "$Ryy32 = $Ryy32in"; |
| } |
| def L2_loadalignh_io : HInst< |
| (outs DoubleRegs:$Ryy32), |
| (ins DoubleRegs:$Ryy32in, IntRegs:$Rs32, s31_1Imm:$Ii), |
| "$Ryy32 = memh_fifo($Rs32+#$Ii)", |
| tc_fedb7e19, TypeLD>, Enc_5cd7e9 { |
| let Inst{24-21} = 0b0010; |
| let Inst{31-27} = 0b10010; |
| let addrMode = BaseImmOffset; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 1; |
| let opExtentBits = 12; |
| let opExtentAlign = 1; |
| let Constraints = "$Ryy32 = $Ryy32in"; |
| } |
| def L2_loadalignh_pbr : HInst< |
| (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), |
| (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Ryy32 = memh_fifo($Rx32++$Mu2:brev)", |
| tc_1c7522a8, TypeLD>, Enc_1f5d8f { |
| let Inst{12-5} = 0b00000000; |
| let Inst{31-21} = 0b10011110010; |
| let addrMode = PostInc; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; |
| } |
| def L2_loadalignh_pci : HInst< |
| (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), |
| (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2), |
| "$Ryy32 = memh_fifo($Rx32++#$Ii:circ($Mu2))", |
| tc_76bb5435, TypeLD>, Enc_9e2e1c { |
| let Inst{12-9} = 0b0000; |
| let Inst{31-21} = 0b10011000010; |
| let addrMode = PostInc; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let Uses = [CS]; |
| let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; |
| } |
| def L2_loadalignh_pcr : HInst< |
| (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), |
| (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Ryy32 = memh_fifo($Rx32++I:circ($Mu2))", |
| tc_1c7522a8, TypeLD>, Enc_1f5d8f { |
| let Inst{12-5} = 0b00010000; |
| let Inst{31-21} = 0b10011000010; |
| let addrMode = PostInc; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let Uses = [CS]; |
| let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; |
| } |
| def L2_loadalignh_pi : HInst< |
| (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), |
| (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_1Imm:$Ii), |
| "$Ryy32 = memh_fifo($Rx32++#$Ii)", |
| tc_1c7522a8, TypeLD>, Enc_bd1cbc { |
| let Inst{13-9} = 0b00000; |
| let Inst{31-21} = 0b10011010010; |
| let addrMode = PostInc; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; |
| } |
| def L2_loadalignh_pr : HInst< |
| (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), |
| (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Ryy32 = memh_fifo($Rx32++$Mu2)", |
| tc_1c7522a8, TypeLD>, Enc_1f5d8f { |
| let Inst{12-5} = 0b00000000; |
| let Inst{31-21} = 0b10011100010; |
| let addrMode = PostInc; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; |
| } |
| def L2_loadalignh_zomap : HInst< |
| (outs DoubleRegs:$Ryy32), |
| (ins DoubleRegs:$Ryy32in, IntRegs:$Rs32), |
| "$Ryy32 = memh_fifo($Rs32)", |
| tc_fedb7e19, TypeMAPPING> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| let Constraints = "$Ryy32 = $Ryy32in"; |
| } |
| def L2_loadbsw2_io : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, s31_1Imm:$Ii), |
| "$Rd32 = membh($Rs32+#$Ii)", |
| tc_4222e6bf, TypeLD>, Enc_de0214 { |
| let Inst{24-21} = 0b0001; |
| let Inst{31-27} = 0b10010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseImmOffset; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 12; |
| let opExtentAlign = 1; |
| } |
| def L2_loadbsw2_pbr : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Rd32 = membh($Rx32++$Mu2:brev)", |
| tc_075c8dd8, TypeLD>, Enc_74d4e5 { |
| let Inst{12-5} = 0b00000000; |
| let Inst{31-21} = 0b10011110001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadbsw2_pci : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2), |
| "$Rd32 = membh($Rx32++#$Ii:circ($Mu2))", |
| tc_5ceb2f9e, TypeLD>, Enc_e83554 { |
| let Inst{12-9} = 0b0000; |
| let Inst{31-21} = 0b10011000001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let Uses = [CS]; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadbsw2_pcr : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Rd32 = membh($Rx32++I:circ($Mu2))", |
| tc_075c8dd8, TypeLD>, Enc_74d4e5 { |
| let Inst{12-5} = 0b00010000; |
| let Inst{31-21} = 0b10011000001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let Uses = [CS]; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadbsw2_pi : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, s4_1Imm:$Ii), |
| "$Rd32 = membh($Rx32++#$Ii)", |
| tc_075c8dd8, TypeLD>, Enc_152467 { |
| let Inst{13-9} = 0b00000; |
| let Inst{31-21} = 0b10011010001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadbsw2_pr : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Rd32 = membh($Rx32++$Mu2)", |
| tc_075c8dd8, TypeLD>, Enc_74d4e5 { |
| let Inst{12-5} = 0b00000000; |
| let Inst{31-21} = 0b10011100001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadbsw2_zomap : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = membh($Rs32)", |
| tc_4222e6bf, TypeMAPPING> { |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L2_loadbsw4_io : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins IntRegs:$Rs32, s30_2Imm:$Ii), |
| "$Rdd32 = membh($Rs32+#$Ii)", |
| tc_4222e6bf, TypeLD>, Enc_2d7491 { |
| let Inst{24-21} = 0b0111; |
| let Inst{31-27} = 0b10010; |
| let addrMode = BaseImmOffset; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 13; |
| let opExtentAlign = 2; |
| } |
| def L2_loadbsw4_pbr : HInst< |
| (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Rdd32 = membh($Rx32++$Mu2:brev)", |
| tc_075c8dd8, TypeLD>, Enc_7eee72 { |
| let Inst{12-5} = 0b00000000; |
| let Inst{31-21} = 0b10011110111; |
| let addrMode = PostInc; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadbsw4_pci : HInst< |
| (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2), |
| "$Rdd32 = membh($Rx32++#$Ii:circ($Mu2))", |
| tc_5ceb2f9e, TypeLD>, Enc_70b24b { |
| let Inst{12-9} = 0b0000; |
| let Inst{31-21} = 0b10011000111; |
| let addrMode = PostInc; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let Uses = [CS]; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadbsw4_pcr : HInst< |
| (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Rdd32 = membh($Rx32++I:circ($Mu2))", |
| tc_075c8dd8, TypeLD>, Enc_7eee72 { |
| let Inst{12-5} = 0b00010000; |
| let Inst{31-21} = 0b10011000111; |
| let addrMode = PostInc; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let Uses = [CS]; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadbsw4_pi : HInst< |
| (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, s4_2Imm:$Ii), |
| "$Rdd32 = membh($Rx32++#$Ii)", |
| tc_075c8dd8, TypeLD>, Enc_71f1b4 { |
| let Inst{13-9} = 0b00000; |
| let Inst{31-21} = 0b10011010111; |
| let addrMode = PostInc; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadbsw4_pr : HInst< |
| (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Rdd32 = membh($Rx32++$Mu2)", |
| tc_075c8dd8, TypeLD>, Enc_7eee72 { |
| let Inst{12-5} = 0b00000000; |
| let Inst{31-21} = 0b10011100111; |
| let addrMode = PostInc; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadbsw4_zomap : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins IntRegs:$Rs32), |
| "$Rdd32 = membh($Rs32)", |
| tc_4222e6bf, TypeMAPPING> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L2_loadbzw2_io : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, s31_1Imm:$Ii), |
| "$Rd32 = memubh($Rs32+#$Ii)", |
| tc_4222e6bf, TypeLD>, Enc_de0214 { |
| let Inst{24-21} = 0b0011; |
| let Inst{31-27} = 0b10010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseImmOffset; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 12; |
| let opExtentAlign = 1; |
| } |
| def L2_loadbzw2_pbr : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Rd32 = memubh($Rx32++$Mu2:brev)", |
| tc_075c8dd8, TypeLD>, Enc_74d4e5 { |
| let Inst{12-5} = 0b00000000; |
| let Inst{31-21} = 0b10011110011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadbzw2_pci : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2), |
| "$Rd32 = memubh($Rx32++#$Ii:circ($Mu2))", |
| tc_5ceb2f9e, TypeLD>, Enc_e83554 { |
| let Inst{12-9} = 0b0000; |
| let Inst{31-21} = 0b10011000011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let Uses = [CS]; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadbzw2_pcr : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Rd32 = memubh($Rx32++I:circ($Mu2))", |
| tc_075c8dd8, TypeLD>, Enc_74d4e5 { |
| let Inst{12-5} = 0b00010000; |
| let Inst{31-21} = 0b10011000011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let Uses = [CS]; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadbzw2_pi : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, s4_1Imm:$Ii), |
| "$Rd32 = memubh($Rx32++#$Ii)", |
| tc_075c8dd8, TypeLD>, Enc_152467 { |
| let Inst{13-9} = 0b00000; |
| let Inst{31-21} = 0b10011010011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadbzw2_pr : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Rd32 = memubh($Rx32++$Mu2)", |
| tc_075c8dd8, TypeLD>, Enc_74d4e5 { |
| let Inst{12-5} = 0b00000000; |
| let Inst{31-21} = 0b10011100011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadbzw2_zomap : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = memubh($Rs32)", |
| tc_4222e6bf, TypeMAPPING> { |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L2_loadbzw4_io : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins IntRegs:$Rs32, s30_2Imm:$Ii), |
| "$Rdd32 = memubh($Rs32+#$Ii)", |
| tc_4222e6bf, TypeLD>, Enc_2d7491 { |
| let Inst{24-21} = 0b0101; |
| let Inst{31-27} = 0b10010; |
| let addrMode = BaseImmOffset; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 13; |
| let opExtentAlign = 2; |
| } |
| def L2_loadbzw4_pbr : HInst< |
| (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Rdd32 = memubh($Rx32++$Mu2:brev)", |
| tc_075c8dd8, TypeLD>, Enc_7eee72 { |
| let Inst{12-5} = 0b00000000; |
| let Inst{31-21} = 0b10011110101; |
| let addrMode = PostInc; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadbzw4_pci : HInst< |
| (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2), |
| "$Rdd32 = memubh($Rx32++#$Ii:circ($Mu2))", |
| tc_5ceb2f9e, TypeLD>, Enc_70b24b { |
| let Inst{12-9} = 0b0000; |
| let Inst{31-21} = 0b10011000101; |
| let addrMode = PostInc; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let Uses = [CS]; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadbzw4_pcr : HInst< |
| (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Rdd32 = memubh($Rx32++I:circ($Mu2))", |
| tc_075c8dd8, TypeLD>, Enc_7eee72 { |
| let Inst{12-5} = 0b00010000; |
| let Inst{31-21} = 0b10011000101; |
| let addrMode = PostInc; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let Uses = [CS]; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadbzw4_pi : HInst< |
| (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, s4_2Imm:$Ii), |
| "$Rdd32 = memubh($Rx32++#$Ii)", |
| tc_075c8dd8, TypeLD>, Enc_71f1b4 { |
| let Inst{13-9} = 0b00000; |
| let Inst{31-21} = 0b10011010101; |
| let addrMode = PostInc; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadbzw4_pr : HInst< |
| (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Rdd32 = memubh($Rx32++$Mu2)", |
| tc_075c8dd8, TypeLD>, Enc_7eee72 { |
| let Inst{12-5} = 0b00000000; |
| let Inst{31-21} = 0b10011100101; |
| let addrMode = PostInc; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadbzw4_zomap : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins IntRegs:$Rs32), |
| "$Rdd32 = memubh($Rs32)", |
| tc_4222e6bf, TypeMAPPING> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L2_loadrb_io : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, s32_0Imm:$Ii), |
| "$Rd32 = memb($Rs32+#$Ii)", |
| tc_4222e6bf, TypeLD>, Enc_211aaa, AddrModeRel, PostInc_BaseImm { |
| let Inst{24-21} = 0b1000; |
| let Inst{31-27} = 0b10010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseImmOffset; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrb_io"; |
| let CextOpcode = "L2_loadrb"; |
| let isPredicable = 1; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 0; |
| } |
| def L2_loadrb_pbr : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Rd32 = memb($Rx32++$Mu2:brev)", |
| tc_075c8dd8, TypeLD>, Enc_74d4e5 { |
| let Inst{12-5} = 0b00000000; |
| let Inst{31-21} = 0b10011111000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadrb_pci : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2), |
| "$Rd32 = memb($Rx32++#$Ii:circ($Mu2))", |
| tc_5ceb2f9e, TypeLD>, Enc_e0a47a { |
| let Inst{12-9} = 0b0000; |
| let Inst{31-21} = 0b10011001000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let Uses = [CS]; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadrb_pcr : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Rd32 = memb($Rx32++I:circ($Mu2))", |
| tc_075c8dd8, TypeLD>, Enc_74d4e5 { |
| let Inst{12-5} = 0b00010000; |
| let Inst{31-21} = 0b10011001000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let Uses = [CS]; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadrb_pi : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, s4_0Imm:$Ii), |
| "$Rd32 = memb($Rx32++#$Ii)", |
| tc_075c8dd8, TypeLD>, Enc_222336, PredNewRel, PostInc_BaseImm { |
| let Inst{13-9} = 0b00000; |
| let Inst{31-21} = 0b10011011000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrb_pi"; |
| let CextOpcode = "L2_loadrb"; |
| let isPredicable = 1; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadrb_pr : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Rd32 = memb($Rx32++$Mu2)", |
| tc_075c8dd8, TypeLD>, Enc_74d4e5 { |
| let Inst{12-5} = 0b00000000; |
| let Inst{31-21} = 0b10011101000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadrb_zomap : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = memb($Rs32)", |
| tc_4222e6bf, TypeMAPPING> { |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L2_loadrbgp : HInst< |
| (outs IntRegs:$Rd32), |
| (ins u32_0Imm:$Ii), |
| "$Rd32 = memb(gp+#$Ii)", |
| tc_8a6d0d94, TypeV2LDST>, Enc_25bef0, AddrModeRel { |
| let Inst{24-21} = 0b1000; |
| let Inst{31-27} = 0b01001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let Uses = [GP]; |
| let BaseOpcode = "L4_loadrb_abs"; |
| let isPredicable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 0; |
| let opExtentBits = 16; |
| let opExtentAlign = 0; |
| } |
| def L2_loadrd_io : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins IntRegs:$Rs32, s29_3Imm:$Ii), |
| "$Rdd32 = memd($Rs32+#$Ii)", |
| tc_4222e6bf, TypeLD>, Enc_fa3ba4, AddrModeRel, PostInc_BaseImm { |
| let Inst{24-21} = 0b1110; |
| let Inst{31-27} = 0b10010; |
| let addrMode = BaseImmOffset; |
| let accessSize = DoubleWordAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrd_io"; |
| let CextOpcode = "L2_loadrd"; |
| let isPredicable = 1; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 14; |
| let opExtentAlign = 3; |
| } |
| def L2_loadrd_pbr : HInst< |
| (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Rdd32 = memd($Rx32++$Mu2:brev)", |
| tc_075c8dd8, TypeLD>, Enc_7eee72 { |
| let Inst{12-5} = 0b00000000; |
| let Inst{31-21} = 0b10011111110; |
| let addrMode = PostInc; |
| let accessSize = DoubleWordAccess; |
| let mayLoad = 1; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadrd_pci : HInst< |
| (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, s4_3Imm:$Ii, ModRegs:$Mu2), |
| "$Rdd32 = memd($Rx32++#$Ii:circ($Mu2))", |
| tc_5ceb2f9e, TypeLD>, Enc_b05839 { |
| let Inst{12-9} = 0b0000; |
| let Inst{31-21} = 0b10011001110; |
| let addrMode = PostInc; |
| let accessSize = DoubleWordAccess; |
| let mayLoad = 1; |
| let Uses = [CS]; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadrd_pcr : HInst< |
| (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Rdd32 = memd($Rx32++I:circ($Mu2))", |
| tc_075c8dd8, TypeLD>, Enc_7eee72 { |
| let Inst{12-5} = 0b00010000; |
| let Inst{31-21} = 0b10011001110; |
| let addrMode = PostInc; |
| let accessSize = DoubleWordAccess; |
| let mayLoad = 1; |
| let Uses = [CS]; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadrd_pi : HInst< |
| (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, s4_3Imm:$Ii), |
| "$Rdd32 = memd($Rx32++#$Ii)", |
| tc_075c8dd8, TypeLD>, Enc_5bdd42, PredNewRel, PostInc_BaseImm { |
| let Inst{13-9} = 0b00000; |
| let Inst{31-21} = 0b10011011110; |
| let addrMode = PostInc; |
| let accessSize = DoubleWordAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrd_pi"; |
| let CextOpcode = "L2_loadrd"; |
| let isPredicable = 1; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadrd_pr : HInst< |
| (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Rdd32 = memd($Rx32++$Mu2)", |
| tc_075c8dd8, TypeLD>, Enc_7eee72 { |
| let Inst{12-5} = 0b00000000; |
| let Inst{31-21} = 0b10011101110; |
| let addrMode = PostInc; |
| let accessSize = DoubleWordAccess; |
| let mayLoad = 1; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadrd_zomap : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins IntRegs:$Rs32), |
| "$Rdd32 = memd($Rs32)", |
| tc_4222e6bf, TypeMAPPING> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L2_loadrdgp : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins u29_3Imm:$Ii), |
| "$Rdd32 = memd(gp+#$Ii)", |
| tc_8a6d0d94, TypeV2LDST>, Enc_509701, AddrModeRel { |
| let Inst{24-21} = 0b1110; |
| let Inst{31-27} = 0b01001; |
| let accessSize = DoubleWordAccess; |
| let mayLoad = 1; |
| let Uses = [GP]; |
| let BaseOpcode = "L4_loadrd_abs"; |
| let isPredicable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 0; |
| let opExtentBits = 19; |
| let opExtentAlign = 3; |
| } |
| def L2_loadrh_io : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, s31_1Imm:$Ii), |
| "$Rd32 = memh($Rs32+#$Ii)", |
| tc_4222e6bf, TypeLD>, Enc_de0214, AddrModeRel, PostInc_BaseImm { |
| let Inst{24-21} = 0b1010; |
| let Inst{31-27} = 0b10010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseImmOffset; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrh_io"; |
| let CextOpcode = "L2_loadrh"; |
| let isPredicable = 1; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 12; |
| let opExtentAlign = 1; |
| } |
| def L2_loadrh_pbr : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Rd32 = memh($Rx32++$Mu2:brev)", |
| tc_075c8dd8, TypeLD>, Enc_74d4e5 { |
| let Inst{12-5} = 0b00000000; |
| let Inst{31-21} = 0b10011111010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadrh_pci : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2), |
| "$Rd32 = memh($Rx32++#$Ii:circ($Mu2))", |
| tc_5ceb2f9e, TypeLD>, Enc_e83554 { |
| let Inst{12-9} = 0b0000; |
| let Inst{31-21} = 0b10011001010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let Uses = [CS]; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadrh_pcr : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Rd32 = memh($Rx32++I:circ($Mu2))", |
| tc_075c8dd8, TypeLD>, Enc_74d4e5 { |
| let Inst{12-5} = 0b00010000; |
| let Inst{31-21} = 0b10011001010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let Uses = [CS]; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadrh_pi : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, s4_1Imm:$Ii), |
| "$Rd32 = memh($Rx32++#$Ii)", |
| tc_075c8dd8, TypeLD>, Enc_152467, PredNewRel, PostInc_BaseImm { |
| let Inst{13-9} = 0b00000; |
| let Inst{31-21} = 0b10011011010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrh_pi"; |
| let CextOpcode = "L2_loadrh"; |
| let isPredicable = 1; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadrh_pr : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Rd32 = memh($Rx32++$Mu2)", |
| tc_075c8dd8, TypeLD>, Enc_74d4e5 { |
| let Inst{12-5} = 0b00000000; |
| let Inst{31-21} = 0b10011101010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadrh_zomap : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = memh($Rs32)", |
| tc_4222e6bf, TypeMAPPING> { |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L2_loadrhgp : HInst< |
| (outs IntRegs:$Rd32), |
| (ins u31_1Imm:$Ii), |
| "$Rd32 = memh(gp+#$Ii)", |
| tc_8a6d0d94, TypeV2LDST>, Enc_8df4be, AddrModeRel { |
| let Inst{24-21} = 0b1010; |
| let Inst{31-27} = 0b01001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let Uses = [GP]; |
| let BaseOpcode = "L4_loadrh_abs"; |
| let isPredicable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 0; |
| let opExtentBits = 17; |
| let opExtentAlign = 1; |
| } |
| def L2_loadri_io : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, s30_2Imm:$Ii), |
| "$Rd32 = memw($Rs32+#$Ii)", |
| tc_4222e6bf, TypeLD>, Enc_2a3787, AddrModeRel, PostInc_BaseImm { |
| let Inst{24-21} = 0b1100; |
| let Inst{31-27} = 0b10010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseImmOffset; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadri_io"; |
| let CextOpcode = "L2_loadri"; |
| let isPredicable = 1; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 13; |
| let opExtentAlign = 2; |
| } |
| def L2_loadri_pbr : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Rd32 = memw($Rx32++$Mu2:brev)", |
| tc_075c8dd8, TypeLD>, Enc_74d4e5 { |
| let Inst{12-5} = 0b00000000; |
| let Inst{31-21} = 0b10011111100; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadri_pci : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2), |
| "$Rd32 = memw($Rx32++#$Ii:circ($Mu2))", |
| tc_5ceb2f9e, TypeLD>, Enc_27fd0e { |
| let Inst{12-9} = 0b0000; |
| let Inst{31-21} = 0b10011001100; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let Uses = [CS]; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadri_pcr : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Rd32 = memw($Rx32++I:circ($Mu2))", |
| tc_075c8dd8, TypeLD>, Enc_74d4e5 { |
| let Inst{12-5} = 0b00010000; |
| let Inst{31-21} = 0b10011001100; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let Uses = [CS]; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadri_pi : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, s4_2Imm:$Ii), |
| "$Rd32 = memw($Rx32++#$Ii)", |
| tc_075c8dd8, TypeLD>, Enc_3d920a, PredNewRel, PostInc_BaseImm { |
| let Inst{13-9} = 0b00000; |
| let Inst{31-21} = 0b10011011100; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadri_pi"; |
| let CextOpcode = "L2_loadri"; |
| let isPredicable = 1; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadri_pr : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Rd32 = memw($Rx32++$Mu2)", |
| tc_075c8dd8, TypeLD>, Enc_74d4e5 { |
| let Inst{12-5} = 0b00000000; |
| let Inst{31-21} = 0b10011101100; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadri_zomap : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = memw($Rs32)", |
| tc_4222e6bf, TypeMAPPING> { |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L2_loadrigp : HInst< |
| (outs IntRegs:$Rd32), |
| (ins u30_2Imm:$Ii), |
| "$Rd32 = memw(gp+#$Ii)", |
| tc_8a6d0d94, TypeV2LDST>, Enc_4f4ed7, AddrModeRel { |
| let Inst{24-21} = 0b1100; |
| let Inst{31-27} = 0b01001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let Uses = [GP]; |
| let BaseOpcode = "L4_loadri_abs"; |
| let isPredicable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 0; |
| let opExtentBits = 18; |
| let opExtentAlign = 2; |
| } |
| def L2_loadrub_io : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, s32_0Imm:$Ii), |
| "$Rd32 = memub($Rs32+#$Ii)", |
| tc_4222e6bf, TypeLD>, Enc_211aaa, AddrModeRel, PostInc_BaseImm { |
| let Inst{24-21} = 0b1001; |
| let Inst{31-27} = 0b10010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseImmOffset; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrub_io"; |
| let CextOpcode = "L2_loadrub"; |
| let isPredicable = 1; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 11; |
| let opExtentAlign = 0; |
| } |
| def L2_loadrub_pbr : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Rd32 = memub($Rx32++$Mu2:brev)", |
| tc_075c8dd8, TypeLD>, Enc_74d4e5 { |
| let Inst{12-5} = 0b00000000; |
| let Inst{31-21} = 0b10011111001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadrub_pci : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2), |
| "$Rd32 = memub($Rx32++#$Ii:circ($Mu2))", |
| tc_5ceb2f9e, TypeLD>, Enc_e0a47a { |
| let Inst{12-9} = 0b0000; |
| let Inst{31-21} = 0b10011001001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let Uses = [CS]; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadrub_pcr : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Rd32 = memub($Rx32++I:circ($Mu2))", |
| tc_075c8dd8, TypeLD>, Enc_74d4e5 { |
| let Inst{12-5} = 0b00010000; |
| let Inst{31-21} = 0b10011001001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let Uses = [CS]; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadrub_pi : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, s4_0Imm:$Ii), |
| "$Rd32 = memub($Rx32++#$Ii)", |
| tc_075c8dd8, TypeLD>, Enc_222336, PredNewRel, PostInc_BaseImm { |
| let Inst{13-9} = 0b00000; |
| let Inst{31-21} = 0b10011011001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrub_pi"; |
| let CextOpcode = "L2_loadrub"; |
| let isPredicable = 1; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadrub_pr : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Rd32 = memub($Rx32++$Mu2)", |
| tc_075c8dd8, TypeLD>, Enc_74d4e5 { |
| let Inst{12-5} = 0b00000000; |
| let Inst{31-21} = 0b10011101001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadrub_zomap : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = memub($Rs32)", |
| tc_4222e6bf, TypeMAPPING> { |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L2_loadrubgp : HInst< |
| (outs IntRegs:$Rd32), |
| (ins u32_0Imm:$Ii), |
| "$Rd32 = memub(gp+#$Ii)", |
| tc_8a6d0d94, TypeV2LDST>, Enc_25bef0, AddrModeRel { |
| let Inst{24-21} = 0b1001; |
| let Inst{31-27} = 0b01001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let Uses = [GP]; |
| let BaseOpcode = "L4_loadrub_abs"; |
| let isPredicable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 0; |
| let opExtentBits = 16; |
| let opExtentAlign = 0; |
| } |
| def L2_loadruh_io : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, s31_1Imm:$Ii), |
| "$Rd32 = memuh($Rs32+#$Ii)", |
| tc_4222e6bf, TypeLD>, Enc_de0214, AddrModeRel, PostInc_BaseImm { |
| let Inst{24-21} = 0b1011; |
| let Inst{31-27} = 0b10010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseImmOffset; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadruh_io"; |
| let CextOpcode = "L2_loadruh"; |
| let isPredicable = 1; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 12; |
| let opExtentAlign = 1; |
| } |
| def L2_loadruh_pbr : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Rd32 = memuh($Rx32++$Mu2:brev)", |
| tc_075c8dd8, TypeLD>, Enc_74d4e5 { |
| let Inst{12-5} = 0b00000000; |
| let Inst{31-21} = 0b10011111011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadruh_pci : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2), |
| "$Rd32 = memuh($Rx32++#$Ii:circ($Mu2))", |
| tc_5ceb2f9e, TypeLD>, Enc_e83554 { |
| let Inst{12-9} = 0b0000; |
| let Inst{31-21} = 0b10011001011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let Uses = [CS]; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadruh_pcr : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Rd32 = memuh($Rx32++I:circ($Mu2))", |
| tc_075c8dd8, TypeLD>, Enc_74d4e5 { |
| let Inst{12-5} = 0b00010000; |
| let Inst{31-21} = 0b10011001011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let Uses = [CS]; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadruh_pi : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, s4_1Imm:$Ii), |
| "$Rd32 = memuh($Rx32++#$Ii)", |
| tc_075c8dd8, TypeLD>, Enc_152467, PredNewRel, PostInc_BaseImm { |
| let Inst{13-9} = 0b00000; |
| let Inst{31-21} = 0b10011011011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadruh_pi"; |
| let CextOpcode = "L2_loadruh"; |
| let isPredicable = 1; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadruh_pr : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, ModRegs:$Mu2), |
| "$Rd32 = memuh($Rx32++$Mu2)", |
| tc_075c8dd8, TypeLD>, Enc_74d4e5 { |
| let Inst{12-5} = 0b00000000; |
| let Inst{31-21} = 0b10011101011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_loadruh_zomap : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = memuh($Rs32)", |
| tc_4222e6bf, TypeMAPPING> { |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L2_loadruhgp : HInst< |
| (outs IntRegs:$Rd32), |
| (ins u31_1Imm:$Ii), |
| "$Rd32 = memuh(gp+#$Ii)", |
| tc_8a6d0d94, TypeV2LDST>, Enc_8df4be, AddrModeRel { |
| let Inst{24-21} = 0b1011; |
| let Inst{31-27} = 0b01001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let Uses = [GP]; |
| let BaseOpcode = "L4_loadruh_abs"; |
| let isPredicable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 0; |
| let opExtentBits = 17; |
| let opExtentAlign = 1; |
| } |
| def L2_loadw_aq : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = memw_aq($Rs32)", |
| tc_2471c1c8, TypeLD>, Enc_5e2823, Requires<[HasV68]> { |
| let Inst{13-5} = 0b001000000; |
| let Inst{31-21} = 0b10010010000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| } |
| def L2_loadw_locked : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = memw_locked($Rs32)", |
| tc_64b00d8a, TypeLD>, Enc_5e2823 { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-21} = 0b10010010000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let isSoloAX = 1; |
| } |
| def L2_ploadrbf_io : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), |
| "if (!$Pt4) $Rd32 = memb($Rs32+#$Ii)", |
| tc_fedb7e19, TypeV2LDST>, Enc_a21d47, AddrModeRel { |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b01000101000; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseImmOffset; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrb_io"; |
| let CextOpcode = "L2_loadrb"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L2_ploadrbf_pi : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), |
| "if (!$Pt4) $Rd32 = memb($Rx32++#$Ii)", |
| tc_1c7522a8, TypeLD>, Enc_f4413a, PredNewRel { |
| let Inst{13-11} = 0b101; |
| let Inst{31-21} = 0b10011011000; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrb_pi"; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_ploadrbf_zomap : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32), |
| "if (!$Pt4) $Rd32 = memb($Rs32)", |
| tc_fedb7e19, TypeMAPPING> { |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L2_ploadrbfnew_io : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), |
| "if (!$Pt4.new) $Rd32 = memb($Rs32+#$Ii)", |
| tc_075c8dd8, TypeV2LDST>, Enc_a21d47, AddrModeRel { |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b01000111000; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseImmOffset; |
| let accessSize = ByteAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrb_io"; |
| let CextOpcode = "L2_loadrb"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L2_ploadrbfnew_pi : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), |
| "if (!$Pt4.new) $Rd32 = memb($Rx32++#$Ii)", |
| tc_5f2afaf7, TypeLD>, Enc_f4413a, PredNewRel { |
| let Inst{13-11} = 0b111; |
| let Inst{31-21} = 0b10011011000; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = ByteAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrb_pi"; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_ploadrbfnew_zomap : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32), |
| "if (!$Pt4.new) $Rd32 = memb($Rs32)", |
| tc_075c8dd8, TypeMAPPING> { |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L2_ploadrbt_io : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), |
| "if ($Pt4) $Rd32 = memb($Rs32+#$Ii)", |
| tc_fedb7e19, TypeV2LDST>, Enc_a21d47, AddrModeRel { |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b01000001000; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseImmOffset; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrb_io"; |
| let CextOpcode = "L2_loadrb"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L2_ploadrbt_pi : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), |
| "if ($Pt4) $Rd32 = memb($Rx32++#$Ii)", |
| tc_1c7522a8, TypeLD>, Enc_f4413a, PredNewRel { |
| let Inst{13-11} = 0b100; |
| let Inst{31-21} = 0b10011011000; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrb_pi"; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_ploadrbt_zomap : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32), |
| "if ($Pt4) $Rd32 = memb($Rs32)", |
| tc_fedb7e19, TypeMAPPING> { |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L2_ploadrbtnew_io : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), |
| "if ($Pt4.new) $Rd32 = memb($Rs32+#$Ii)", |
| tc_075c8dd8, TypeV2LDST>, Enc_a21d47, AddrModeRel { |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b01000011000; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseImmOffset; |
| let accessSize = ByteAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrb_io"; |
| let CextOpcode = "L2_loadrb"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L2_ploadrbtnew_pi : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), |
| "if ($Pt4.new) $Rd32 = memb($Rx32++#$Ii)", |
| tc_5f2afaf7, TypeLD>, Enc_f4413a, PredNewRel { |
| let Inst{13-11} = 0b110; |
| let Inst{31-21} = 0b10011011000; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = ByteAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrb_pi"; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_ploadrbtnew_zomap : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32), |
| "if ($Pt4.new) $Rd32 = memb($Rs32)", |
| tc_075c8dd8, TypeMAPPING> { |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L2_ploadrdf_io : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii), |
| "if (!$Pt4) $Rdd32 = memd($Rs32+#$Ii)", |
| tc_fedb7e19, TypeV2LDST>, Enc_acd6ed, AddrModeRel { |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b01000101110; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let addrMode = BaseImmOffset; |
| let accessSize = DoubleWordAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrd_io"; |
| let CextOpcode = "L2_loadrd"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 9; |
| let opExtentAlign = 3; |
| } |
| def L2_ploadrdf_pi : HInst< |
| (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), |
| (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii), |
| "if (!$Pt4) $Rdd32 = memd($Rx32++#$Ii)", |
| tc_1c7522a8, TypeLD>, Enc_9d1247, PredNewRel { |
| let Inst{13-11} = 0b101; |
| let Inst{31-21} = 0b10011011110; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let addrMode = PostInc; |
| let accessSize = DoubleWordAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrd_pi"; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_ploadrdf_zomap : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32), |
| "if (!$Pt4) $Rdd32 = memd($Rs32)", |
| tc_fedb7e19, TypeMAPPING> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L2_ploadrdfnew_io : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii), |
| "if (!$Pt4.new) $Rdd32 = memd($Rs32+#$Ii)", |
| tc_075c8dd8, TypeV2LDST>, Enc_acd6ed, AddrModeRel { |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b01000111110; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let addrMode = BaseImmOffset; |
| let accessSize = DoubleWordAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrd_io"; |
| let CextOpcode = "L2_loadrd"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 9; |
| let opExtentAlign = 3; |
| } |
| def L2_ploadrdfnew_pi : HInst< |
| (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), |
| (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii), |
| "if (!$Pt4.new) $Rdd32 = memd($Rx32++#$Ii)", |
| tc_5f2afaf7, TypeLD>, Enc_9d1247, PredNewRel { |
| let Inst{13-11} = 0b111; |
| let Inst{31-21} = 0b10011011110; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let addrMode = PostInc; |
| let accessSize = DoubleWordAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrd_pi"; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_ploadrdfnew_zomap : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32), |
| "if (!$Pt4.new) $Rdd32 = memd($Rs32)", |
| tc_075c8dd8, TypeMAPPING> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L2_ploadrdt_io : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii), |
| "if ($Pt4) $Rdd32 = memd($Rs32+#$Ii)", |
| tc_fedb7e19, TypeV2LDST>, Enc_acd6ed, AddrModeRel { |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b01000001110; |
| let isPredicated = 1; |
| let addrMode = BaseImmOffset; |
| let accessSize = DoubleWordAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrd_io"; |
| let CextOpcode = "L2_loadrd"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 9; |
| let opExtentAlign = 3; |
| } |
| def L2_ploadrdt_pi : HInst< |
| (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), |
| (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii), |
| "if ($Pt4) $Rdd32 = memd($Rx32++#$Ii)", |
| tc_1c7522a8, TypeLD>, Enc_9d1247, PredNewRel { |
| let Inst{13-11} = 0b100; |
| let Inst{31-21} = 0b10011011110; |
| let isPredicated = 1; |
| let addrMode = PostInc; |
| let accessSize = DoubleWordAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrd_pi"; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_ploadrdt_zomap : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32), |
| "if ($Pt4) $Rdd32 = memd($Rs32)", |
| tc_fedb7e19, TypeMAPPING> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L2_ploadrdtnew_io : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii), |
| "if ($Pt4.new) $Rdd32 = memd($Rs32+#$Ii)", |
| tc_075c8dd8, TypeV2LDST>, Enc_acd6ed, AddrModeRel { |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b01000011110; |
| let isPredicated = 1; |
| let addrMode = BaseImmOffset; |
| let accessSize = DoubleWordAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrd_io"; |
| let CextOpcode = "L2_loadrd"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 9; |
| let opExtentAlign = 3; |
| } |
| def L2_ploadrdtnew_pi : HInst< |
| (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), |
| (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii), |
| "if ($Pt4.new) $Rdd32 = memd($Rx32++#$Ii)", |
| tc_5f2afaf7, TypeLD>, Enc_9d1247, PredNewRel { |
| let Inst{13-11} = 0b110; |
| let Inst{31-21} = 0b10011011110; |
| let isPredicated = 1; |
| let addrMode = PostInc; |
| let accessSize = DoubleWordAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrd_pi"; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_ploadrdtnew_zomap : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32), |
| "if ($Pt4.new) $Rdd32 = memd($Rs32)", |
| tc_075c8dd8, TypeMAPPING> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L2_ploadrhf_io : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), |
| "if (!$Pt4) $Rd32 = memh($Rs32+#$Ii)", |
| tc_fedb7e19, TypeV2LDST>, Enc_a198f6, AddrModeRel { |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b01000101010; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseImmOffset; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrh_io"; |
| let CextOpcode = "L2_loadrh"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 7; |
| let opExtentAlign = 1; |
| } |
| def L2_ploadrhf_pi : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), |
| "if (!$Pt4) $Rd32 = memh($Rx32++#$Ii)", |
| tc_1c7522a8, TypeLD>, Enc_733b27, PredNewRel { |
| let Inst{13-11} = 0b101; |
| let Inst{31-21} = 0b10011011010; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrh_pi"; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_ploadrhf_zomap : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32), |
| "if (!$Pt4) $Rd32 = memh($Rs32)", |
| tc_fedb7e19, TypeMAPPING> { |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L2_ploadrhfnew_io : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), |
| "if (!$Pt4.new) $Rd32 = memh($Rs32+#$Ii)", |
| tc_075c8dd8, TypeV2LDST>, Enc_a198f6, AddrModeRel { |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b01000111010; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseImmOffset; |
| let accessSize = HalfWordAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrh_io"; |
| let CextOpcode = "L2_loadrh"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 7; |
| let opExtentAlign = 1; |
| } |
| def L2_ploadrhfnew_pi : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), |
| "if (!$Pt4.new) $Rd32 = memh($Rx32++#$Ii)", |
| tc_5f2afaf7, TypeLD>, Enc_733b27, PredNewRel { |
| let Inst{13-11} = 0b111; |
| let Inst{31-21} = 0b10011011010; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = HalfWordAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrh_pi"; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_ploadrhfnew_zomap : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32), |
| "if (!$Pt4.new) $Rd32 = memh($Rs32)", |
| tc_075c8dd8, TypeMAPPING> { |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L2_ploadrht_io : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), |
| "if ($Pt4) $Rd32 = memh($Rs32+#$Ii)", |
| tc_fedb7e19, TypeV2LDST>, Enc_a198f6, AddrModeRel { |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b01000001010; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseImmOffset; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrh_io"; |
| let CextOpcode = "L2_loadrh"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 7; |
| let opExtentAlign = 1; |
| } |
| def L2_ploadrht_pi : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), |
| "if ($Pt4) $Rd32 = memh($Rx32++#$Ii)", |
| tc_1c7522a8, TypeLD>, Enc_733b27, PredNewRel { |
| let Inst{13-11} = 0b100; |
| let Inst{31-21} = 0b10011011010; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrh_pi"; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_ploadrht_zomap : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32), |
| "if ($Pt4) $Rd32 = memh($Rs32)", |
| tc_fedb7e19, TypeMAPPING> { |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L2_ploadrhtnew_io : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), |
| "if ($Pt4.new) $Rd32 = memh($Rs32+#$Ii)", |
| tc_075c8dd8, TypeV2LDST>, Enc_a198f6, AddrModeRel { |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b01000011010; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseImmOffset; |
| let accessSize = HalfWordAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrh_io"; |
| let CextOpcode = "L2_loadrh"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 7; |
| let opExtentAlign = 1; |
| } |
| def L2_ploadrhtnew_pi : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), |
| "if ($Pt4.new) $Rd32 = memh($Rx32++#$Ii)", |
| tc_5f2afaf7, TypeLD>, Enc_733b27, PredNewRel { |
| let Inst{13-11} = 0b110; |
| let Inst{31-21} = 0b10011011010; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = HalfWordAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrh_pi"; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_ploadrhtnew_zomap : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32), |
| "if ($Pt4.new) $Rd32 = memh($Rs32)", |
| tc_075c8dd8, TypeMAPPING> { |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L2_ploadrif_io : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii), |
| "if (!$Pt4) $Rd32 = memw($Rs32+#$Ii)", |
| tc_fedb7e19, TypeV2LDST>, Enc_f82eaf, AddrModeRel { |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b01000101100; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseImmOffset; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadri_io"; |
| let CextOpcode = "L2_loadri"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 8; |
| let opExtentAlign = 2; |
| } |
| def L2_ploadrif_pi : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii), |
| "if (!$Pt4) $Rd32 = memw($Rx32++#$Ii)", |
| tc_1c7522a8, TypeLD>, Enc_b97f71, PredNewRel { |
| let Inst{13-11} = 0b101; |
| let Inst{31-21} = 0b10011011100; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadri_pi"; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_ploadrif_zomap : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32), |
| "if (!$Pt4) $Rd32 = memw($Rs32)", |
| tc_fedb7e19, TypeMAPPING> { |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L2_ploadrifnew_io : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii), |
| "if (!$Pt4.new) $Rd32 = memw($Rs32+#$Ii)", |
| tc_075c8dd8, TypeV2LDST>, Enc_f82eaf, AddrModeRel { |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b01000111100; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseImmOffset; |
| let accessSize = WordAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadri_io"; |
| let CextOpcode = "L2_loadri"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 8; |
| let opExtentAlign = 2; |
| } |
| def L2_ploadrifnew_pi : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii), |
| "if (!$Pt4.new) $Rd32 = memw($Rx32++#$Ii)", |
| tc_5f2afaf7, TypeLD>, Enc_b97f71, PredNewRel { |
| let Inst{13-11} = 0b111; |
| let Inst{31-21} = 0b10011011100; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = WordAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadri_pi"; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_ploadrifnew_zomap : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32), |
| "if (!$Pt4.new) $Rd32 = memw($Rs32)", |
| tc_075c8dd8, TypeMAPPING> { |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L2_ploadrit_io : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii), |
| "if ($Pt4) $Rd32 = memw($Rs32+#$Ii)", |
| tc_fedb7e19, TypeV2LDST>, Enc_f82eaf, AddrModeRel { |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b01000001100; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseImmOffset; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadri_io"; |
| let CextOpcode = "L2_loadri"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 8; |
| let opExtentAlign = 2; |
| } |
| def L2_ploadrit_pi : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii), |
| "if ($Pt4) $Rd32 = memw($Rx32++#$Ii)", |
| tc_1c7522a8, TypeLD>, Enc_b97f71, PredNewRel { |
| let Inst{13-11} = 0b100; |
| let Inst{31-21} = 0b10011011100; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadri_pi"; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_ploadrit_zomap : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32), |
| "if ($Pt4) $Rd32 = memw($Rs32)", |
| tc_fedb7e19, TypeMAPPING> { |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L2_ploadritnew_io : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii), |
| "if ($Pt4.new) $Rd32 = memw($Rs32+#$Ii)", |
| tc_075c8dd8, TypeV2LDST>, Enc_f82eaf, AddrModeRel { |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b01000011100; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseImmOffset; |
| let accessSize = WordAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadri_io"; |
| let CextOpcode = "L2_loadri"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 8; |
| let opExtentAlign = 2; |
| } |
| def L2_ploadritnew_pi : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii), |
| "if ($Pt4.new) $Rd32 = memw($Rx32++#$Ii)", |
| tc_5f2afaf7, TypeLD>, Enc_b97f71, PredNewRel { |
| let Inst{13-11} = 0b110; |
| let Inst{31-21} = 0b10011011100; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = WordAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadri_pi"; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_ploadritnew_zomap : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32), |
| "if ($Pt4.new) $Rd32 = memw($Rs32)", |
| tc_075c8dd8, TypeMAPPING> { |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L2_ploadrubf_io : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), |
| "if (!$Pt4) $Rd32 = memub($Rs32+#$Ii)", |
| tc_fedb7e19, TypeV2LDST>, Enc_a21d47, AddrModeRel { |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b01000101001; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseImmOffset; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrub_io"; |
| let CextOpcode = "L2_loadrub"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L2_ploadrubf_pi : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), |
| "if (!$Pt4) $Rd32 = memub($Rx32++#$Ii)", |
| tc_1c7522a8, TypeLD>, Enc_f4413a, PredNewRel { |
| let Inst{13-11} = 0b101; |
| let Inst{31-21} = 0b10011011001; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrub_pi"; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_ploadrubf_zomap : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32), |
| "if (!$Pt4) $Rd32 = memub($Rs32)", |
| tc_fedb7e19, TypeMAPPING> { |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L2_ploadrubfnew_io : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), |
| "if (!$Pt4.new) $Rd32 = memub($Rs32+#$Ii)", |
| tc_075c8dd8, TypeV2LDST>, Enc_a21d47, AddrModeRel { |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b01000111001; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseImmOffset; |
| let accessSize = ByteAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrub_io"; |
| let CextOpcode = "L2_loadrub"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L2_ploadrubfnew_pi : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), |
| "if (!$Pt4.new) $Rd32 = memub($Rx32++#$Ii)", |
| tc_5f2afaf7, TypeLD>, Enc_f4413a, PredNewRel { |
| let Inst{13-11} = 0b111; |
| let Inst{31-21} = 0b10011011001; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = ByteAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrub_pi"; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_ploadrubfnew_zomap : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32), |
| "if (!$Pt4.new) $Rd32 = memub($Rs32)", |
| tc_075c8dd8, TypeMAPPING> { |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L2_ploadrubt_io : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), |
| "if ($Pt4) $Rd32 = memub($Rs32+#$Ii)", |
| tc_fedb7e19, TypeV2LDST>, Enc_a21d47, AddrModeRel { |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b01000001001; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseImmOffset; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrub_io"; |
| let CextOpcode = "L2_loadrub"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L2_ploadrubt_pi : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), |
| "if ($Pt4) $Rd32 = memub($Rx32++#$Ii)", |
| tc_1c7522a8, TypeLD>, Enc_f4413a, PredNewRel { |
| let Inst{13-11} = 0b100; |
| let Inst{31-21} = 0b10011011001; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrub_pi"; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_ploadrubt_zomap : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32), |
| "if ($Pt4) $Rd32 = memub($Rs32)", |
| tc_fedb7e19, TypeMAPPING> { |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L2_ploadrubtnew_io : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), |
| "if ($Pt4.new) $Rd32 = memub($Rs32+#$Ii)", |
| tc_075c8dd8, TypeV2LDST>, Enc_a21d47, AddrModeRel { |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b01000011001; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseImmOffset; |
| let accessSize = ByteAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrub_io"; |
| let CextOpcode = "L2_loadrub"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L2_ploadrubtnew_pi : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), |
| "if ($Pt4.new) $Rd32 = memub($Rx32++#$Ii)", |
| tc_5f2afaf7, TypeLD>, Enc_f4413a, PredNewRel { |
| let Inst{13-11} = 0b110; |
| let Inst{31-21} = 0b10011011001; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = ByteAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadrub_pi"; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_ploadrubtnew_zomap : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32), |
| "if ($Pt4.new) $Rd32 = memub($Rs32)", |
| tc_075c8dd8, TypeMAPPING> { |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L2_ploadruhf_io : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), |
| "if (!$Pt4) $Rd32 = memuh($Rs32+#$Ii)", |
| tc_fedb7e19, TypeV2LDST>, Enc_a198f6, AddrModeRel { |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b01000101011; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseImmOffset; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadruh_io"; |
| let CextOpcode = "L2_loadruh"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 7; |
| let opExtentAlign = 1; |
| } |
| def L2_ploadruhf_pi : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), |
| "if (!$Pt4) $Rd32 = memuh($Rx32++#$Ii)", |
| tc_1c7522a8, TypeLD>, Enc_733b27, PredNewRel { |
| let Inst{13-11} = 0b101; |
| let Inst{31-21} = 0b10011011011; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadruh_pi"; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_ploadruhf_zomap : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32), |
| "if (!$Pt4) $Rd32 = memuh($Rs32)", |
| tc_fedb7e19, TypeMAPPING> { |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L2_ploadruhfnew_io : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), |
| "if (!$Pt4.new) $Rd32 = memuh($Rs32+#$Ii)", |
| tc_075c8dd8, TypeV2LDST>, Enc_a198f6, AddrModeRel { |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b01000111011; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseImmOffset; |
| let accessSize = HalfWordAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadruh_io"; |
| let CextOpcode = "L2_loadruh"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 7; |
| let opExtentAlign = 1; |
| } |
| def L2_ploadruhfnew_pi : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), |
| "if (!$Pt4.new) $Rd32 = memuh($Rx32++#$Ii)", |
| tc_5f2afaf7, TypeLD>, Enc_733b27, PredNewRel { |
| let Inst{13-11} = 0b111; |
| let Inst{31-21} = 0b10011011011; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = HalfWordAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadruh_pi"; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_ploadruhfnew_zomap : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32), |
| "if (!$Pt4.new) $Rd32 = memuh($Rs32)", |
| tc_075c8dd8, TypeMAPPING> { |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L2_ploadruht_io : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), |
| "if ($Pt4) $Rd32 = memuh($Rs32+#$Ii)", |
| tc_fedb7e19, TypeV2LDST>, Enc_a198f6, AddrModeRel { |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b01000001011; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseImmOffset; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadruh_io"; |
| let CextOpcode = "L2_loadruh"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 7; |
| let opExtentAlign = 1; |
| } |
| def L2_ploadruht_pi : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), |
| "if ($Pt4) $Rd32 = memuh($Rx32++#$Ii)", |
| tc_1c7522a8, TypeLD>, Enc_733b27, PredNewRel { |
| let Inst{13-11} = 0b100; |
| let Inst{31-21} = 0b10011011011; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadruh_pi"; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_ploadruht_zomap : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32), |
| "if ($Pt4) $Rd32 = memuh($Rs32)", |
| tc_fedb7e19, TypeMAPPING> { |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L2_ploadruhtnew_io : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), |
| "if ($Pt4.new) $Rd32 = memuh($Rs32+#$Ii)", |
| tc_075c8dd8, TypeV2LDST>, Enc_a198f6, AddrModeRel { |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b01000011011; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseImmOffset; |
| let accessSize = HalfWordAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadruh_io"; |
| let CextOpcode = "L2_loadruh"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 7; |
| let opExtentAlign = 1; |
| } |
| def L2_ploadruhtnew_pi : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Rx32), |
| (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), |
| "if ($Pt4.new) $Rd32 = memuh($Rx32++#$Ii)", |
| tc_5f2afaf7, TypeLD>, Enc_733b27, PredNewRel { |
| let Inst{13-11} = 0b110; |
| let Inst{31-21} = 0b10011011011; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = PostInc; |
| let accessSize = HalfWordAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let BaseOpcode = "L2_loadruh_pi"; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def L2_ploadruhtnew_zomap : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, IntRegs:$Rs32), |
| "if ($Pt4.new) $Rd32 = memuh($Rs32)", |
| tc_075c8dd8, TypeMAPPING> { |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L4_add_memopb_io : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), |
| "memb($Rs32+#$Ii) += $Rt32", |
| tc_9bcfb2ee, TypeV4LDST>, Enc_d44e31 { |
| let Inst{6-5} = 0b00; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b00111110000; |
| let addrMode = BaseImmOffset; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let isRestrictNoSlot1Store = 1; |
| let mayStore = 1; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_add_memopb_zomap : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "memb($Rs32) += $Rt32", |
| tc_9bcfb2ee, TypeMAPPING> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L4_add_memoph_io : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), |
| "memh($Rs32+#$Ii) += $Rt32", |
| tc_9bcfb2ee, TypeV4LDST>, Enc_163a3c { |
| let Inst{6-5} = 0b00; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b00111110001; |
| let addrMode = BaseImmOffset; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let isRestrictNoSlot1Store = 1; |
| let mayStore = 1; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 0; |
| let opExtentBits = 7; |
| let opExtentAlign = 1; |
| } |
| def L4_add_memoph_zomap : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "memh($Rs32) += $Rt32", |
| tc_9bcfb2ee, TypeMAPPING> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L4_add_memopw_io : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), |
| "memw($Rs32+#$Ii) += $Rt32", |
| tc_9bcfb2ee, TypeV4LDST>, Enc_226535 { |
| let Inst{6-5} = 0b00; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b00111110010; |
| let addrMode = BaseImmOffset; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let isRestrictNoSlot1Store = 1; |
| let mayStore = 1; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 0; |
| let opExtentBits = 8; |
| let opExtentAlign = 2; |
| } |
| def L4_add_memopw_zomap : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "memw($Rs32) += $Rt32", |
| tc_9bcfb2ee, TypeMAPPING> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L4_and_memopb_io : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), |
| "memb($Rs32+#$Ii) &= $Rt32", |
| tc_9bcfb2ee, TypeV4LDST>, Enc_d44e31 { |
| let Inst{6-5} = 0b10; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b00111110000; |
| let addrMode = BaseImmOffset; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let isRestrictNoSlot1Store = 1; |
| let mayStore = 1; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_and_memopb_zomap : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "memb($Rs32) &= $Rt32", |
| tc_9bcfb2ee, TypeMAPPING> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L4_and_memoph_io : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), |
| "memh($Rs32+#$Ii) &= $Rt32", |
| tc_9bcfb2ee, TypeV4LDST>, Enc_163a3c { |
| let Inst{6-5} = 0b10; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b00111110001; |
| let addrMode = BaseImmOffset; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let isRestrictNoSlot1Store = 1; |
| let mayStore = 1; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 0; |
| let opExtentBits = 7; |
| let opExtentAlign = 1; |
| } |
| def L4_and_memoph_zomap : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "memh($Rs32) &= $Rt32", |
| tc_9bcfb2ee, TypeMAPPING> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L4_and_memopw_io : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), |
| "memw($Rs32+#$Ii) &= $Rt32", |
| tc_9bcfb2ee, TypeV4LDST>, Enc_226535 { |
| let Inst{6-5} = 0b10; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b00111110010; |
| let addrMode = BaseImmOffset; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let isRestrictNoSlot1Store = 1; |
| let mayStore = 1; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 0; |
| let opExtentBits = 8; |
| let opExtentAlign = 2; |
| } |
| def L4_and_memopw_zomap : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "memw($Rs32) &= $Rt32", |
| tc_9bcfb2ee, TypeMAPPING> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L4_iadd_memopb_io : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II), |
| "memb($Rs32+#$Ii) += #$II", |
| tc_158aa3f7, TypeV4LDST>, Enc_46c951 { |
| let Inst{6-5} = 0b00; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b00111111000; |
| let addrMode = BaseImmOffset; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let isRestrictNoSlot1Store = 1; |
| let mayStore = 1; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_iadd_memopb_zomap : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, u5_0Imm:$II), |
| "memb($Rs32) += #$II", |
| tc_158aa3f7, TypeMAPPING> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L4_iadd_memoph_io : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II), |
| "memh($Rs32+#$Ii) += #$II", |
| tc_158aa3f7, TypeV4LDST>, Enc_e66a97 { |
| let Inst{6-5} = 0b00; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b00111111001; |
| let addrMode = BaseImmOffset; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let isRestrictNoSlot1Store = 1; |
| let mayStore = 1; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 0; |
| let opExtentBits = 7; |
| let opExtentAlign = 1; |
| } |
| def L4_iadd_memoph_zomap : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, u5_0Imm:$II), |
| "memh($Rs32) += #$II", |
| tc_158aa3f7, TypeMAPPING> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L4_iadd_memopw_io : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II), |
| "memw($Rs32+#$Ii) += #$II", |
| tc_158aa3f7, TypeV4LDST>, Enc_84b2cd { |
| let Inst{6-5} = 0b00; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b00111111010; |
| let addrMode = BaseImmOffset; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let isRestrictNoSlot1Store = 1; |
| let mayStore = 1; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 0; |
| let opExtentBits = 8; |
| let opExtentAlign = 2; |
| } |
| def L4_iadd_memopw_zomap : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, u5_0Imm:$II), |
| "memw($Rs32) += #$II", |
| tc_158aa3f7, TypeMAPPING> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L4_iand_memopb_io : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II), |
| "memb($Rs32+#$Ii) = clrbit(#$II)", |
| tc_158aa3f7, TypeV4LDST>, Enc_46c951 { |
| let Inst{6-5} = 0b10; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b00111111000; |
| let addrMode = BaseImmOffset; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let isRestrictNoSlot1Store = 1; |
| let mayStore = 1; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_iand_memopb_zomap : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, u5_0Imm:$II), |
| "memb($Rs32) = clrbit(#$II)", |
| tc_158aa3f7, TypeMAPPING> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L4_iand_memoph_io : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II), |
| "memh($Rs32+#$Ii) = clrbit(#$II)", |
| tc_158aa3f7, TypeV4LDST>, Enc_e66a97 { |
| let Inst{6-5} = 0b10; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b00111111001; |
| let addrMode = BaseImmOffset; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let isRestrictNoSlot1Store = 1; |
| let mayStore = 1; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 0; |
| let opExtentBits = 7; |
| let opExtentAlign = 1; |
| } |
| def L4_iand_memoph_zomap : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, u5_0Imm:$II), |
| "memh($Rs32) = clrbit(#$II)", |
| tc_158aa3f7, TypeMAPPING> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L4_iand_memopw_io : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II), |
| "memw($Rs32+#$Ii) = clrbit(#$II)", |
| tc_158aa3f7, TypeV4LDST>, Enc_84b2cd { |
| let Inst{6-5} = 0b10; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b00111111010; |
| let addrMode = BaseImmOffset; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let isRestrictNoSlot1Store = 1; |
| let mayStore = 1; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 0; |
| let opExtentBits = 8; |
| let opExtentAlign = 2; |
| } |
| def L4_iand_memopw_zomap : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, u5_0Imm:$II), |
| "memw($Rs32) = clrbit(#$II)", |
| tc_158aa3f7, TypeMAPPING> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L4_ior_memopb_io : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II), |
| "memb($Rs32+#$Ii) = setbit(#$II)", |
| tc_158aa3f7, TypeV4LDST>, Enc_46c951 { |
| let Inst{6-5} = 0b11; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b00111111000; |
| let addrMode = BaseImmOffset; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let isRestrictNoSlot1Store = 1; |
| let mayStore = 1; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_ior_memopb_zomap : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, u5_0Imm:$II), |
| "memb($Rs32) = setbit(#$II)", |
| tc_158aa3f7, TypeMAPPING> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L4_ior_memoph_io : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II), |
| "memh($Rs32+#$Ii) = setbit(#$II)", |
| tc_158aa3f7, TypeV4LDST>, Enc_e66a97 { |
| let Inst{6-5} = 0b11; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b00111111001; |
| let addrMode = BaseImmOffset; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let isRestrictNoSlot1Store = 1; |
| let mayStore = 1; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 0; |
| let opExtentBits = 7; |
| let opExtentAlign = 1; |
| } |
| def L4_ior_memoph_zomap : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, u5_0Imm:$II), |
| "memh($Rs32) = setbit(#$II)", |
| tc_158aa3f7, TypeMAPPING> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L4_ior_memopw_io : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II), |
| "memw($Rs32+#$Ii) = setbit(#$II)", |
| tc_158aa3f7, TypeV4LDST>, Enc_84b2cd { |
| let Inst{6-5} = 0b11; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b00111111010; |
| let addrMode = BaseImmOffset; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let isRestrictNoSlot1Store = 1; |
| let mayStore = 1; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 0; |
| let opExtentBits = 8; |
| let opExtentAlign = 2; |
| } |
| def L4_ior_memopw_zomap : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, u5_0Imm:$II), |
| "memw($Rs32) = setbit(#$II)", |
| tc_158aa3f7, TypeMAPPING> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L4_isub_memopb_io : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II), |
| "memb($Rs32+#$Ii) -= #$II", |
| tc_158aa3f7, TypeV4LDST>, Enc_46c951 { |
| let Inst{6-5} = 0b01; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b00111111000; |
| let addrMode = BaseImmOffset; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let isRestrictNoSlot1Store = 1; |
| let mayStore = 1; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_isub_memopb_zomap : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, u5_0Imm:$II), |
| "memb($Rs32) -= #$II", |
| tc_158aa3f7, TypeMAPPING> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L4_isub_memoph_io : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II), |
| "memh($Rs32+#$Ii) -= #$II", |
| tc_158aa3f7, TypeV4LDST>, Enc_e66a97 { |
| let Inst{6-5} = 0b01; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b00111111001; |
| let addrMode = BaseImmOffset; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let isRestrictNoSlot1Store = 1; |
| let mayStore = 1; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 0; |
| let opExtentBits = 7; |
| let opExtentAlign = 1; |
| } |
| def L4_isub_memoph_zomap : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, u5_0Imm:$II), |
| "memh($Rs32) -= #$II", |
| tc_158aa3f7, TypeMAPPING> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L4_isub_memopw_io : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II), |
| "memw($Rs32+#$Ii) -= #$II", |
| tc_158aa3f7, TypeV4LDST>, Enc_84b2cd { |
| let Inst{6-5} = 0b01; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b00111111010; |
| let addrMode = BaseImmOffset; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let isRestrictNoSlot1Store = 1; |
| let mayStore = 1; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 0; |
| let opExtentBits = 8; |
| let opExtentAlign = 2; |
| } |
| def L4_isub_memopw_zomap : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, u5_0Imm:$II), |
| "memw($Rs32) -= #$II", |
| tc_158aa3f7, TypeMAPPING> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L4_loadalignb_ap : HInst< |
| (outs DoubleRegs:$Ryy32, IntRegs:$Re32), |
| (ins DoubleRegs:$Ryy32in, u32_0Imm:$II), |
| "$Ryy32 = memb_fifo($Re32=#$II)", |
| tc_ac65613f, TypeLD>, Enc_f394d3 { |
| let Inst{7-7} = 0b0; |
| let Inst{13-12} = 0b01; |
| let Inst{31-21} = 0b10011010100; |
| let addrMode = AbsoluteSet; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| let Constraints = "$Ryy32 = $Ryy32in"; |
| } |
| def L4_loadalignb_ur : HInst< |
| (outs DoubleRegs:$Ryy32), |
| (ins DoubleRegs:$Ryy32in, IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), |
| "$Ryy32 = memb_fifo($Rt32<<#$Ii+#$II)", |
| tc_a32e03e7, TypeLD>, Enc_04c959 { |
| let Inst{12-12} = 0b1; |
| let Inst{31-21} = 0b10011100100; |
| let addrMode = BaseLongOffset; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let InputType = "imm"; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 4; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| let Constraints = "$Ryy32 = $Ryy32in"; |
| } |
| def L4_loadalignh_ap : HInst< |
| (outs DoubleRegs:$Ryy32, IntRegs:$Re32), |
| (ins DoubleRegs:$Ryy32in, u32_0Imm:$II), |
| "$Ryy32 = memh_fifo($Re32=#$II)", |
| tc_ac65613f, TypeLD>, Enc_f394d3 { |
| let Inst{7-7} = 0b0; |
| let Inst{13-12} = 0b01; |
| let Inst{31-21} = 0b10011010010; |
| let addrMode = AbsoluteSet; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| let Constraints = "$Ryy32 = $Ryy32in"; |
| } |
| def L4_loadalignh_ur : HInst< |
| (outs DoubleRegs:$Ryy32), |
| (ins DoubleRegs:$Ryy32in, IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), |
| "$Ryy32 = memh_fifo($Rt32<<#$Ii+#$II)", |
| tc_a32e03e7, TypeLD>, Enc_04c959 { |
| let Inst{12-12} = 0b1; |
| let Inst{31-21} = 0b10011100010; |
| let addrMode = BaseLongOffset; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let InputType = "imm"; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 4; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| let Constraints = "$Ryy32 = $Ryy32in"; |
| } |
| def L4_loadbsw2_ap : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Re32), |
| (ins u32_0Imm:$II), |
| "$Rd32 = membh($Re32=#$II)", |
| tc_822c3c68, TypeLD>, Enc_323f2d { |
| let Inst{7-7} = 0b0; |
| let Inst{13-12} = 0b01; |
| let Inst{31-21} = 0b10011010001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = AbsoluteSet; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_loadbsw2_ur : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), |
| "$Rd32 = membh($Rt32<<#$Ii+#$II)", |
| tc_abfd9a6d, TypeLD>, Enc_4f677b { |
| let Inst{12-12} = 0b1; |
| let Inst{31-21} = 0b10011100001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseLongOffset; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let InputType = "imm"; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_loadbsw4_ap : HInst< |
| (outs DoubleRegs:$Rdd32, IntRegs:$Re32), |
| (ins u32_0Imm:$II), |
| "$Rdd32 = membh($Re32=#$II)", |
| tc_822c3c68, TypeLD>, Enc_7fa7f6 { |
| let Inst{7-7} = 0b0; |
| let Inst{13-12} = 0b01; |
| let Inst{31-21} = 0b10011010111; |
| let addrMode = AbsoluteSet; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_loadbsw4_ur : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), |
| "$Rdd32 = membh($Rt32<<#$Ii+#$II)", |
| tc_abfd9a6d, TypeLD>, Enc_6185fe { |
| let Inst{12-12} = 0b1; |
| let Inst{31-21} = 0b10011100111; |
| let addrMode = BaseLongOffset; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let InputType = "imm"; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_loadbzw2_ap : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Re32), |
| (ins u32_0Imm:$II), |
| "$Rd32 = memubh($Re32=#$II)", |
| tc_822c3c68, TypeLD>, Enc_323f2d { |
| let Inst{7-7} = 0b0; |
| let Inst{13-12} = 0b01; |
| let Inst{31-21} = 0b10011010011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = AbsoluteSet; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_loadbzw2_ur : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), |
| "$Rd32 = memubh($Rt32<<#$Ii+#$II)", |
| tc_abfd9a6d, TypeLD>, Enc_4f677b { |
| let Inst{12-12} = 0b1; |
| let Inst{31-21} = 0b10011100011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseLongOffset; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let InputType = "imm"; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_loadbzw4_ap : HInst< |
| (outs DoubleRegs:$Rdd32, IntRegs:$Re32), |
| (ins u32_0Imm:$II), |
| "$Rdd32 = memubh($Re32=#$II)", |
| tc_822c3c68, TypeLD>, Enc_7fa7f6 { |
| let Inst{7-7} = 0b0; |
| let Inst{13-12} = 0b01; |
| let Inst{31-21} = 0b10011010101; |
| let addrMode = AbsoluteSet; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_loadbzw4_ur : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), |
| "$Rdd32 = memubh($Rt32<<#$Ii+#$II)", |
| tc_abfd9a6d, TypeLD>, Enc_6185fe { |
| let Inst{12-12} = 0b1; |
| let Inst{31-21} = 0b10011100101; |
| let addrMode = BaseLongOffset; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let InputType = "imm"; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_loadd_aq : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins IntRegs:$Rs32), |
| "$Rdd32 = memd_aq($Rs32)", |
| tc_2471c1c8, TypeLD>, Enc_3a3d62, Requires<[HasV68]> { |
| let Inst{13-5} = 0b011000000; |
| let Inst{31-21} = 0b10010010000; |
| let accessSize = DoubleWordAccess; |
| let mayLoad = 1; |
| } |
| def L4_loadd_locked : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins IntRegs:$Rs32), |
| "$Rdd32 = memd_locked($Rs32)", |
| tc_64b00d8a, TypeLD>, Enc_3a3d62 { |
| let Inst{13-5} = 0b010000000; |
| let Inst{31-21} = 0b10010010000; |
| let accessSize = DoubleWordAccess; |
| let mayLoad = 1; |
| let isSoloAX = 1; |
| } |
| def L4_loadrb_ap : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Re32), |
| (ins u32_0Imm:$II), |
| "$Rd32 = memb($Re32=#$II)", |
| tc_822c3c68, TypeLD>, Enc_323f2d { |
| let Inst{7-7} = 0b0; |
| let Inst{13-12} = 0b01; |
| let Inst{31-21} = 0b10011011000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = AbsoluteSet; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_loadrb_rr : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), |
| "$Rd32 = memb($Rs32+$Rt32<<#$Ii)", |
| tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { |
| let Inst{6-5} = 0b00; |
| let Inst{31-21} = 0b00111010000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseRegOffset; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L4_loadrb_rr"; |
| let CextOpcode = "L2_loadrb"; |
| let InputType = "reg"; |
| let isPredicable = 1; |
| } |
| def L4_loadrb_ur : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), |
| "$Rd32 = memb($Rt32<<#$Ii+#$II)", |
| tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { |
| let Inst{12-12} = 0b1; |
| let Inst{31-21} = 0b10011101000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseLongOffset; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let CextOpcode = "L2_loadrb"; |
| let InputType = "imm"; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_loadrd_ap : HInst< |
| (outs DoubleRegs:$Rdd32, IntRegs:$Re32), |
| (ins u32_0Imm:$II), |
| "$Rdd32 = memd($Re32=#$II)", |
| tc_822c3c68, TypeLD>, Enc_7fa7f6 { |
| let Inst{7-7} = 0b0; |
| let Inst{13-12} = 0b01; |
| let Inst{31-21} = 0b10011011110; |
| let addrMode = AbsoluteSet; |
| let accessSize = DoubleWordAccess; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_loadrd_rr : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), |
| "$Rdd32 = memd($Rs32+$Rt32<<#$Ii)", |
| tc_bf2ffc0f, TypeLD>, Enc_84bff1, AddrModeRel, ImmRegShl { |
| let Inst{6-5} = 0b00; |
| let Inst{31-21} = 0b00111010110; |
| let addrMode = BaseRegOffset; |
| let accessSize = DoubleWordAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L4_loadrd_rr"; |
| let CextOpcode = "L2_loadrd"; |
| let InputType = "reg"; |
| let isPredicable = 1; |
| } |
| def L4_loadrd_ur : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), |
| "$Rdd32 = memd($Rt32<<#$Ii+#$II)", |
| tc_abfd9a6d, TypeLD>, Enc_6185fe, AddrModeRel, ImmRegShl { |
| let Inst{12-12} = 0b1; |
| let Inst{31-21} = 0b10011101110; |
| let addrMode = BaseLongOffset; |
| let accessSize = DoubleWordAccess; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let CextOpcode = "L2_loadrd"; |
| let InputType = "imm"; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_loadrh_ap : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Re32), |
| (ins u32_0Imm:$II), |
| "$Rd32 = memh($Re32=#$II)", |
| tc_822c3c68, TypeLD>, Enc_323f2d { |
| let Inst{7-7} = 0b0; |
| let Inst{13-12} = 0b01; |
| let Inst{31-21} = 0b10011011010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = AbsoluteSet; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_loadrh_rr : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), |
| "$Rd32 = memh($Rs32+$Rt32<<#$Ii)", |
| tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { |
| let Inst{6-5} = 0b00; |
| let Inst{31-21} = 0b00111010010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseRegOffset; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L4_loadrh_rr"; |
| let CextOpcode = "L2_loadrh"; |
| let InputType = "reg"; |
| let isPredicable = 1; |
| } |
| def L4_loadrh_ur : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), |
| "$Rd32 = memh($Rt32<<#$Ii+#$II)", |
| tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { |
| let Inst{12-12} = 0b1; |
| let Inst{31-21} = 0b10011101010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseLongOffset; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let CextOpcode = "L2_loadrh"; |
| let InputType = "imm"; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_loadri_ap : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Re32), |
| (ins u32_0Imm:$II), |
| "$Rd32 = memw($Re32=#$II)", |
| tc_822c3c68, TypeLD>, Enc_323f2d { |
| let Inst{7-7} = 0b0; |
| let Inst{13-12} = 0b01; |
| let Inst{31-21} = 0b10011011100; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = AbsoluteSet; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_loadri_rr : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), |
| "$Rd32 = memw($Rs32+$Rt32<<#$Ii)", |
| tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { |
| let Inst{6-5} = 0b00; |
| let Inst{31-21} = 0b00111010100; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseRegOffset; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L4_loadri_rr"; |
| let CextOpcode = "L2_loadri"; |
| let InputType = "reg"; |
| let isPredicable = 1; |
| } |
| def L4_loadri_ur : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), |
| "$Rd32 = memw($Rt32<<#$Ii+#$II)", |
| tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { |
| let Inst{12-12} = 0b1; |
| let Inst{31-21} = 0b10011101100; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseLongOffset; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let CextOpcode = "L2_loadri"; |
| let InputType = "imm"; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_loadrub_ap : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Re32), |
| (ins u32_0Imm:$II), |
| "$Rd32 = memub($Re32=#$II)", |
| tc_822c3c68, TypeLD>, Enc_323f2d { |
| let Inst{7-7} = 0b0; |
| let Inst{13-12} = 0b01; |
| let Inst{31-21} = 0b10011011001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = AbsoluteSet; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_loadrub_rr : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), |
| "$Rd32 = memub($Rs32+$Rt32<<#$Ii)", |
| tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { |
| let Inst{6-5} = 0b00; |
| let Inst{31-21} = 0b00111010001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseRegOffset; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L4_loadrub_rr"; |
| let CextOpcode = "L2_loadrub"; |
| let InputType = "reg"; |
| let isPredicable = 1; |
| } |
| def L4_loadrub_ur : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), |
| "$Rd32 = memub($Rt32<<#$Ii+#$II)", |
| tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { |
| let Inst{12-12} = 0b1; |
| let Inst{31-21} = 0b10011101001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseLongOffset; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let CextOpcode = "L2_loadrub"; |
| let InputType = "imm"; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_loadruh_ap : HInst< |
| (outs IntRegs:$Rd32, IntRegs:$Re32), |
| (ins u32_0Imm:$II), |
| "$Rd32 = memuh($Re32=#$II)", |
| tc_822c3c68, TypeLD>, Enc_323f2d { |
| let Inst{7-7} = 0b0; |
| let Inst{13-12} = 0b01; |
| let Inst{31-21} = 0b10011011011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = AbsoluteSet; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_loadruh_rr : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), |
| "$Rd32 = memuh($Rs32+$Rt32<<#$Ii)", |
| tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { |
| let Inst{6-5} = 0b00; |
| let Inst{31-21} = 0b00111010011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseRegOffset; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L4_loadruh_rr"; |
| let CextOpcode = "L2_loadruh"; |
| let InputType = "reg"; |
| let isPredicable = 1; |
| } |
| def L4_loadruh_ur : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), |
| "$Rd32 = memuh($Rt32<<#$Ii+#$II)", |
| tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { |
| let Inst{12-12} = 0b1; |
| let Inst{31-21} = 0b10011101011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseLongOffset; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let CextOpcode = "L2_loadruh"; |
| let InputType = "imm"; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_or_memopb_io : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), |
| "memb($Rs32+#$Ii) |= $Rt32", |
| tc_9bcfb2ee, TypeV4LDST>, Enc_d44e31 { |
| let Inst{6-5} = 0b11; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b00111110000; |
| let addrMode = BaseImmOffset; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let isRestrictNoSlot1Store = 1; |
| let mayStore = 1; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_or_memopb_zomap : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "memb($Rs32) |= $Rt32", |
| tc_9bcfb2ee, TypeMAPPING> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L4_or_memoph_io : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), |
| "memh($Rs32+#$Ii) |= $Rt32", |
| tc_9bcfb2ee, TypeV4LDST>, Enc_163a3c { |
| let Inst{6-5} = 0b11; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b00111110001; |
| let addrMode = BaseImmOffset; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let isRestrictNoSlot1Store = 1; |
| let mayStore = 1; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 0; |
| let opExtentBits = 7; |
| let opExtentAlign = 1; |
| } |
| def L4_or_memoph_zomap : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "memh($Rs32) |= $Rt32", |
| tc_9bcfb2ee, TypeMAPPING> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L4_or_memopw_io : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), |
| "memw($Rs32+#$Ii) |= $Rt32", |
| tc_9bcfb2ee, TypeV4LDST>, Enc_226535 { |
| let Inst{6-5} = 0b11; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b00111110010; |
| let addrMode = BaseImmOffset; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let isRestrictNoSlot1Store = 1; |
| let mayStore = 1; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 0; |
| let opExtentBits = 8; |
| let opExtentAlign = 2; |
| } |
| def L4_or_memopw_zomap : HInst< |
| (outs), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "memw($Rs32) |= $Rt32", |
| tc_9bcfb2ee, TypeMAPPING> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def L4_ploadrbf_abs : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, u32_0Imm:$Ii), |
| "if (!$Pt4) $Rd32 = memb(#$Ii)", |
| tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel { |
| let Inst{7-5} = 0b100; |
| let Inst{13-11} = 0b101; |
| let Inst{31-21} = 0b10011111000; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = Absolute; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let BaseOpcode = "L4_loadrb_abs"; |
| let CextOpcode = "L2_loadrb"; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_ploadrbf_rr : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), |
| "if (!$Pv4) $Rd32 = memb($Rs32+$Rt32<<#$Ii)", |
| tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel { |
| let Inst{31-21} = 0b00110001000; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseRegOffset; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L4_loadrb_rr"; |
| let CextOpcode = "L2_loadrb"; |
| let InputType = "reg"; |
| } |
| def L4_ploadrbfnew_abs : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, u32_0Imm:$Ii), |
| "if (!$Pt4.new) $Rd32 = memb(#$Ii)", |
| tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel { |
| let Inst{7-5} = 0b100; |
| let Inst{13-11} = 0b111; |
| let Inst{31-21} = 0b10011111000; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = Absolute; |
| let accessSize = ByteAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let BaseOpcode = "L4_loadrb_abs"; |
| let CextOpcode = "L2_loadrb"; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_ploadrbfnew_rr : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), |
| "if (!$Pv4.new) $Rd32 = memb($Rs32+$Rt32<<#$Ii)", |
| tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel { |
| let Inst{31-21} = 0b00110011000; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseRegOffset; |
| let accessSize = ByteAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let BaseOpcode = "L4_loadrb_rr"; |
| let CextOpcode = "L2_loadrb"; |
| let InputType = "reg"; |
| } |
| def L4_ploadrbt_abs : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, u32_0Imm:$Ii), |
| "if ($Pt4) $Rd32 = memb(#$Ii)", |
| tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel { |
| let Inst{7-5} = 0b100; |
| let Inst{13-11} = 0b100; |
| let Inst{31-21} = 0b10011111000; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = Absolute; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let BaseOpcode = "L4_loadrb_abs"; |
| let CextOpcode = "L2_loadrb"; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_ploadrbt_rr : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), |
| "if ($Pv4) $Rd32 = memb($Rs32+$Rt32<<#$Ii)", |
| tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel { |
| let Inst{31-21} = 0b00110000000; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseRegOffset; |
| let accessSize = ByteAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L4_loadrb_rr"; |
| let CextOpcode = "L2_loadrb"; |
| let InputType = "reg"; |
| } |
| def L4_ploadrbtnew_abs : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, u32_0Imm:$Ii), |
| "if ($Pt4.new) $Rd32 = memb(#$Ii)", |
| tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel { |
| let Inst{7-5} = 0b100; |
| let Inst{13-11} = 0b110; |
| let Inst{31-21} = 0b10011111000; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = Absolute; |
| let accessSize = ByteAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let BaseOpcode = "L4_loadrb_abs"; |
| let CextOpcode = "L2_loadrb"; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_ploadrbtnew_rr : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), |
| "if ($Pv4.new) $Rd32 = memb($Rs32+$Rt32<<#$Ii)", |
| tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel { |
| let Inst{31-21} = 0b00110010000; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseRegOffset; |
| let accessSize = ByteAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let BaseOpcode = "L4_loadrb_rr"; |
| let CextOpcode = "L2_loadrb"; |
| let InputType = "reg"; |
| } |
| def L4_ploadrdf_abs : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins PredRegs:$Pt4, u32_0Imm:$Ii), |
| "if (!$Pt4) $Rdd32 = memd(#$Ii)", |
| tc_7c6d32e4, TypeLD>, Enc_2a7b91, AddrModeRel { |
| let Inst{7-5} = 0b100; |
| let Inst{13-11} = 0b101; |
| let Inst{31-21} = 0b10011111110; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let addrMode = Absolute; |
| let accessSize = DoubleWordAccess; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let BaseOpcode = "L4_loadrd_abs"; |
| let CextOpcode = "L2_loadrd"; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_ploadrdf_rr : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), |
| "if (!$Pv4) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)", |
| tc_45791fb8, TypeLD>, Enc_98c0b8, AddrModeRel { |
| let Inst{31-21} = 0b00110001110; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let addrMode = BaseRegOffset; |
| let accessSize = DoubleWordAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L4_loadrd_rr"; |
| let CextOpcode = "L2_loadrd"; |
| let InputType = "reg"; |
| } |
| def L4_ploadrdfnew_abs : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins PredRegs:$Pt4, u32_0Imm:$Ii), |
| "if (!$Pt4.new) $Rdd32 = memd(#$Ii)", |
| tc_822c3c68, TypeLD>, Enc_2a7b91, AddrModeRel { |
| let Inst{7-5} = 0b100; |
| let Inst{13-11} = 0b111; |
| let Inst{31-21} = 0b10011111110; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let addrMode = Absolute; |
| let accessSize = DoubleWordAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let BaseOpcode = "L4_loadrd_abs"; |
| let CextOpcode = "L2_loadrd"; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_ploadrdfnew_rr : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), |
| "if (!$Pv4.new) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)", |
| tc_b7c4062a, TypeLD>, Enc_98c0b8, AddrModeRel { |
| let Inst{31-21} = 0b00110011110; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let addrMode = BaseRegOffset; |
| let accessSize = DoubleWordAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let BaseOpcode = "L4_loadrd_rr"; |
| let CextOpcode = "L2_loadrd"; |
| let InputType = "reg"; |
| } |
| def L4_ploadrdt_abs : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins PredRegs:$Pt4, u32_0Imm:$Ii), |
| "if ($Pt4) $Rdd32 = memd(#$Ii)", |
| tc_7c6d32e4, TypeLD>, Enc_2a7b91, AddrModeRel { |
| let Inst{7-5} = 0b100; |
| let Inst{13-11} = 0b100; |
| let Inst{31-21} = 0b10011111110; |
| let isPredicated = 1; |
| let addrMode = Absolute; |
| let accessSize = DoubleWordAccess; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let BaseOpcode = "L4_loadrd_abs"; |
| let CextOpcode = "L2_loadrd"; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_ploadrdt_rr : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), |
| "if ($Pv4) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)", |
| tc_45791fb8, TypeLD>, Enc_98c0b8, AddrModeRel { |
| let Inst{31-21} = 0b00110000110; |
| let isPredicated = 1; |
| let addrMode = BaseRegOffset; |
| let accessSize = DoubleWordAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L4_loadrd_rr"; |
| let CextOpcode = "L2_loadrd"; |
| let InputType = "reg"; |
| } |
| def L4_ploadrdtnew_abs : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins PredRegs:$Pt4, u32_0Imm:$Ii), |
| "if ($Pt4.new) $Rdd32 = memd(#$Ii)", |
| tc_822c3c68, TypeLD>, Enc_2a7b91, AddrModeRel { |
| let Inst{7-5} = 0b100; |
| let Inst{13-11} = 0b110; |
| let Inst{31-21} = 0b10011111110; |
| let isPredicated = 1; |
| let addrMode = Absolute; |
| let accessSize = DoubleWordAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let BaseOpcode = "L4_loadrd_abs"; |
| let CextOpcode = "L2_loadrd"; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_ploadrdtnew_rr : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), |
| "if ($Pv4.new) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)", |
| tc_b7c4062a, TypeLD>, Enc_98c0b8, AddrModeRel { |
| let Inst{31-21} = 0b00110010110; |
| let isPredicated = 1; |
| let addrMode = BaseRegOffset; |
| let accessSize = DoubleWordAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let BaseOpcode = "L4_loadrd_rr"; |
| let CextOpcode = "L2_loadrd"; |
| let InputType = "reg"; |
| } |
| def L4_ploadrhf_abs : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, u32_0Imm:$Ii), |
| "if (!$Pt4) $Rd32 = memh(#$Ii)", |
| tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel { |
| let Inst{7-5} = 0b100; |
| let Inst{13-11} = 0b101; |
| let Inst{31-21} = 0b10011111010; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = Absolute; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let BaseOpcode = "L4_loadrh_abs"; |
| let CextOpcode = "L2_loadrh"; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_ploadrhf_rr : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), |
| "if (!$Pv4) $Rd32 = memh($Rs32+$Rt32<<#$Ii)", |
| tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel { |
| let Inst{31-21} = 0b00110001010; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseRegOffset; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L4_loadrh_rr"; |
| let CextOpcode = "L2_loadrh"; |
| let InputType = "reg"; |
| } |
| def L4_ploadrhfnew_abs : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, u32_0Imm:$Ii), |
| "if (!$Pt4.new) $Rd32 = memh(#$Ii)", |
| tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel { |
| let Inst{7-5} = 0b100; |
| let Inst{13-11} = 0b111; |
| let Inst{31-21} = 0b10011111010; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = Absolute; |
| let accessSize = HalfWordAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let BaseOpcode = "L4_loadrh_abs"; |
| let CextOpcode = "L2_loadrh"; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_ploadrhfnew_rr : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), |
| "if (!$Pv4.new) $Rd32 = memh($Rs32+$Rt32<<#$Ii)", |
| tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel { |
| let Inst{31-21} = 0b00110011010; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseRegOffset; |
| let accessSize = HalfWordAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let BaseOpcode = "L4_loadrh_rr"; |
| let CextOpcode = "L2_loadrh"; |
| let InputType = "reg"; |
| } |
| def L4_ploadrht_abs : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, u32_0Imm:$Ii), |
| "if ($Pt4) $Rd32 = memh(#$Ii)", |
| tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel { |
| let Inst{7-5} = 0b100; |
| let Inst{13-11} = 0b100; |
| let Inst{31-21} = 0b10011111010; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = Absolute; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let BaseOpcode = "L4_loadrh_abs"; |
| let CextOpcode = "L2_loadrh"; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_ploadrht_rr : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), |
| "if ($Pv4) $Rd32 = memh($Rs32+$Rt32<<#$Ii)", |
| tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel { |
| let Inst{31-21} = 0b00110000010; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseRegOffset; |
| let accessSize = HalfWordAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L4_loadrh_rr"; |
| let CextOpcode = "L2_loadrh"; |
| let InputType = "reg"; |
| } |
| def L4_ploadrhtnew_abs : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, u32_0Imm:$Ii), |
| "if ($Pt4.new) $Rd32 = memh(#$Ii)", |
| tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel { |
| let Inst{7-5} = 0b100; |
| let Inst{13-11} = 0b110; |
| let Inst{31-21} = 0b10011111010; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = Absolute; |
| let accessSize = HalfWordAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let BaseOpcode = "L4_loadrh_abs"; |
| let CextOpcode = "L2_loadrh"; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_ploadrhtnew_rr : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), |
| "if ($Pv4.new) $Rd32 = memh($Rs32+$Rt32<<#$Ii)", |
| tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel { |
| let Inst{31-21} = 0b00110010010; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseRegOffset; |
| let accessSize = HalfWordAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let BaseOpcode = "L4_loadrh_rr"; |
| let CextOpcode = "L2_loadrh"; |
| let InputType = "reg"; |
| } |
| def L4_ploadrif_abs : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, u32_0Imm:$Ii), |
| "if (!$Pt4) $Rd32 = memw(#$Ii)", |
| tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel { |
| let Inst{7-5} = 0b100; |
| let Inst{13-11} = 0b101; |
| let Inst{31-21} = 0b10011111100; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = Absolute; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let BaseOpcode = "L4_loadri_abs"; |
| let CextOpcode = "L2_loadri"; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_ploadrif_rr : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), |
| "if (!$Pv4) $Rd32 = memw($Rs32+$Rt32<<#$Ii)", |
| tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel { |
| let Inst{31-21} = 0b00110001100; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseRegOffset; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let BaseOpcode = "L4_loadri_rr"; |
| let CextOpcode = "L2_loadri"; |
| let InputType = "reg"; |
| } |
| def L4_ploadrifnew_abs : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, u32_0Imm:$Ii), |
| "if (!$Pt4.new) $Rd32 = memw(#$Ii)", |
| tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel { |
| let Inst{7-5} = 0b100; |
| let Inst{13-11} = 0b111; |
| let Inst{31-21} = 0b10011111100; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = Absolute; |
| let accessSize = WordAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let BaseOpcode = "L4_loadri_abs"; |
| let CextOpcode = "L2_loadri"; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def L4_ploadrifnew_rr : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), |
| "if (!$Pv4.new) $Rd32 = memw($Rs32+$Rt32<<#$Ii)", |
| tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel { |
| let Inst{31-21} = 0b00110011100; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = BaseRegOffset; |
| let accessSize = WordAccess; |
| let isPredicatedNew = 1; |
| let mayLoad = 1; |
| let BaseOpcode = "L4_loadri_rr"; |
| let CextOpcode = "L2_loadri"; |
| let InputType = "reg"; |
| } |
| def L4_ploadrit_abs : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pt4, u32_0Imm:$Ii), |
| "if ($Pt4) $Rd32 = memw(#$Ii)", |
| tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel { |
| let Inst{7-5} = 0b100; |
| let Inst{13-11} = 0b100; |
| let Inst{31-21} = 0b10011111100; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let addrMode = Absolute; |
| let accessSize = WordAccess; |
| let mayLoad = 1; |
| let isExtended = 1; |
| let BaseOpcode = "L4_loadri_abs"; |
| let CextOpcode = "L2_loadri"; |
| let DecoderNamespace = "MustExtend"; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 0; |
|
