llvm/test/CodeGen/Xtensa/cpus.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; This tests that llc accepts all valid Xtensa CPUs

; RUN: llc < %s --mtriple=xtensa --mcpu=esp8266 2>&1 | FileCheck -check-prefix=XTENSA-ESP8266  %s
; RUN: llc < %s --mtriple=xtensa --mcpu=esp32 2>&1 | FileCheck -check-prefix=XTENSA-ESP32 %s
; RUN: llc < %s --mtriple=xtensa --mcpu=generic 2>&1 | FileCheck -check-prefix=XTENSA-GENERIC %s

define i32 @f(i32 %z) {
; XTENSA-ESP8266-LABEL: f:
; XTENSA-ESP8266:         .cfi_startproc
; XTENSA-ESP8266-NEXT:  # %bb.0:
; XTENSA-ESP8266-NEXT:    movi a2, 0
; XTENSA-ESP8266-NEXT:    ret
;
; XTENSA-ESP32-LABEL: f:
; XTENSA-ESP32:         .cfi_startproc
; XTENSA-ESP32-NEXT:  # %bb.0:
; XTENSA-ESP32-NEXT:    entry a1, 32
; XTENSA-ESP32-NEXT:    .cfi_def_cfa_offset 32
; XTENSA-ESP32-NEXT:    movi a2, 0
; XTENSA-ESP32-NEXT:    retw.n
;
; XTENSA-GENERIC-LABEL: f:
; XTENSA-GENERIC:         .cfi_startproc
; XTENSA-GENERIC-NEXT:  # %bb.0:
; XTENSA-GENERIC-NEXT:    movi a2, 0
; XTENSA-GENERIC-NEXT:    ret
  ret i32 0
}