| // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s |
| |
| |
| // ------------------------------------------------------------------------- // |
| // Invalid element size |
| |
| udivr z0.b, p7/m, z0.b, z1.b |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width |
| // CHECK-NEXT: udivr z0.b, p7/m, z0.b, z1.b |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| udivr z0.h, p7/m, z0.h, z1.h |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width |
| // CHECK-NEXT: udivr z0.h, p7/m, z0.h, z1.h |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| |
| // ------------------------------------------------------------------------- // |
| // Tied operands must match |
| |
| udivr z0.s, p7/m, z1.s, z2.s |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register |
| // CHECK-NEXT: udivr z0.s, p7/m, z1.s, z2.s |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| |
| // ------------------------------------------------------------------------- // |
| // Invalid predicate |
| |
| udivr z0.s, p8/m, z0.s, z1.s |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) |
| // CHECK-NEXT: udivr z0.s, p8/m, z0.s, z1.s |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
