| // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s |
| |
| // --------------------------------------------------------------------------// |
| // restricted predicate has range [0, 7]. |
| |
| ldff1b z27.b, p8/z, [x0] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) |
| // CHECK-NEXT: ldff1b z27.b, p8/z, [x0] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ldff1b z9.h, p8/z, [x0] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) |
| // CHECK-NEXT: ldff1b z9.h, p8/z, [x0] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ldff1b z12.s, p8/z, [x0] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) |
| // CHECK-NEXT: ldff1b z12.s, p8/z, [x0] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ldff1b z4.d, p8/z, [x0] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) |
| // CHECK-NEXT: ldff1b z4.d, p8/z, [x0] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| // --------------------------------------------------------------------------// |
| // Invalid scalar + scalar addressing modes |
| |
| ldff1b z0.b, p0/z, [x0, sp] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift |
| // CHECK-NEXT: ldff1b z0.b, p0/z, [x0, sp] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ldff1b z0.b, p0/z, [x0, x0, lsl #1] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift |
| // CHECK-NEXT: ldff1b z0.b, p0/z, [x0, x0, lsl #1] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ldff1b z0.b, p0/z, [x0, w0] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift |
| // CHECK-NEXT: ldff1b z0.b, p0/z, [x0, w0] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ldff1b z0.b, p0/z, [x0, w0, uxtw] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift |
| // CHECK-NEXT: ldff1b z0.b, p0/z, [x0, w0, uxtw] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| // --------------------------------------------------------------------------// |
| // Invalid scalar + vector addressing modes |
| |
| ldff1b z0.d, p0/z, [x0, z0.b] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand |
| // CHECK-NEXT: ldff1b z0.d, p0/z, [x0, z0.b] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ldff1b z0.d, p0/z, [x0, z0.h] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand |
| // CHECK-NEXT: ldff1b z0.d, p0/z, [x0, z0.h] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ldff1b z0.d, p0/z, [x0, z0.s] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand |
| // CHECK-NEXT: ldff1b z0.d, p0/z, [x0, z0.s] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ldff1b z0.s, p0/z, [x0, z0.s] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' |
| // CHECK-NEXT: ldff1b z0.s, p0/z, [x0, z0.s] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ldff1b z0.s, p0/z, [x0, z0.s, uxtw #1] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' |
| // CHECK-NEXT: ldff1b z0.s, p0/z, [x0, z0.s, uxtw #1] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ldff1b z0.s, p0/z, [x0, z0.s, lsl #0] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' |
| // CHECK-NEXT: ldff1b z0.s, p0/z, [x0, z0.s, lsl #0] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ldff1b z0.d, p0/z, [x0, z0.d, lsl #1] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' |
| // CHECK-NEXT: ldff1b z0.d, p0/z, [x0, z0.d, lsl #1] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ldff1b z0.d, p0/z, [x0, z0.d, sxtw #1] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' |
| // CHECK-NEXT: ldff1b z0.d, p0/z, [x0, z0.d, sxtw #1] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| |
| // --------------------------------------------------------------------------// |
| // Invalid vector + immediate addressing modes |
| |
| ldff1b z0.s, p0/z, [z0.s, #-1] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]. |
| // CHECK-NEXT: ldff1b z0.s, p0/z, [z0.s, #-1] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ldff1b z0.s, p0/z, [z0.s, #32] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]. |
| // CHECK-NEXT: ldff1b z0.s, p0/z, [z0.s, #32] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ldff1b z0.d, p0/z, [z0.d, #-1] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]. |
| // CHECK-NEXT: ldff1b z0.d, p0/z, [z0.d, #-1] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| ldff1b z0.d, p0/z, [z0.d, #32] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]. |
| // CHECK-NEXT: ldff1b z0.d, p0/z, [z0.d, #32] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| |
| // --------------------------------------------------------------------------// |
| // Negative tests for instructions that are incompatible with movprfx |
| |
| movprfx z0.d, p0/z, z7.d |
| ldff1b { z0.d }, p0/z, [z0.d] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov |
| // CHECK-NEXT: ldff1b { z0.d }, p0/z, [z0.d] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| movprfx z0, z7 |
| ldff1b { z0.d }, p0/z, [z0.d] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov |
| // CHECK-NEXT: ldff1b { z0.d }, p0/z, [z0.d] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
