| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ |
| ; RUN: --riscv-no-aliases < %s | FileCheck %s |
| declare <vscale x 1 x i8> @llvm.riscv.vrgatherei16.nxv1i8.nxv1i16( |
| <vscale x 1 x i8>, |
| <vscale x 1 x i16>, |
| i64); |
| |
| define <vscale x 1 x i8> @intrinsic_vrgatherei16_vv_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1i8_nxv1i8_nxv1i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu |
| ; CHECK-NEXT: vrgatherei16.vv v25, v8, v9 |
| ; CHECK-NEXT: vmv1r.v v8, v25 |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.nxv1i8.nxv1i16( |
| <vscale x 1 x i8> %0, |
| <vscale x 1 x i16> %1, |
| i64 %2) |
| |
| ret <vscale x 1 x i8> %a |
| } |
| |
| declare <vscale x 1 x i8> @llvm.riscv.vrgatherei16.mask.nxv1i8.nxv1i16( |
| <vscale x 1 x i8>, |
| <vscale x 1 x i8>, |
| <vscale x 1 x i16>, |
| <vscale x 1 x i1>, |
| i64); |
| |
| define <vscale x 1 x i8> @intrinsic_vrgatherei16_mask_vv_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv1i8_nxv1i8_nxv1i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu |
| ; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.mask.nxv1i8.nxv1i16( |
| <vscale x 1 x i8> %0, |
| <vscale x 1 x i8> %1, |
| <vscale x 1 x i16> %2, |
| <vscale x 1 x i1> %3, |
| i64 %4) |
| |
| ret <vscale x 1 x i8> %a |
| } |
| |
| declare <vscale x 2 x i8> @llvm.riscv.vrgatherei16.nxv2i8.nxv2i16( |
| <vscale x 2 x i8>, |
| <vscale x 2 x i16>, |
| i64); |
| |
| define <vscale x 2 x i8> @intrinsic_vrgatherei16_vv_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv2i8_nxv2i8_nxv2i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu |
| ; CHECK-NEXT: vrgatherei16.vv v25, v8, v9 |
| ; CHECK-NEXT: vmv1r.v v8, v25 |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 2 x i8> @llvm.riscv.vrgatherei16.nxv2i8.nxv2i16( |
| <vscale x 2 x i8> %0, |
| <vscale x 2 x i16> %1, |
| i64 %2) |
| |
| ret <vscale x 2 x i8> %a |
| } |
| |
| declare <vscale x 2 x i8> @llvm.riscv.vrgatherei16.mask.nxv2i8.nxv2i16( |
| <vscale x 2 x i8>, |
| <vscale x 2 x i8>, |
| <vscale x 2 x i16>, |
| <vscale x 2 x i1>, |
| i64); |
| |
| define <vscale x 2 x i8> @intrinsic_vrgatherei16_mask_vv_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv2i8_nxv2i8_nxv2i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu |
| ; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 2 x i8> @llvm.riscv.vrgatherei16.mask.nxv2i8.nxv2i16( |
| <vscale x 2 x i8> %0, |
| <vscale x 2 x i8> %1, |
| <vscale x 2 x i16> %2, |
| <vscale x 2 x i1> %3, |
| i64 %4) |
| |
| ret <vscale x 2 x i8> %a |
| } |
| |
| declare <vscale x 4 x i8> @llvm.riscv.vrgatherei16.nxv4i8.nxv4i16( |
| <vscale x 4 x i8>, |
| <vscale x 4 x i16>, |
| i64); |
| |
| define <vscale x 4 x i8> @intrinsic_vrgatherei16_vv_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4i8_nxv4i8_nxv4i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu |
| ; CHECK-NEXT: vrgatherei16.vv v25, v8, v9 |
| ; CHECK-NEXT: vmv1r.v v8, v25 |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 4 x i8> @llvm.riscv.vrgatherei16.nxv4i8.nxv4i16( |
| <vscale x 4 x i8> %0, |
| <vscale x 4 x i16> %1, |
| i64 %2) |
| |
| ret <vscale x 4 x i8> %a |
| } |
| |
| declare <vscale x 4 x i8> @llvm.riscv.vrgatherei16.mask.nxv4i8.nxv4i16( |
| <vscale x 4 x i8>, |
| <vscale x 4 x i8>, |
| <vscale x 4 x i16>, |
| <vscale x 4 x i1>, |
| i64); |
| |
| define <vscale x 4 x i8> @intrinsic_vrgatherei16_mask_vv_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4i8_nxv4i8_nxv4i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu |
| ; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 4 x i8> @llvm.riscv.vrgatherei16.mask.nxv4i8.nxv4i16( |
| <vscale x 4 x i8> %0, |
| <vscale x 4 x i8> %1, |
| <vscale x 4 x i16> %2, |
| <vscale x 4 x i1> %3, |
| i64 %4) |
| |
| ret <vscale x 4 x i8> %a |
| } |
| |
| declare <vscale x 8 x i8> @llvm.riscv.vrgatherei16.nxv8i8.nxv8i16( |
| <vscale x 8 x i8>, |
| <vscale x 8 x i16>, |
| i64); |
| |
| define <vscale x 8 x i8> @intrinsic_vrgatherei16_vv_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8i8_nxv8i8_nxv8i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu |
| ; CHECK-NEXT: vrgatherei16.vv v25, v8, v10 |
| ; CHECK-NEXT: vmv1r.v v8, v25 |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.nxv8i8.nxv8i16( |
| <vscale x 8 x i8> %0, |
| <vscale x 8 x i16> %1, |
| i64 %2) |
| |
| ret <vscale x 8 x i8> %a |
| } |
| |
| declare <vscale x 8 x i8> @llvm.riscv.vrgatherei16.mask.nxv8i8.nxv8i16( |
| <vscale x 8 x i8>, |
| <vscale x 8 x i8>, |
| <vscale x 8 x i16>, |
| <vscale x 8 x i1>, |
| i64); |
| |
| define <vscale x 8 x i8> @intrinsic_vrgatherei16_mask_vv_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8i8_nxv8i8_nxv8i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu |
| ; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.mask.nxv8i8.nxv8i16( |
| <vscale x 8 x i8> %0, |
| <vscale x 8 x i8> %1, |
| <vscale x 8 x i16> %2, |
| <vscale x 8 x i1> %3, |
| i64 %4) |
| |
| ret <vscale x 8 x i8> %a |
| } |
| |
| declare <vscale x 16 x i8> @llvm.riscv.vrgatherei16.nxv16i8.nxv16i16( |
| <vscale x 16 x i8>, |
| <vscale x 16 x i16>, |
| i64); |
| |
| define <vscale x 16 x i8> @intrinsic_vrgatherei16_vv_nxv16i8_nxv16i8_nxv16i16(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, i64 %2) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16i8_nxv16i8_nxv16i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu |
| ; CHECK-NEXT: vrgatherei16.vv v26, v8, v12 |
| ; CHECK-NEXT: vmv2r.v v8, v26 |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 16 x i8> @llvm.riscv.vrgatherei16.nxv16i8.nxv16i16( |
| <vscale x 16 x i8> %0, |
| <vscale x 16 x i16> %1, |
| i64 %2) |
| |
| ret <vscale x 16 x i8> %a |
| } |
| |
| declare <vscale x 16 x i8> @llvm.riscv.vrgatherei16.mask.nxv16i8.nxv16i16( |
| <vscale x 16 x i8>, |
| <vscale x 16 x i8>, |
| <vscale x 16 x i16>, |
| <vscale x 16 x i1>, |
| i64); |
| |
| define <vscale x 16 x i8> @intrinsic_vrgatherei16_mask_vv_nxv16i8_nxv16i8_nxv16i16(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16i8_nxv16i8_nxv16i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu |
| ; CHECK-NEXT: vrgatherei16.vv v8, v10, v12, v0.t |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 16 x i8> @llvm.riscv.vrgatherei16.mask.nxv16i8.nxv16i16( |
| <vscale x 16 x i8> %0, |
| <vscale x 16 x i8> %1, |
| <vscale x 16 x i16> %2, |
| <vscale x 16 x i1> %3, |
| i64 %4) |
| |
| ret <vscale x 16 x i8> %a |
| } |
| |
| declare <vscale x 32 x i8> @llvm.riscv.vrgatherei16.nxv32i8.nxv32i16( |
| <vscale x 32 x i8>, |
| <vscale x 32 x i16>, |
| i64); |
| |
| define <vscale x 32 x i8> @intrinsic_vrgatherei16_vv_nxv32i8_nxv32i8_nxv32i16(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, i64 %2) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv32i8_nxv32i8_nxv32i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu |
| ; CHECK-NEXT: vrgatherei16.vv v28, v8, v16 |
| ; CHECK-NEXT: vmv4r.v v8, v28 |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 32 x i8> @llvm.riscv.vrgatherei16.nxv32i8.nxv32i16( |
| <vscale x 32 x i8> %0, |
| <vscale x 32 x i16> %1, |
| i64 %2) |
| |
| ret <vscale x 32 x i8> %a |
| } |
| |
| declare <vscale x 32 x i8> @llvm.riscv.vrgatherei16.mask.nxv32i8.nxv32i16( |
| <vscale x 32 x i8>, |
| <vscale x 32 x i8>, |
| <vscale x 32 x i16>, |
| <vscale x 32 x i1>, |
| i64); |
| |
| define <vscale x 32 x i8> @intrinsic_vrgatherei16_mask_vv_nxv32i8_nxv32i8_nxv32i16(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv32i8_nxv32i8_nxv32i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu |
| ; CHECK-NEXT: vrgatherei16.vv v8, v12, v16, v0.t |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 32 x i8> @llvm.riscv.vrgatherei16.mask.nxv32i8.nxv32i16( |
| <vscale x 32 x i8> %0, |
| <vscale x 32 x i8> %1, |
| <vscale x 32 x i16> %2, |
| <vscale x 32 x i1> %3, |
| i64 %4) |
| |
| ret <vscale x 32 x i8> %a |
| } |
| |
| declare <vscale x 1 x i16> @llvm.riscv.vrgatherei16.nxv1i16.nxv1i16( |
| <vscale x 1 x i16>, |
| <vscale x 1 x i16>, |
| i64); |
| |
| define <vscale x 1 x i16> @intrinsic_vrgatherei16_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1i16_nxv1i16_nxv1i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu |
| ; CHECK-NEXT: vrgatherei16.vv v25, v8, v9 |
| ; CHECK-NEXT: vmv1r.v v8, v25 |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 1 x i16> @llvm.riscv.vrgatherei16.nxv1i16.nxv1i16( |
| <vscale x 1 x i16> %0, |
| <vscale x 1 x i16> %1, |
| i64 %2) |
| |
| ret <vscale x 1 x i16> %a |
| } |
| |
| declare <vscale x 1 x i16> @llvm.riscv.vrgatherei16.mask.nxv1i16.nxv1i16( |
| <vscale x 1 x i16>, |
| <vscale x 1 x i16>, |
| <vscale x 1 x i16>, |
| <vscale x 1 x i1>, |
| i64); |
| |
| define <vscale x 1 x i16> @intrinsic_vrgatherei16_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv1i16_nxv1i16_nxv1i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu |
| ; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 1 x i16> @llvm.riscv.vrgatherei16.mask.nxv1i16.nxv1i16( |
| <vscale x 1 x i16> %0, |
| <vscale x 1 x i16> %1, |
| <vscale x 1 x i16> %2, |
| <vscale x 1 x i1> %3, |
| i64 %4) |
| |
| ret <vscale x 1 x i16> %a |
| } |
| |
| declare <vscale x 2 x i16> @llvm.riscv.vrgatherei16.nxv2i16.nxv2i16( |
| <vscale x 2 x i16>, |
| <vscale x 2 x i16>, |
| i64); |
| |
| define <vscale x 2 x i16> @intrinsic_vrgatherei16_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv2i16_nxv2i16_nxv2i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu |
| ; CHECK-NEXT: vrgatherei16.vv v25, v8, v9 |
| ; CHECK-NEXT: vmv1r.v v8, v25 |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 2 x i16> @llvm.riscv.vrgatherei16.nxv2i16.nxv2i16( |
| <vscale x 2 x i16> %0, |
| <vscale x 2 x i16> %1, |
| i64 %2) |
| |
| ret <vscale x 2 x i16> %a |
| } |
| |
| declare <vscale x 2 x i16> @llvm.riscv.vrgatherei16.mask.nxv2i16.nxv2i16( |
| <vscale x 2 x i16>, |
| <vscale x 2 x i16>, |
| <vscale x 2 x i16>, |
| <vscale x 2 x i1>, |
| i64); |
| |
| define <vscale x 2 x i16> @intrinsic_vrgatherei16_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv2i16_nxv2i16_nxv2i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu |
| ; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 2 x i16> @llvm.riscv.vrgatherei16.mask.nxv2i16.nxv2i16( |
| <vscale x 2 x i16> %0, |
| <vscale x 2 x i16> %1, |
| <vscale x 2 x i16> %2, |
| <vscale x 2 x i1> %3, |
| i64 %4) |
| |
| ret <vscale x 2 x i16> %a |
| } |
| |
| declare <vscale x 4 x i16> @llvm.riscv.vrgatherei16.nxv4i16.nxv4i16( |
| <vscale x 4 x i16>, |
| <vscale x 4 x i16>, |
| i64); |
| |
| define <vscale x 4 x i16> @intrinsic_vrgatherei16_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4i16_nxv4i16_nxv4i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu |
| ; CHECK-NEXT: vrgatherei16.vv v25, v8, v9 |
| ; CHECK-NEXT: vmv1r.v v8, v25 |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 4 x i16> @llvm.riscv.vrgatherei16.nxv4i16.nxv4i16( |
| <vscale x 4 x i16> %0, |
| <vscale x 4 x i16> %1, |
| i64 %2) |
| |
| ret <vscale x 4 x i16> %a |
| } |
| |
| declare <vscale x 4 x i16> @llvm.riscv.vrgatherei16.mask.nxv4i16.nxv4i16( |
| <vscale x 4 x i16>, |
| <vscale x 4 x i16>, |
| <vscale x 4 x i16>, |
| <vscale x 4 x i1>, |
| i64); |
| |
| define <vscale x 4 x i16> @intrinsic_vrgatherei16_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4i16_nxv4i16_nxv4i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu |
| ; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 4 x i16> @llvm.riscv.vrgatherei16.mask.nxv4i16.nxv4i16( |
| <vscale x 4 x i16> %0, |
| <vscale x 4 x i16> %1, |
| <vscale x 4 x i16> %2, |
| <vscale x 4 x i1> %3, |
| i64 %4) |
| |
| ret <vscale x 4 x i16> %a |
| } |
| |
| declare <vscale x 8 x i16> @llvm.riscv.vrgatherei16.nxv8i16.nxv8i16( |
| <vscale x 8 x i16>, |
| <vscale x 8 x i16>, |
| i64); |
| |
| define <vscale x 8 x i16> @intrinsic_vrgatherei16_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8i16_nxv8i16_nxv8i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu |
| ; CHECK-NEXT: vrgatherei16.vv v26, v8, v10 |
| ; CHECK-NEXT: vmv2r.v v8, v26 |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 8 x i16> @llvm.riscv.vrgatherei16.nxv8i16.nxv8i16( |
| <vscale x 8 x i16> %0, |
| <vscale x 8 x i16> %1, |
| i64 %2) |
| |
| ret <vscale x 8 x i16> %a |
| } |
| |
| declare <vscale x 8 x i16> @llvm.riscv.vrgatherei16.mask.nxv8i16.nxv8i16( |
| <vscale x 8 x i16>, |
| <vscale x 8 x i16>, |
| <vscale x 8 x i16>, |
| <vscale x 8 x i1>, |
| i64); |
| |
| define <vscale x 8 x i16> @intrinsic_vrgatherei16_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8i16_nxv8i16_nxv8i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu |
| ; CHECK-NEXT: vrgatherei16.vv v8, v10, v12, v0.t |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 8 x i16> @llvm.riscv.vrgatherei16.mask.nxv8i16.nxv8i16( |
| <vscale x 8 x i16> %0, |
| <vscale x 8 x i16> %1, |
| <vscale x 8 x i16> %2, |
| <vscale x 8 x i1> %3, |
| i64 %4) |
| |
| ret <vscale x 8 x i16> %a |
| } |
| |
| declare <vscale x 16 x i16> @llvm.riscv.vrgatherei16.nxv16i16.nxv16i16( |
| <vscale x 16 x i16>, |
| <vscale x 16 x i16>, |
| i64); |
| |
| define <vscale x 16 x i16> @intrinsic_vrgatherei16_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16i16_nxv16i16_nxv16i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu |
| ; CHECK-NEXT: vrgatherei16.vv v28, v8, v12 |
| ; CHECK-NEXT: vmv4r.v v8, v28 |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 16 x i16> @llvm.riscv.vrgatherei16.nxv16i16.nxv16i16( |
| <vscale x 16 x i16> %0, |
| <vscale x 16 x i16> %1, |
| i64 %2) |
| |
| ret <vscale x 16 x i16> %a |
| } |
| |
| declare <vscale x 16 x i16> @llvm.riscv.vrgatherei16.mask.nxv16i16.nxv16i16( |
| <vscale x 16 x i16>, |
| <vscale x 16 x i16>, |
| <vscale x 16 x i16>, |
| <vscale x 16 x i1>, |
| i64); |
| |
| define <vscale x 16 x i16> @intrinsic_vrgatherei16_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16i16_nxv16i16_nxv16i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu |
| ; CHECK-NEXT: vrgatherei16.vv v8, v12, v16, v0.t |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 16 x i16> @llvm.riscv.vrgatherei16.mask.nxv16i16.nxv16i16( |
| <vscale x 16 x i16> %0, |
| <vscale x 16 x i16> %1, |
| <vscale x 16 x i16> %2, |
| <vscale x 16 x i1> %3, |
| i64 %4) |
| |
| ret <vscale x 16 x i16> %a |
| } |
| |
| declare <vscale x 32 x i16> @llvm.riscv.vrgatherei16.nxv32i16.nxv32i16( |
| <vscale x 32 x i16>, |
| <vscale x 32 x i16>, |
| i64); |
| |
| define <vscale x 32 x i16> @intrinsic_vrgatherei16_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i64 %2) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv32i16_nxv32i16_nxv32i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu |
| ; CHECK-NEXT: vrgatherei16.vv v24, v8, v16 |
| ; CHECK-NEXT: vmv8r.v v8, v24 |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 32 x i16> @llvm.riscv.vrgatherei16.nxv32i16.nxv32i16( |
| <vscale x 32 x i16> %0, |
| <vscale x 32 x i16> %1, |
| i64 %2) |
| |
| ret <vscale x 32 x i16> %a |
| } |
| |
| declare <vscale x 32 x i16> @llvm.riscv.vrgatherei16.mask.nxv32i16.nxv32i16( |
| <vscale x 32 x i16>, |
| <vscale x 32 x i16>, |
| <vscale x 32 x i16>, |
| <vscale x 32 x i1>, |
| i64); |
| |
| define <vscale x 32 x i16> @intrinsic_vrgatherei16_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv32i16_nxv32i16_nxv32i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu |
| ; CHECK-NEXT: vle16.v v24, (a0) |
| ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu |
| ; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 32 x i16> @llvm.riscv.vrgatherei16.mask.nxv32i16.nxv32i16( |
| <vscale x 32 x i16> %0, |
| <vscale x 32 x i16> %1, |
| <vscale x 32 x i16> %2, |
| <vscale x 32 x i1> %3, |
| i64 %4) |
| |
| ret <vscale x 32 x i16> %a |
| } |
| |
| declare <vscale x 1 x i32> @llvm.riscv.vrgatherei16.nxv1i32.nxv1i16( |
| <vscale x 1 x i32>, |
| <vscale x 1 x i16>, |
| i64); |
| |
| define <vscale x 1 x i32> @intrinsic_vrgatherei16_vv_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i64 %2) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1i32_nxv1i32_nxv1i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu |
| ; CHECK-NEXT: vrgatherei16.vv v25, v8, v9 |
| ; CHECK-NEXT: vmv1r.v v8, v25 |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 1 x i32> @llvm.riscv.vrgatherei16.nxv1i32.nxv1i16( |
| <vscale x 1 x i32> %0, |
| <vscale x 1 x i16> %1, |
| i64 %2) |
| |
| ret <vscale x 1 x i32> %a |
| } |
| |
| declare <vscale x 1 x i32> @llvm.riscv.vrgatherei16.mask.nxv1i32.nxv1i16( |
| <vscale x 1 x i32>, |
| <vscale x 1 x i32>, |
| <vscale x 1 x i16>, |
| <vscale x 1 x i1>, |
| i64); |
| |
| define <vscale x 1 x i32> @intrinsic_vrgatherei16_mask_vv_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv1i32_nxv1i32_nxv1i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu |
| ; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 1 x i32> @llvm.riscv.vrgatherei16.mask.nxv1i32.nxv1i16( |
| <vscale x 1 x i32> %0, |
| <vscale x 1 x i32> %1, |
| <vscale x 1 x i16> %2, |
| <vscale x 1 x i1> %3, |
| i64 %4) |
| |
| ret <vscale x 1 x i32> %a |
| } |
| |
| declare <vscale x 4 x i32> @llvm.riscv.vrgatherei16.nxv4i32.nxv4i16( |
| <vscale x 4 x i32>, |
| <vscale x 4 x i16>, |
| i64); |
| |
| define <vscale x 4 x i32> @intrinsic_vrgatherei16_vv_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i64 %2) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4i32_nxv4i32_nxv4i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu |
| ; CHECK-NEXT: vrgatherei16.vv v26, v8, v10 |
| ; CHECK-NEXT: vmv2r.v v8, v26 |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 4 x i32> @llvm.riscv.vrgatherei16.nxv4i32.nxv4i16( |
| <vscale x 4 x i32> %0, |
| <vscale x 4 x i16> %1, |
| i64 %2) |
| |
| ret <vscale x 4 x i32> %a |
| } |
| |
| declare <vscale x 4 x i32> @llvm.riscv.vrgatherei16.mask.nxv4i32.nxv4i16( |
| <vscale x 4 x i32>, |
| <vscale x 4 x i32>, |
| <vscale x 4 x i16>, |
| <vscale x 4 x i1>, |
| i64); |
| |
| define <vscale x 4 x i32> @intrinsic_vrgatherei16_mask_vv_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4i32_nxv4i32_nxv4i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu |
| ; CHECK-NEXT: vrgatherei16.vv v8, v10, v12, v0.t |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 4 x i32> @llvm.riscv.vrgatherei16.mask.nxv4i32.nxv4i16( |
| <vscale x 4 x i32> %0, |
| <vscale x 4 x i32> %1, |
| <vscale x 4 x i16> %2, |
| <vscale x 4 x i1> %3, |
| i64 %4) |
| |
| ret <vscale x 4 x i32> %a |
| } |
| |
| declare <vscale x 8 x i32> @llvm.riscv.vrgatherei16.nxv8i32.nxv8i16( |
| <vscale x 8 x i32>, |
| <vscale x 8 x i16>, |
| i64); |
| |
| define <vscale x 8 x i32> @intrinsic_vrgatherei16_vv_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, i64 %2) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8i32_nxv8i32_nxv8i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu |
| ; CHECK-NEXT: vrgatherei16.vv v28, v8, v12 |
| ; CHECK-NEXT: vmv4r.v v8, v28 |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 8 x i32> @llvm.riscv.vrgatherei16.nxv8i32.nxv8i16( |
| <vscale x 8 x i32> %0, |
| <vscale x 8 x i16> %1, |
| i64 %2) |
| |
| ret <vscale x 8 x i32> %a |
| } |
| |
| declare <vscale x 8 x i32> @llvm.riscv.vrgatherei16.mask.nxv8i32.nxv8i16( |
| <vscale x 8 x i32>, |
| <vscale x 8 x i32>, |
| <vscale x 8 x i16>, |
| <vscale x 8 x i1>, |
| i64); |
| |
| define <vscale x 8 x i32> @intrinsic_vrgatherei16_mask_vv_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8i32_nxv8i32_nxv8i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu |
| ; CHECK-NEXT: vrgatherei16.vv v8, v12, v16, v0.t |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 8 x i32> @llvm.riscv.vrgatherei16.mask.nxv8i32.nxv8i16( |
| <vscale x 8 x i32> %0, |
| <vscale x 8 x i32> %1, |
| <vscale x 8 x i16> %2, |
| <vscale x 8 x i1> %3, |
| i64 %4) |
| |
| ret <vscale x 8 x i32> %a |
| } |
| |
| declare <vscale x 16 x i32> @llvm.riscv.vrgatherei16.nxv16i32.nxv16i16( |
| <vscale x 16 x i32>, |
| <vscale x 16 x i16>, |
| i64); |
| |
| define <vscale x 16 x i32> @intrinsic_vrgatherei16_vv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, i64 %2) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16i32_nxv16i32_nxv16i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu |
| ; CHECK-NEXT: vrgatherei16.vv v24, v8, v16 |
| ; CHECK-NEXT: vmv8r.v v8, v24 |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 16 x i32> @llvm.riscv.vrgatherei16.nxv16i32.nxv16i16( |
| <vscale x 16 x i32> %0, |
| <vscale x 16 x i16> %1, |
| i64 %2) |
| |
| ret <vscale x 16 x i32> %a |
| } |
| |
| declare <vscale x 16 x i32> @llvm.riscv.vrgatherei16.mask.nxv16i32.nxv16i16( |
| <vscale x 16 x i32>, |
| <vscale x 16 x i32>, |
| <vscale x 16 x i16>, |
| <vscale x 16 x i1>, |
| i64); |
| |
| define <vscale x 16 x i32> @intrinsic_vrgatherei16_mask_vv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16i32_nxv16i32_nxv16i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu |
| ; CHECK-NEXT: vle16.v v28, (a0) |
| ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu |
| ; CHECK-NEXT: vrgatherei16.vv v8, v16, v28, v0.t |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 16 x i32> @llvm.riscv.vrgatherei16.mask.nxv16i32.nxv16i16( |
| <vscale x 16 x i32> %0, |
| <vscale x 16 x i32> %1, |
| <vscale x 16 x i16> %2, |
| <vscale x 16 x i1> %3, |
| i64 %4) |
| |
| ret <vscale x 16 x i32> %a |
| } |
| |
| declare <vscale x 4 x i64> @llvm.riscv.vrgatherei16.nxv4i64.nxv4i16( |
| <vscale x 4 x i64>, |
| <vscale x 4 x i16>, |
| i64); |
| |
| define <vscale x 4 x i64> @intrinsic_vrgatherei16_vv_nxv4i64_nxv4i64_nxv4i16(<vscale x 4 x i64> %0, <vscale x 4 x i16> %1, i64 %2) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4i64_nxv4i64_nxv4i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu |
| ; CHECK-NEXT: vrgatherei16.vv v28, v8, v12 |
| ; CHECK-NEXT: vmv4r.v v8, v28 |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 4 x i64> @llvm.riscv.vrgatherei16.nxv4i64.nxv4i16( |
| <vscale x 4 x i64> %0, |
| <vscale x 4 x i16> %1, |
| i64 %2) |
| |
| ret <vscale x 4 x i64> %a |
| } |
| |
| declare <vscale x 4 x i64> @llvm.riscv.vrgatherei16.mask.nxv4i64.nxv4i16( |
| <vscale x 4 x i64>, |
| <vscale x 4 x i64>, |
| <vscale x 4 x i16>, |
| <vscale x 4 x i1>, |
| i64); |
| |
| define <vscale x 4 x i64> @intrinsic_vrgatherei16_mask_vv_nxv4i64_nxv4i64_nxv4i16(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4i64_nxv4i64_nxv4i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu |
| ; CHECK-NEXT: vrgatherei16.vv v8, v12, v16, v0.t |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 4 x i64> @llvm.riscv.vrgatherei16.mask.nxv4i64.nxv4i16( |
| <vscale x 4 x i64> %0, |
| <vscale x 4 x i64> %1, |
| <vscale x 4 x i16> %2, |
| <vscale x 4 x i1> %3, |
| i64 %4) |
| |
| ret <vscale x 4 x i64> %a |
| } |
| |
| declare <vscale x 8 x i64> @llvm.riscv.vrgatherei16.nxv8i64.nxv8i16( |
| <vscale x 8 x i64>, |
| <vscale x 8 x i16>, |
| i64); |
| |
| define <vscale x 8 x i64> @intrinsic_vrgatherei16_vv_nxv8i64_nxv8i64_nxv8i16(<vscale x 8 x i64> %0, <vscale x 8 x i16> %1, i64 %2) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8i64_nxv8i64_nxv8i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu |
| ; CHECK-NEXT: vrgatherei16.vv v24, v8, v16 |
| ; CHECK-NEXT: vmv8r.v v8, v24 |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 8 x i64> @llvm.riscv.vrgatherei16.nxv8i64.nxv8i16( |
| <vscale x 8 x i64> %0, |
| <vscale x 8 x i16> %1, |
| i64 %2) |
| |
| ret <vscale x 8 x i64> %a |
| } |
| |
| declare <vscale x 8 x i64> @llvm.riscv.vrgatherei16.mask.nxv8i64.nxv8i16( |
| <vscale x 8 x i64>, |
| <vscale x 8 x i64>, |
| <vscale x 8 x i16>, |
| <vscale x 8 x i1>, |
| i64); |
| |
| define <vscale x 8 x i64> @intrinsic_vrgatherei16_mask_vv_nxv8i64_nxv8i64_nxv8i16(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8i64_nxv8i64_nxv8i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a2, zero, e16,m2,ta,mu |
| ; CHECK-NEXT: vle16.v v26, (a0) |
| ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu |
| ; CHECK-NEXT: vrgatherei16.vv v8, v16, v26, v0.t |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 8 x i64> @llvm.riscv.vrgatherei16.mask.nxv8i64.nxv8i16( |
| <vscale x 8 x i64> %0, |
| <vscale x 8 x i64> %1, |
| <vscale x 8 x i16> %2, |
| <vscale x 8 x i1> %3, |
| i64 %4) |
| |
| ret <vscale x 8 x i64> %a |
| } |
| |
| declare <vscale x 1 x half> @llvm.riscv.vrgatherei16.nxv1f16.nxv1i16( |
| <vscale x 1 x half>, |
| <vscale x 1 x i16>, |
| i64); |
| |
| define <vscale x 1 x half> @intrinsic_vrgatherei16_vv_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half> %0, <vscale x 1 x i16> %1, i64 %2) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1f16_nxv1f16_nxv1i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu |
| ; CHECK-NEXT: vrgatherei16.vv v25, v8, v9 |
| ; CHECK-NEXT: vmv1r.v v8, v25 |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 1 x half> @llvm.riscv.vrgatherei16.nxv1f16.nxv1i16( |
| <vscale x 1 x half> %0, |
| <vscale x 1 x i16> %1, |
| i64 %2) |
| |
| ret <vscale x 1 x half> %a |
| } |
| |
| declare <vscale x 1 x half> @llvm.riscv.vrgatherei16.mask.nxv1f16.nxv1i16( |
| <vscale x 1 x half>, |
| <vscale x 1 x half>, |
| <vscale x 1 x i16>, |
| <vscale x 1 x i1>, |
| i64); |
| |
| define <vscale x 1 x half> @intrinsic_vrgatherei16_mask_vv_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv1f16_nxv1f16_nxv1i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu |
| ; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 1 x half> @llvm.riscv.vrgatherei16.mask.nxv1f16.nxv1i16( |
| <vscale x 1 x half> %0, |
| <vscale x 1 x half> %1, |
| <vscale x 1 x i16> %2, |
| <vscale x 1 x i1> %3, |
| i64 %4) |
| |
| ret <vscale x 1 x half> %a |
| } |
| |
| declare <vscale x 2 x half> @llvm.riscv.vrgatherei16.nxv2f16.nxv2i16( |
| <vscale x 2 x half>, |
| <vscale x 2 x i16>, |
| i64); |
| |
| define <vscale x 2 x half> @intrinsic_vrgatherei16_vv_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half> %0, <vscale x 2 x i16> %1, i64 %2) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv2f16_nxv2f16_nxv2i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu |
| ; CHECK-NEXT: vrgatherei16.vv v25, v8, v9 |
| ; CHECK-NEXT: vmv1r.v v8, v25 |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 2 x half> @llvm.riscv.vrgatherei16.nxv2f16.nxv2i16( |
| <vscale x 2 x half> %0, |
| <vscale x 2 x i16> %1, |
| i64 %2) |
| |
| ret <vscale x 2 x half> %a |
| } |
| |
| declare <vscale x 2 x half> @llvm.riscv.vrgatherei16.mask.nxv2f16.nxv2i16( |
| <vscale x 2 x half>, |
| <vscale x 2 x half>, |
| <vscale x 2 x i16>, |
| <vscale x 2 x i1>, |
| i64); |
| |
| define <vscale x 2 x half> @intrinsic_vrgatherei16_mask_vv_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv2f16_nxv2f16_nxv2i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu |
| ; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 2 x half> @llvm.riscv.vrgatherei16.mask.nxv2f16.nxv2i16( |
| <vscale x 2 x half> %0, |
| <vscale x 2 x half> %1, |
| <vscale x 2 x i16> %2, |
| <vscale x 2 x i1> %3, |
| i64 %4) |
| |
| ret <vscale x 2 x half> %a |
| } |
| |
| declare <vscale x 4 x half> @llvm.riscv.vrgatherei16.nxv4f16.nxv4i16( |
| <vscale x 4 x half>, |
| <vscale x 4 x i16>, |
| i64); |
| |
| define <vscale x 4 x half> @intrinsic_vrgatherei16_vv_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half> %0, <vscale x 4 x i16> %1, i64 %2) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4f16_nxv4f16_nxv4i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu |
| ; CHECK-NEXT: vrgatherei16.vv v25, v8, v9 |
| ; CHECK-NEXT: vmv1r.v v8, v25 |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 4 x half> @llvm.riscv.vrgatherei16.nxv4f16.nxv4i16( |
| <vscale x 4 x half> %0, |
| <vscale x 4 x i16> %1, |
| i64 %2) |
| |
| ret <vscale x 4 x half> %a |
| } |
| |
| declare <vscale x 4 x half> @llvm.riscv.vrgatherei16.mask.nxv4f16.nxv4i16( |
| <vscale x 4 x half>, |
| <vscale x 4 x half>, |
| <vscale x 4 x i16>, |
| <vscale x 4 x i1>, |
| i64); |
| |
| define <vscale x 4 x half> @intrinsic_vrgatherei16_mask_vv_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4f16_nxv4f16_nxv4i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu |
| ; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 4 x half> @llvm.riscv.vrgatherei16.mask.nxv4f16.nxv4i16( |
| <vscale x 4 x half> %0, |
| <vscale x 4 x half> %1, |
| <vscale x 4 x i16> %2, |
| <vscale x 4 x i1> %3, |
| i64 %4) |
| |
| ret <vscale x 4 x half> %a |
| } |
| |
| declare <vscale x 8 x half> @llvm.riscv.vrgatherei16.nxv8f16.nxv8i16( |
| <vscale x 8 x half>, |
| <vscale x 8 x i16>, |
| i64); |
| |
| define <vscale x 8 x half> @intrinsic_vrgatherei16_vv_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half> %0, <vscale x 8 x i16> %1, i64 %2) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8f16_nxv8f16_nxv8i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu |
| ; CHECK-NEXT: vrgatherei16.vv v26, v8, v10 |
| ; CHECK-NEXT: vmv2r.v v8, v26 |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 8 x half> @llvm.riscv.vrgatherei16.nxv8f16.nxv8i16( |
| <vscale x 8 x half> %0, |
| <vscale x 8 x i16> %1, |
| i64 %2) |
| |
| ret <vscale x 8 x half> %a |
| } |
| |
| declare <vscale x 8 x half> @llvm.riscv.vrgatherei16.mask.nxv8f16.nxv8i16( |
| <vscale x 8 x half>, |
| <vscale x 8 x half>, |
| <vscale x 8 x i16>, |
| <vscale x 8 x i1>, |
| i64); |
| |
| define <vscale x 8 x half> @intrinsic_vrgatherei16_mask_vv_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8f16_nxv8f16_nxv8i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu |
| ; CHECK-NEXT: vrgatherei16.vv v8, v10, v12, v0.t |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 8 x half> @llvm.riscv.vrgatherei16.mask.nxv8f16.nxv8i16( |
| <vscale x 8 x half> %0, |
| <vscale x 8 x half> %1, |
| <vscale x 8 x i16> %2, |
| <vscale x 8 x i1> %3, |
| i64 %4) |
| |
| ret <vscale x 8 x half> %a |
| } |
| |
| declare <vscale x 16 x half> @llvm.riscv.vrgatherei16.nxv16f16.nxv16i16( |
| <vscale x 16 x half>, |
| <vscale x 16 x i16>, |
| i64); |
| |
| define <vscale x 16 x half> @intrinsic_vrgatherei16_vv_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half> %0, <vscale x 16 x i16> %1, i64 %2) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16f16_nxv16f16_nxv16i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu |
| ; CHECK-NEXT: vrgatherei16.vv v28, v8, v12 |
| ; CHECK-NEXT: vmv4r.v v8, v28 |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 16 x half> @llvm.riscv.vrgatherei16.nxv16f16.nxv16i16( |
| <vscale x 16 x half> %0, |
| <vscale x 16 x i16> %1, |
| i64 %2) |
| |
| ret <vscale x 16 x half> %a |
| } |
| |
| declare <vscale x 16 x half> @llvm.riscv.vrgatherei16.mask.nxv16f16.nxv16i16( |
| <vscale x 16 x half>, |
| <vscale x 16 x half>, |
| <vscale x 16 x i16>, |
| <vscale x 16 x i1>, |
| i64); |
| |
| define <vscale x 16 x half> @intrinsic_vrgatherei16_mask_vv_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16f16_nxv16f16_nxv16i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu |
| ; CHECK-NEXT: vrgatherei16.vv v8, v12, v16, v0.t |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 16 x half> @llvm.riscv.vrgatherei16.mask.nxv16f16.nxv16i16( |
| <vscale x 16 x half> %0, |
| <vscale x 16 x half> %1, |
| <vscale x 16 x i16> %2, |
| <vscale x 16 x i1> %3, |
| i64 %4) |
| |
| ret <vscale x 16 x half> %a |
| } |
| |
| declare <vscale x 32 x half> @llvm.riscv.vrgatherei16.nxv32f16.nxv32i16( |
| <vscale x 32 x half>, |
| <vscale x 32 x i16>, |
| i64); |
| |
| define <vscale x 32 x half> @intrinsic_vrgatherei16_vv_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, <vscale x 32 x i16> %1, i64 %2) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv32f16_nxv32f16_nxv32i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu |
| ; CHECK-NEXT: vrgatherei16.vv v24, v8, v16 |
| ; CHECK-NEXT: vmv8r.v v8, v24 |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.nxv32f16.nxv32i16( |
| <vscale x 32 x half> %0, |
| <vscale x 32 x i16> %1, |
| i64 %2) |
| |
| ret <vscale x 32 x half> %a |
| } |
| |
| declare <vscale x 32 x half> @llvm.riscv.vrgatherei16.mask.nxv32f16.nxv32i16( |
| <vscale x 32 x half>, |
| <vscale x 32 x half>, |
| <vscale x 32 x i16>, |
| <vscale x 32 x i1>, |
| i64); |
| |
| define <vscale x 32 x half> @intrinsic_vrgatherei16_mask_vv_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv32f16_nxv32f16_nxv32i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu |
| ; CHECK-NEXT: vle16.v v24, (a0) |
| ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu |
| ; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.mask.nxv32f16.nxv32i16( |
| <vscale x 32 x half> %0, |
| <vscale x 32 x half> %1, |
| <vscale x 32 x i16> %2, |
| <vscale x 32 x i1> %3, |
| i64 %4) |
| |
| ret <vscale x 32 x half> %a |
| } |
| |
| declare <vscale x 1 x float> @llvm.riscv.vrgatherei16.nxv1f32.nxv1i16( |
| <vscale x 1 x float>, |
| <vscale x 1 x i16>, |
| i64); |
| |
| define <vscale x 1 x float> @intrinsic_vrgatherei16_vv_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float> %0, <vscale x 1 x i16> %1, i64 %2) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1f32_nxv1f32_nxv1i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu |
| ; CHECK-NEXT: vrgatherei16.vv v25, v8, v9 |
| ; CHECK-NEXT: vmv1r.v v8, v25 |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.nxv1f32.nxv1i16( |
| <vscale x 1 x float> %0, |
| <vscale x 1 x i16> %1, |
| i64 %2) |
| |
| ret <vscale x 1 x float> %a |
| } |
| |
| declare <vscale x 1 x float> @llvm.riscv.vrgatherei16.mask.nxv1f32.nxv1i16( |
| <vscale x 1 x float>, |
| <vscale x 1 x float>, |
| <vscale x 1 x i16>, |
| <vscale x 1 x i1>, |
| i64); |
| |
| define <vscale x 1 x float> @intrinsic_vrgatherei16_mask_vv_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv1f32_nxv1f32_nxv1i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu |
| ; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.mask.nxv1f32.nxv1i16( |
| <vscale x 1 x float> %0, |
| <vscale x 1 x float> %1, |
| <vscale x 1 x i16> %2, |
| <vscale x 1 x i1> %3, |
| i64 %4) |
| |
| ret <vscale x 1 x float> %a |
| } |
| |
| declare <vscale x 4 x float> @llvm.riscv.vrgatherei16.nxv4f32.nxv4i16( |
| <vscale x 4 x float>, |
| <vscale x 4 x i16>, |
| i64); |
| |
| define <vscale x 4 x float> @intrinsic_vrgatherei16_vv_nxv4f32_nxv4f32_nxv4i16(<vscale x 4 x float> %0, <vscale x 4 x i16> %1, i64 %2) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4f32_nxv4f32_nxv4i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu |
| ; CHECK-NEXT: vrgatherei16.vv v26, v8, v10 |
| ; CHECK-NEXT: vmv2r.v v8, v26 |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 4 x float> @llvm.riscv.vrgatherei16.nxv4f32.nxv4i16( |
| <vscale x 4 x float> %0, |
| <vscale x 4 x i16> %1, |
| i64 %2) |
| |
| ret <vscale x 4 x float> %a |
| } |
| |
| declare <vscale x 4 x float> @llvm.riscv.vrgatherei16.mask.nxv4f32.nxv4i16( |
| <vscale x 4 x float>, |
| <vscale x 4 x float>, |
| <vscale x 4 x i16>, |
| <vscale x 4 x i1>, |
| i64); |
| |
| define <vscale x 4 x float> @intrinsic_vrgatherei16_mask_vv_nxv4f32_nxv4f32_nxv4i16(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4f32_nxv4f32_nxv4i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu |
| ; CHECK-NEXT: vrgatherei16.vv v8, v10, v12, v0.t |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 4 x float> @llvm.riscv.vrgatherei16.mask.nxv4f32.nxv4i16( |
| <vscale x 4 x float> %0, |
| <vscale x 4 x float> %1, |
| <vscale x 4 x i16> %2, |
| <vscale x 4 x i1> %3, |
| i64 %4) |
| |
| ret <vscale x 4 x float> %a |
| } |
| |
| declare <vscale x 8 x float> @llvm.riscv.vrgatherei16.nxv8f32.nxv8i16( |
| <vscale x 8 x float>, |
| <vscale x 8 x i16>, |
| i64); |
| |
| define <vscale x 8 x float> @intrinsic_vrgatherei16_vv_nxv8f32_nxv8f32_nxv8i16(<vscale x 8 x float> %0, <vscale x 8 x i16> %1, i64 %2) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8f32_nxv8f32_nxv8i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu |
| ; CHECK-NEXT: vrgatherei16.vv v28, v8, v12 |
| ; CHECK-NEXT: vmv4r.v v8, v28 |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 8 x float> @llvm.riscv.vrgatherei16.nxv8f32.nxv8i16( |
| <vscale x 8 x float> %0, |
| <vscale x 8 x i16> %1, |
| i64 %2) |
| |
| ret <vscale x 8 x float> %a |
| } |
| |
| declare <vscale x 8 x float> @llvm.riscv.vrgatherei16.mask.nxv8f32.nxv8i16( |
| <vscale x 8 x float>, |
| <vscale x 8 x float>, |
| <vscale x 8 x i16>, |
| <vscale x 8 x i1>, |
| i64); |
| |
| define <vscale x 8 x float> @intrinsic_vrgatherei16_mask_vv_nxv8f32_nxv8f32_nxv8i16(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8f32_nxv8f32_nxv8i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu |
| ; CHECK-NEXT: vrgatherei16.vv v8, v12, v16, v0.t |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 8 x float> @llvm.riscv.vrgatherei16.mask.nxv8f32.nxv8i16( |
| <vscale x 8 x float> %0, |
| <vscale x 8 x float> %1, |
| <vscale x 8 x i16> %2, |
| <vscale x 8 x i1> %3, |
| i64 %4) |
| |
| ret <vscale x 8 x float> %a |
| } |
| |
| declare <vscale x 16 x float> @llvm.riscv.vrgatherei16.nxv16f32.nxv16i16( |
| <vscale x 16 x float>, |
| <vscale x 16 x i16>, |
| i64); |
| |
| define <vscale x 16 x float> @intrinsic_vrgatherei16_vv_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float> %0, <vscale x 16 x i16> %1, i64 %2) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16f32_nxv16f32_nxv16i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu |
| ; CHECK-NEXT: vrgatherei16.vv v24, v8, v16 |
| ; CHECK-NEXT: vmv8r.v v8, v24 |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 16 x float> @llvm.riscv.vrgatherei16.nxv16f32.nxv16i16( |
| <vscale x 16 x float> %0, |
| <vscale x 16 x i16> %1, |
| i64 %2) |
| |
| ret <vscale x 16 x float> %a |
| } |
| |
| declare <vscale x 16 x float> @llvm.riscv.vrgatherei16.mask.nxv16f32.nxv16i16( |
| <vscale x 16 x float>, |
| <vscale x 16 x float>, |
| <vscale x 16 x i16>, |
| <vscale x 16 x i1>, |
| i64); |
| |
| define <vscale x 16 x float> @intrinsic_vrgatherei16_mask_vv_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16f32_nxv16f32_nxv16i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu |
| ; CHECK-NEXT: vle16.v v28, (a0) |
| ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu |
| ; CHECK-NEXT: vrgatherei16.vv v8, v16, v28, v0.t |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 16 x float> @llvm.riscv.vrgatherei16.mask.nxv16f32.nxv16i16( |
| <vscale x 16 x float> %0, |
| <vscale x 16 x float> %1, |
| <vscale x 16 x i16> %2, |
| <vscale x 16 x i1> %3, |
| i64 %4) |
| |
| ret <vscale x 16 x float> %a |
| } |
| |
| declare <vscale x 4 x double> @llvm.riscv.vrgatherei16.nxv4f64.nxv4i16( |
| <vscale x 4 x double>, |
| <vscale x 4 x i16>, |
| i64); |
| |
| define <vscale x 4 x double> @intrinsic_vrgatherei16_vv_nxv4f64_nxv4f64_nxv4i16(<vscale x 4 x double> %0, <vscale x 4 x i16> %1, i64 %2) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4f64_nxv4f64_nxv4i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu |
| ; CHECK-NEXT: vrgatherei16.vv v28, v8, v12 |
| ; CHECK-NEXT: vmv4r.v v8, v28 |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 4 x double> @llvm.riscv.vrgatherei16.nxv4f64.nxv4i16( |
| <vscale x 4 x double> %0, |
| <vscale x 4 x i16> %1, |
| i64 %2) |
| |
| ret <vscale x 4 x double> %a |
| } |
| |
| declare <vscale x 4 x double> @llvm.riscv.vrgatherei16.mask.nxv4f64.nxv4i16( |
| <vscale x 4 x double>, |
| <vscale x 4 x double>, |
| <vscale x 4 x i16>, |
| <vscale x 4 x i1>, |
| i64); |
| |
| define <vscale x 4 x double> @intrinsic_vrgatherei16_mask_vv_nxv4f64_nxv4f64_nxv4i16(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4f64_nxv4f64_nxv4i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu |
| ; CHECK-NEXT: vrgatherei16.vv v8, v12, v16, v0.t |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 4 x double> @llvm.riscv.vrgatherei16.mask.nxv4f64.nxv4i16( |
| <vscale x 4 x double> %0, |
| <vscale x 4 x double> %1, |
| <vscale x 4 x i16> %2, |
| <vscale x 4 x i1> %3, |
| i64 %4) |
| |
| ret <vscale x 4 x double> %a |
| } |
| |
| declare <vscale x 8 x double> @llvm.riscv.vrgatherei16.nxv8f64.nxv8i16( |
| <vscale x 8 x double>, |
| <vscale x 8 x i16>, |
| i64); |
| |
| define <vscale x 8 x double> @intrinsic_vrgatherei16_vv_nxv8f64_nxv8f64_nxv8i16(<vscale x 8 x double> %0, <vscale x 8 x i16> %1, i64 %2) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8f64_nxv8f64_nxv8i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu |
| ; CHECK-NEXT: vrgatherei16.vv v24, v8, v16 |
| ; CHECK-NEXT: vmv8r.v v8, v24 |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 8 x double> @llvm.riscv.vrgatherei16.nxv8f64.nxv8i16( |
| <vscale x 8 x double> %0, |
| <vscale x 8 x i16> %1, |
| i64 %2) |
| |
| ret <vscale x 8 x double> %a |
| } |
| |
| declare <vscale x 8 x double> @llvm.riscv.vrgatherei16.mask.nxv8f64.nxv8i16( |
| <vscale x 8 x double>, |
| <vscale x 8 x double>, |
| <vscale x 8 x i16>, |
| <vscale x 8 x i1>, |
| i64); |
| |
| define <vscale x 8 x double> @intrinsic_vrgatherei16_mask_vv_nxv8f64_nxv8f64_nxv8i16(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { |
| ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8f64_nxv8f64_nxv8i16: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vsetvli a2, zero, e16,m2,ta,mu |
| ; CHECK-NEXT: vle16.v v26, (a0) |
| ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu |
| ; CHECK-NEXT: vrgatherei16.vv v8, v16, v26, v0.t |
| ; CHECK-NEXT: jalr zero, 0(ra) |
| entry: |
| %a = call <vscale x 8 x double> @llvm.riscv.vrgatherei16.mask.nxv8f64.nxv8i16( |
| <vscale x 8 x double> %0, |
| <vscale x 8 x double> %1, |
| <vscale x 8 x i16> %2, |
| <vscale x 8 x i1> %3, |
| i64 %4) |
| |
| ret <vscale x 8 x double> %a |
| } |