llvm/test/CodeGen/X86/combine-fmin.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=SSE
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=sandybridge | FileCheck %s --check-prefixes=AVX
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=AVX
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX

define <4 x double> @concat_fmin_v4f64_v2f64(<2 x double> %a0, <2 x double> %a1) {
; SSE-LABEL: concat_fmin_v4f64_v2f64:
; SSE:       # %bb.0:
; SSE-NEXT:    xorpd %xmm2, %xmm2
; SSE-NEXT:    minpd %xmm2, %xmm0
; SSE-NEXT:    minpd %xmm2, %xmm1
; SSE-NEXT:    retq
;
; AVX-LABEL: concat_fmin_v4f64_v2f64:
; AVX:       # %bb.0:
; AVX-NEXT:    # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX-NEXT:    vxorpd %xmm1, %xmm1, %xmm1
; AVX-NEXT:    vminpd %ymm1, %ymm0, %ymm0
; AVX-NEXT:    retq
  %v0 = call <2 x double> @llvm.x86.sse2.min.pd(<2 x double> %a0, <2 x double> zeroinitializer)
  %v1 = call <2 x double> @llvm.x86.sse2.min.pd(<2 x double> %a1, <2 x double> zeroinitializer)
  %res  = shufflevector <2 x double> %v0, <2 x double> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  ret <4 x double> %res
}

define <8 x float> @concat_fmin_v8f32_v4f32(<4 x float> %a0, <4 x float> %a1) {
; SSE-LABEL: concat_fmin_v8f32_v4f32:
; SSE:       # %bb.0:
; SSE-NEXT:    xorps %xmm2, %xmm2
; SSE-NEXT:    minps %xmm2, %xmm0
; SSE-NEXT:    minps %xmm2, %xmm1
; SSE-NEXT:    retq
;
; AVX-LABEL: concat_fmin_v8f32_v4f32:
; AVX:       # %bb.0:
; AVX-NEXT:    # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX-NEXT:    vxorps %xmm1, %xmm1, %xmm1
; AVX-NEXT:    vminps %ymm1, %ymm0, %ymm0
; AVX-NEXT:    retq
  %v0 = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> %a0, <4 x float> zeroinitializer)
  %v1 = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> %a1, <4 x float> zeroinitializer)
  %res  = shufflevector <4 x float> %v0, <4 x float> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
  ret <8 x float> %res
}