llvm/test/CodeGen/X86/avx10_2_512fptosi_satcvtds.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-linux -mattr=+avx10.2 | FileCheck %s --check-prefixes=CHECK,X86
; RUN: llc < %s -mtriple=x86_64-linux -mattr=+avx10.2 | FileCheck %s --check-prefixes=CHECK,X64

; VCVTTPD2DQS
define <8 x i24> @test_signed_v8i24_v8f64(<8 x double> %f) nounwind {
; X86-LABEL: test_signed_v8i24_v8f64:
; X86:       # %bb.0:
; X86-NEXT:    vcvttpd2dqs %zmm0, %ymm0
; X86-NEXT:    vpmaxsd {{\.?LCPI[0-9]+_[0-9]+}}{1to8}, %ymm0, %ymm0
; X86-NEXT:    vpminsd {{\.?LCPI[0-9]+_[0-9]+}}{1to8}, %ymm0, %ymm0
; X86-NEXT:    retl
;
; X64-LABEL: test_signed_v8i24_v8f64:
; X64:       # %bb.0:
; X64-NEXT:    vcvttpd2dqs %zmm0, %ymm0
; X64-NEXT:    vpmaxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
; X64-NEXT:    vpminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
; X64-NEXT:    retq
  %x = call  <8 x i24> @llvm.fptosi.sat.v8i24.v8f64(<8 x double> %f)
  ret <8 x i24> %x
}

define <8 x i32> @test_signed_v8i32_v8f64(<8 x double> %f) nounwind {
; CHECK-LABEL: test_signed_v8i32_v8f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vcvttpd2dqs %zmm0, %ymm0
; CHECK-NEXT:    ret{{[l|q]}}
  %x = call  <8 x i32> @llvm.fptosi.sat.v8i32.v8f64(<8 x double> %f)
  ret <8 x i32> %x
}

; VCVTTPD2QQS
define <8 x i48> @test_signed_v8i48_v8f64(<8 x double> %f) nounwind {
; X86-LABEL: test_signed_v8i48_v8f64:
; X86:       # %bb.0:
; X86-NEXT:    vcvttpd2qqs %zmm0, %zmm0
; X86-NEXT:    vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}{1to8}, %zmm0, %zmm0
; X86-NEXT:    vpminsq {{\.?LCPI[0-9]+_[0-9]+}}{1to8}, %zmm0, %zmm0
; X86-NEXT:    retl
;
; X64-LABEL: test_signed_v8i48_v8f64:
; X64:       # %bb.0:
; X64-NEXT:    vcvttpd2qqs %zmm0, %zmm0
; X64-NEXT:    vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; X64-NEXT:    vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; X64-NEXT:    retq
  %x = call <8 x i48> @llvm.fptosi.sat.v8i48.v8f64(<8 x double> %f)
  ret <8 x i48> %x
}

define <8 x i64> @test_signed_v8i64_v8f64(<8 x double> %f) nounwind {
; CHECK-LABEL: test_signed_v8i64_v8f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vcvttpd2qqs %zmm0, %zmm0
; CHECK-NEXT:    ret{{[l|q]}}
  %x = call <8 x i64> @llvm.fptosi.sat.v8i64.v8f64(<8 x double> %f)
  ret <8 x i64> %x
}

; VCVTTPD2UDQS
define <8 x i24> @test_unsigned_v8i24_v8f64(<8 x double> %f) nounwind {
; X86-LABEL: test_unsigned_v8i24_v8f64:
; X86:       # %bb.0:
; X86-NEXT:    vcvttpd2udqs %zmm0, %ymm0
; X86-NEXT:    vpminud {{\.?LCPI[0-9]+_[0-9]+}}{1to8}, %ymm0, %ymm0
; X86-NEXT:    retl
;
; X64-LABEL: test_unsigned_v8i24_v8f64:
; X64:       # %bb.0:
; X64-NEXT:    vcvttpd2udqs %zmm0, %ymm0
; X64-NEXT:    vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
; X64-NEXT:    retq
  %x = call  <8 x i24> @llvm.fptoui.sat.v8i24.v8f64(<8 x double> %f)
 ret <8 x i24> %x
}

define <8 x i32> @test_unsigned_v8i32_v8f64(<8 x double> %f) nounwind {
; CHECK-LABEL: test_unsigned_v8i32_v8f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vcvttpd2udqs %zmm0, %ymm0
; CHECK-NEXT:    ret{{[l|q]}}
  %x = call  <8 x i32> @llvm.fptoui.sat.v8i32.v8f64(<8 x double> %f)
 ret <8 x i32> %x
}

; VCVTTPD2UQQS
define <8 x i48> @test_unsigned_v8i48_v8f64(<8 x double> %f) nounwind {
; X86-LABEL: test_unsigned_v8i48_v8f64:
; X86:       # %bb.0:
; X86-NEXT:    vcvttpd2uqqs %zmm0, %zmm0
; X86-NEXT:    vpminuq {{\.?LCPI[0-9]+_[0-9]+}}{1to8}, %zmm0, %zmm0
; X86-NEXT:    retl
;
; X64-LABEL: test_unsigned_v8i48_v8f64:
; X64:       # %bb.0:
; X64-NEXT:    vcvttpd2uqqs %zmm0, %zmm0
; X64-NEXT:    vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; X64-NEXT:    retq
  %x = call  <8 x i48> @llvm.fptoui.sat.v8i48.v8f64(<8 x double> %f)
  ret <8 x i48> %x
}

define <8 x i64> @test_unsigned_v8i64_v8f64(<8 x double> %f) nounwind {
; CHECK-LABEL: test_unsigned_v8i64_v8f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vcvttpd2uqqs %zmm0, %zmm0
; CHECK-NEXT:    ret{{[l|q]}}
  %x = call  <8 x i64> @llvm.fptoui.sat.v8i64.v8f64(<8 x double> %f)
  ret <8 x i64> %x
}

; VCVTTPS2DQS
define <16 x i24> @test_signed_v16i24_v16f32(<16 x float> %f) nounwind {
; X86-LABEL: test_signed_v16i24_v16f32:
; X86:       # %bb.0:
; X86-NEXT:    vcvttps2dqs %zmm0, %zmm0
; X86-NEXT:    vpmaxsd {{\.?LCPI[0-9]+_[0-9]+}}{1to16}, %zmm0, %zmm0
; X86-NEXT:    vpminsd {{\.?LCPI[0-9]+_[0-9]+}}{1to16}, %zmm0, %zmm0
; X86-NEXT:    retl
;
; X64-LABEL: test_signed_v16i24_v16f32:
; X64:       # %bb.0:
; X64-NEXT:    vcvttps2dqs %zmm0, %zmm0
; X64-NEXT:    vpmaxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; X64-NEXT:    vpminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; X64-NEXT:    retq
  %x = call  <16 x i24> @llvm.fptosi.sat.v16i24.v16f32(<16 x float> %f)
  ret <16 x i24> %x
}

define <16 x i32> @test_signed_v16i32_v16f32(<16 x float> %f) nounwind {
; CHECK-LABEL: test_signed_v16i32_v16f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vcvttps2dqs %zmm0, %zmm0
; CHECK-NEXT:    ret{{[l|q]}}
  %x = call  <16 x i32> @llvm.fptosi.sat.v16i32.v16f32(<16 x float> %f)
  ret <16 x i32> %x
}

; VCVTTPS2UDQS
define <16 x i24> @test_unsigned_v16i24_v16f32(<16 x float> %f) nounwind {
; X86-LABEL: test_unsigned_v16i24_v16f32:
; X86:       # %bb.0:
; X86-NEXT:    vcvttps2udqs %zmm0, %zmm0
; X86-NEXT:    vpminud {{\.?LCPI[0-9]+_[0-9]+}}{1to16}, %zmm0, %zmm0
; X86-NEXT:    retl
;
; X64-LABEL: test_unsigned_v16i24_v16f32:
; X64:       # %bb.0:
; X64-NEXT:    vcvttps2udqs %zmm0, %zmm0
; X64-NEXT:    vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
; X64-NEXT:    retq
  %x = call  <16 x i24> @llvm.fptoui.sat.v16i24.v16f32(<16 x float> %f)
  ret <16 x i24> %x
}

define <16 x i32> @test_unsigned_v16i32_v16f32(<16 x float> %f) nounwind {
; CHECK-LABEL: test_unsigned_v16i32_v16f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vcvttps2udqs %zmm0, %zmm0
; CHECK-NEXT:    ret{{[l|q]}}
  %x = call  <16 x i32> @llvm.fptoui.sat.v16i32.v16f32(<16 x float> %f)
  ret <16 x i32> %x
}

; VCVTTPS2QQS
define <8 x i48> @test_signed_v8i48_v8f32(<8 x float> %f) nounwind {
; X86-LABEL: test_signed_v8i48_v8f32:
; X86:       # %bb.0:
; X86-NEXT:    vcvttps2qqs %ymm0, %zmm0
; X86-NEXT:    vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}{1to8}, %zmm0, %zmm0
; X86-NEXT:    vpminsq {{\.?LCPI[0-9]+_[0-9]+}}{1to8}, %zmm0, %zmm0
; X86-NEXT:    retl
;
; X64-LABEL: test_signed_v8i48_v8f32:
; X64:       # %bb.0:
; X64-NEXT:    vcvttps2qqs %ymm0, %zmm0
; X64-NEXT:    vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; X64-NEXT:    vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; X64-NEXT:    retq
  %x = call  <8 x i48> @llvm.fptosi.sat.v8i48.v8f32(<8 x float> %f)
  ret <8 x i48> %x
}

define <8 x i64> @test_signed_v8i64_v8f32(<8 x float> %f) nounwind {
; CHECK-LABEL: test_signed_v8i64_v8f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vcvttps2qqs %ymm0, %zmm0
; CHECK-NEXT:    ret{{[l|q]}}
  %x = call  <8 x i64> @llvm.fptosi.sat.v8i64.v8f32(<8 x float> %f)
  ret <8 x i64> %x
}

; VCVTTPS2UQQS
define <8 x i48> @test_unsigned_v8i48_v8f32(<8 x float> %f) nounwind {
; X86-LABEL: test_unsigned_v8i48_v8f32:
; X86:       # %bb.0:
; X86-NEXT:    vcvttps2uqqs %ymm0, %zmm0
; X86-NEXT:    vpminuq {{\.?LCPI[0-9]+_[0-9]+}}{1to8}, %zmm0, %zmm0
; X86-NEXT:    retl
;
; X64-LABEL: test_unsigned_v8i48_v8f32:
; X64:       # %bb.0:
; X64-NEXT:    vcvttps2uqqs %ymm0, %zmm0
; X64-NEXT:    vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0
; X64-NEXT:    retq
  %x = call  <8 x i48> @llvm.fptoui.sat.v8i48.v8f32(<8 x float> %f)
  ret <8 x i48> %x
}

define <8 x i64> @test_unsigned_v8i64_v8f32(<8 x float> %f) nounwind {
; CHECK-LABEL: test_unsigned_v8i64_v8f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vcvttps2uqqs %ymm0, %zmm0
; CHECK-NEXT:    ret{{[l|q]}}
  %x = call  <8 x i64> @llvm.fptoui.sat.v8i64.v8f32(<8 x float> %f)
  ret <8 x i64> %x
}

; VCVTTBF162IUBS
define <32 x i8> @test_unsigned_v32i8_v32bf16(<32 x bfloat> %f) nounwind {
; CHECK-LABEL: test_unsigned_v32i8_v32bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vcvttbf162iubs %zmm0, %zmm0
; CHECK-NEXT:    vpmovwb %zmm0, %ymm0
; CHECK-NEXT:    ret{{[l|q]}}
  %x = call  <32 x i8> @llvm.fptoui.sat.v32i8.v32bf16(<32 x bfloat> %f)
  ret <32 x i8> %x
}

; VCVTTBF162IBS
define <32 x i8> @test_signed_v32i8_v32bf16(<32 x bfloat> %f) nounwind {
; CHECK-LABEL: test_signed_v32i8_v32bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vcvttbf162ibs %zmm0, %zmm0
; CHECK-NEXT:    vpmovwb %zmm0, %ymm0
; CHECK-NEXT:    ret{{[l|q]}}
  %x = call  <32 x i8> @llvm.fptosi.sat.v32i8.v32bf16(<32 x bfloat> %f)
  ret <32 x i8> %x
}