llvm/test/CodeGen/AMDGPU/machine-sink-loop-var-out-of-divergent-loop-swdev407790.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 < %s | FileCheck %s

; A VGPR loop variable was incorrectly sunk into a flow block, past
; the si_end_cf reconvergence point.

define void @machinesink_loop_variable_out_of_divergent_loop(i32 %arg, i1 %cmp49280.not, i32 %arg1, i1 %cmp108) {
; CHECK-LABEL: machinesink_loop_variable_out_of_divergent_loop:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_and_b32_e32 v1, 1, v1
; CHECK-NEXT:    v_and_b32_e32 v3, 1, v3
; CHECK-NEXT:    s_mov_b32 s5, 0
; CHECK-NEXT:    v_cmp_eq_u32_e64 s4, 1, v1
; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v3
; CHECK-NEXT:    s_xor_b32 s6, s4, -1
; CHECK-NEXT:    s_inst_prefetch 0x1
; CHECK-NEXT:    s_branch .LBB0_3
; CHECK-NEXT:    .p2align 6
; CHECK-NEXT:  .LBB0_1: ; %Flow
; CHECK-NEXT:    ; in Loop: Header=BB0_3 Depth=1
; CHECK-NEXT:    s_or_b32 exec_lo, exec_lo, s8
; CHECK-NEXT:    v_add_nc_u32_e32 v3, -4, v3
; CHECK-NEXT:  .LBB0_2: ; %Flow1
; CHECK-NEXT:    ; in Loop: Header=BB0_3 Depth=1
; CHECK-NEXT:    s_or_b32 exec_lo, exec_lo, s7
; CHECK-NEXT:    v_cmp_ne_u32_e64 s4, 0, v1
; CHECK-NEXT:    ;;#ASMSTART
; CHECK-NEXT:    ; j lastloop entry
; CHECK-NEXT:    ;;#ASMEND
; CHECK-NEXT:    s_or_b32 s5, s4, s5
; CHECK-NEXT:    s_andn2_b32 exec_lo, exec_lo, s5
; CHECK-NEXT:    s_cbranch_execz .LBB0_8
; CHECK-NEXT:  .LBB0_3: ; %for.body33
; CHECK-NEXT:    ; =>This Loop Header: Depth=1
; CHECK-NEXT:    ; Child Loop BB0_6 Depth 2
; CHECK-NEXT:    v_mov_b32_e32 v3, 0
; CHECK-NEXT:    v_mov_b32_e32 v1, 0
; CHECK-NEXT:    s_and_saveexec_b32 s7, s6
; CHECK-NEXT:    s_cbranch_execz .LBB0_2
; CHECK-NEXT:  ; %bb.4: ; %for.body51.preheader
; CHECK-NEXT:    ; in Loop: Header=BB0_3 Depth=1
; CHECK-NEXT:    s_mov_b32 s8, 0
; CHECK-NEXT:    s_mov_b32 s9, 0
; CHECK-NEXT:    s_branch .LBB0_6
; CHECK-NEXT:    .p2align 6
; CHECK-NEXT:  .LBB0_5: ; %if.end118
; CHECK-NEXT:    ; in Loop: Header=BB0_6 Depth=2
; CHECK-NEXT:    s_or_b32 exec_lo, exec_lo, s4
; CHECK-NEXT:    s_add_i32 s9, s9, 4
; CHECK-NEXT:    ;;#ASMSTART
; CHECK-NEXT:    ; backedge
; CHECK-NEXT:    ;;#ASMEND
; CHECK-NEXT:    v_add_nc_u32_e32 v3, s9, v2
; CHECK-NEXT:    v_cmp_ge_u32_e64 s4, v3, v0
; CHECK-NEXT:    s_or_b32 s8, s4, s8
; CHECK-NEXT:    s_andn2_b32 exec_lo, exec_lo, s8
; CHECK-NEXT:    s_cbranch_execz .LBB0_1
; CHECK-NEXT:  .LBB0_6: ; %for.body51
; CHECK-NEXT:    ; Parent Loop BB0_3 Depth=1
; CHECK-NEXT:    ; => This Inner Loop Header: Depth=2
; CHECK-NEXT:    v_mov_b32_e32 v1, 1
; CHECK-NEXT:    s_and_saveexec_b32 s4, vcc_lo
; CHECK-NEXT:    s_cbranch_execz .LBB0_5
; CHECK-NEXT:  ; %bb.7: ; %if.then112
; CHECK-NEXT:    ; in Loop: Header=BB0_6 Depth=2
; CHECK-NEXT:    s_add_i32 s10, s9, 4
; CHECK-NEXT:    v_mov_b32_e32 v1, 0
; CHECK-NEXT:    v_mov_b32_e32 v3, s10
; CHECK-NEXT:    ds_write_b32 v1, v3
; CHECK-NEXT:    s_branch .LBB0_5
; CHECK-NEXT:  .LBB0_8: ; %for.body159.preheader
; CHECK-NEXT:    s_inst_prefetch 0x2
; CHECK-NEXT:    s_or_b32 exec_lo, exec_lo, s5
; CHECK-NEXT:    s_mov_b32 vcc_lo, exec_lo
; CHECK-NEXT:  .LBB0_9: ; %for.body159
; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT:    s_cbranch_vccnz .LBB0_9
; CHECK-NEXT:  ; %bb.10: ; %DummyReturnBlock
; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
; CHECK-NEXT:    s_setpc_b64 s[30:31]
entry:
  br label %for.body33

for.body33:                                       ; preds = %for.end121, %entry
  br i1 %cmp49280.not, label %for.end121, label %for.body51

for.body51:                                       ; preds = %if.end118, %for.body33
  %add48284 = phi i32 [ %add48, %if.end118 ], [ %arg1, %for.body33 ]
  %collision.0281 = phi i32 [ %inc119, %if.end118 ], [ 1, %for.body33 ]
  br i1 %cmp108, label %if.then112, label %if.end118

if.then112:                                       ; preds = %for.body51
  %inc101 = add i32 %collision.0281, 3
  store i32 %inc101, ptr addrspace(3) null, align 2147483648
  br label %if.end118

if.end118:                                        ; preds = %if.then112, %for.body51
  %thCollNum.5 = phi i32 [ 0, %if.then112 ], [ 1, %for.body51 ]
  %inc119 = add i32 %collision.0281, 4
  tail call void asm sideeffect "; backedge", ""()
  %add48 = add i32 %add48284, 4
  %cmp49 = icmp ult i32 %add48, %arg
  br i1 %cmp49, label %for.body51, label %for.end121

for.end121:                                       ; preds = %if.end118, %for.body33
  %thCollNum.1.lcssa = phi i32 [ 0, %for.body33 ], [ %thCollNum.5, %if.end118 ]
  %j.0.lcssa = phi i32 [ 0, %for.body33 ], [ %add48284, %if.end118 ]
  %i5 = tail call i32 asm sideeffect "; j lastloop entry", "=v,0"(i32 %j.0.lcssa)
  %cmp31 = icmp eq i32 %thCollNum.1.lcssa, 0
  br i1 %cmp31, label %for.body33, label %for.body159

for.body159:                                      ; preds = %for.body159, %for.end121
  br label %for.body159
}