| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 |
| ; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck %s |
| |
| define amdgpu_cs <2 x i32> @f() { |
| ; CHECK-LABEL: f: |
| ; CHECK: ; %bb.0: ; %bb |
| ; CHECK-NEXT: s_mov_b32 s4, 0 |
| ; CHECK-NEXT: s_mov_b32 s1, 0 |
| ; CHECK-NEXT: s_mov_b32 s5, s4 |
| ; CHECK-NEXT: s_mov_b32 s6, s4 |
| ; CHECK-NEXT: s_mov_b32 s7, s4 |
| ; CHECK-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 0 |
| ; CHECK-NEXT: s_waitcnt vmcnt(0) |
| ; CHECK-NEXT: v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1] |
| ; CHECK-NEXT: v_mov_b32_e32 v1, s4 |
| ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo |
| ; CHECK-NEXT: v_readfirstlane_b32 s0, v0 |
| ; CHECK-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 |
| ; CHECK-NEXT: ; return to shader part epilog |
| bb: |
| %i = call <2 x i32> @llvm.amdgcn.raw.buffer.load.v2i32(<4 x i32> zeroinitializer, i32 0, i32 0, i32 0) |
| %i1 = bitcast <2 x i32> %i to i64 |
| %i2 = insertelement <3 x i64> zeroinitializer, i64 %i1, i64 2 |
| %i3 = icmp ne <3 x i64> %i2, zeroinitializer |
| %i4 = zext <3 x i1> %i3 to <3 x i64> |
| %i5 = bitcast <3 x i64> %i4 to <6 x i32> |
| %i6 = shufflevector <6 x i32> %i5, <6 x i32> zeroinitializer, <2 x i32> <i32 4, i32 5> |
| call void @llvm.amdgcn.raw.buffer.store.v2i32(<2 x i32> %i6, <4 x i32> zeroinitializer, i32 0, i32 0, i32 0) |
| ret <2 x i32> %i6 |
| } |
| |
| declare <2 x i32> @llvm.amdgcn.raw.buffer.load.v2i32(<4 x i32>, i32, i32, i32 immarg) |
| declare void @llvm.amdgcn.raw.buffer.store.v2i32(<2 x i32>, <4 x i32>, i32, i32, i32 immarg) |