llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cmpb-32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
; RUN:   --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s

define i64 @test_cmpb(i64 %a, i64 %b) {
; CHECK-LABEL: test_cmpb:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    cmpb r4, r4, r6
; CHECK-NEXT:    cmpb r3, r3, r5
; CHECK-NEXT:    blr
entry:
  %0 = trunc i64 %a to i32
  %1 = trunc i64 %b to i32
  %2 = lshr i64 %a, 32
  %3 = trunc i64 %2 to i32
  %4 = lshr i64 %b, 32
  %5 = trunc i64 %4 to i32
  %cmpb = tail call i32 @llvm.ppc.cmpb.i32.i32.i32(i32 %0, i32 %1)
  %6 = zext i32 %cmpb to i64
  %cmpb1 = tail call i32 @llvm.ppc.cmpb.i32.i32.i32(i32 %3, i32 %5)
  %7 = zext i32 %cmpb1 to i64
  %8 = shl nuw i64 %7, 32
  %9 = or i64 %8, %6
  ret i64 %9
}

declare i32 @llvm.ppc.cmpb.i32.i32.i32(i32, i32)