llvm/test/CodeGen/Mips/GlobalISel/legalizer/cttz.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
---
name:            cttz_i32
alignment:       4
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0

    ; MIPS32-LABEL: name: cttz_i32
    ; MIPS32: liveins: $a0
    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
    ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C]]
    ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C]]
    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]]
    ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
    ; MIPS32: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
    ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[CTLZ]]
    ; MIPS32: $v0 = COPY [[SUB]](s32)
    ; MIPS32: RetRA implicit $v0
    %0:_(s32) = COPY $a0
    %1:_(s32) = G_CTTZ %0(s32)
    $v0 = COPY %1(s32)
    RetRA implicit $v0

...
---
name:            cttz_i64
alignment:       4
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1

    ; MIPS32-LABEL: name: cttz_i64
    ; MIPS32: liveins: $a0, $a1
    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
    ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
    ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[C1]]
    ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[C1]]
    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]]
    ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
    ; MIPS32: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
    ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[CTLZ]]
    ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[SUB]], [[C2]]
    ; MIPS32: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C1]]
    ; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]]
    ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR1]], [[ADD2]]
    ; MIPS32: [[CTLZ1:%[0-9]+]]:_(s32) = G_CTLZ [[AND1]](s32)
    ; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[CTLZ1]]
    ; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
    ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C3]]
    ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[ADD1]], [[SUB1]]
    ; MIPS32: $v0 = COPY [[SELECT]](s32)
    ; MIPS32: $v1 = COPY [[C]](s32)
    ; MIPS32: RetRA implicit $v0, implicit $v1
    %1:_(s32) = COPY $a0
    %2:_(s32) = COPY $a1
    %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
    %3:_(s64) = G_CTTZ %0(s64)
    %4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64)
    $v0 = COPY %4(s32)
    $v1 = COPY %5(s32)
    RetRA implicit $v0, implicit $v1

...
---
name:            ffs_i32_expansion
alignment:       4
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0

    ; MIPS32-LABEL: name: ffs_i32_expansion
    ; MIPS32: liveins: $a0
    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
    ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
    ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C2]]
    ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C2]]
    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]]
    ; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
    ; MIPS32: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
    ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[CTLZ]]
    ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = nuw nsw G_ADD [[SUB]], [[C]]
    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C1]]
    ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
    ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[C1]], [[ADD1]]
    ; MIPS32: $v0 = COPY [[SELECT]](s32)
    ; MIPS32: RetRA implicit $v0
    %0:_(s32) = COPY $a0
    %2:_(s32) = G_CONSTANT i32 1
    %4:_(s32) = G_CONSTANT i32 0
    %1:_(s32) = G_CTTZ_ZERO_UNDEF %0(s32)
    %3:_(s32) = nuw nsw G_ADD %1, %2
    %5:_(s1) = G_ICMP intpred(eq), %0(s32), %4
    %6:_(s32) = G_SELECT %5(s1), %4, %3
    $v0 = COPY %6(s32)
    RetRA implicit $v0

...
---
name:            ffs_i64_expansion
alignment:       4
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1

    ; MIPS32-LABEL: name: ffs_i64_expansion
    ; MIPS32: liveins: $a0, $a1
    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
    ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C1]](s32), [[C1]](s32)
    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C1]]
    ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
    ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[C2]]
    ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[C2]]
    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]]
    ; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
    ; MIPS32: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
    ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[CTLZ]]
    ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[SUB]], [[C3]]
    ; MIPS32: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C2]]
    ; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C2]]
    ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR1]], [[ADD2]]
    ; MIPS32: [[CTLZ1:%[0-9]+]]:_(s32) = G_CTLZ [[AND1]](s32)
    ; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[CTLZ1]]
    ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
    ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[ADD1]], [[SUB1]]
    ; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[SELECT]], [[C]]
    ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[C]]
    ; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[C1]], [[C1]]
    ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
    ; MIPS32: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[ADD4]], [[AND3]]
    ; MIPS32: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ADD3]](s32), [[ADD5]](s32)
    ; MIPS32: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C1]]
    ; MIPS32: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[C1]]
    ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[XOR2]], [[XOR3]]
    ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s32), [[C1]]
    ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ICMP2]], [[C]]
    ; MIPS32: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND4]](s32), [[MV]], [[MV1]]
    ; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SELECT1]](s64)
    ; MIPS32: $v0 = COPY [[UV]](s32)
    ; MIPS32: $v1 = COPY [[UV1]](s32)
    ; MIPS32: RetRA implicit $v0, implicit $v1
    %1:_(s32) = COPY $a0
    %2:_(s32) = COPY $a1
    %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
    %4:_(s64) = G_CONSTANT i64 1
    %6:_(s64) = G_CONSTANT i64 0
    %3:_(s64) = G_CTTZ_ZERO_UNDEF %0(s64)
    %5:_(s64) = nuw nsw G_ADD %3, %4
    %7:_(s1) = G_ICMP intpred(eq), %0(s64), %6
    %8:_(s64) = G_SELECT %7(s1), %6, %5
    %9:_(s32), %10:_(s32) = G_UNMERGE_VALUES %8(s64)
    $v0 = COPY %9(s32)
    $v1 = COPY %10(s32)
    RetRA implicit $v0, implicit $v1

...