llvm/test/CodeGen/Mips/GlobalISel/instruction-select/store_4_unaligned_r6.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R6
--- |

  @float_align1 = common global float 0.000000e+00, align 1
  @float_align8 = common global float 0.000000e+00, align 8
  @i32_align2 = common global i32 0, align 2

  define void @store_float_align1(float %a) #0 {
  entry:
    store float %a, float* @float_align1, align 1
    ret void
  }

  define void @store_float_align8(float %a) #0 {
  entry:
    store float %a, float* @float_align8, align 8
    ret void
  }

  define void @store_i32_align2(i32 signext %a) #0 {
  entry:
    store i32 %a, i32* @i32_align2, align 2
    ret void
  }

...
---
name:            store_float_align1
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $f12

    ; MIPS32R6-LABEL: name: store_float_align1
    ; MIPS32R6: liveins: $f12
    ; MIPS32R6: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; MIPS32R6: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align1
    ; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align1
    ; MIPS32R6: SWC1 [[COPY]], [[ADDiu]], 0 :: (store (s32) into @float_align1, align 1)
    ; MIPS32R6: RetRA
    %0:fprb(s32) = COPY $f12
    %1:gprb(p0) = G_GLOBAL_VALUE @float_align1
    G_STORE %0(s32), %1(p0) :: (store (s32) into @float_align1, align 1)
    RetRA

...
---
name:            store_float_align8
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $f12

    ; MIPS32R6-LABEL: name: store_float_align8
    ; MIPS32R6: liveins: $f12
    ; MIPS32R6: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; MIPS32R6: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align8
    ; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align8
    ; MIPS32R6: SWC1 [[COPY]], [[ADDiu]], 0 :: (store (s32) into @float_align8, align 8)
    ; MIPS32R6: RetRA
    %0:fprb(s32) = COPY $f12
    %1:gprb(p0) = G_GLOBAL_VALUE @float_align8
    G_STORE %0(s32), %1(p0) :: (store (s32) into @float_align8, align 8)
    RetRA

...
---
name:            store_i32_align2
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0

    ; MIPS32R6-LABEL: name: store_i32_align2
    ; MIPS32R6: liveins: $a0
    ; MIPS32R6: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
    ; MIPS32R6: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @i32_align2
    ; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @i32_align2
    ; MIPS32R6: SW [[COPY]], [[ADDiu]], 0 :: (store (s32) into @i32_align2, align 2)
    ; MIPS32R6: RetRA
    %0:gprb(s32) = COPY $a0
    %1:gprb(p0) = G_GLOBAL_VALUE @i32_align2
    G_STORE %0(s32), %1(p0) :: (store (s32) into @i32_align2, align 2)
    RetRA

...