[PowerPC] Implement Vector Insert Builtins in LLVM/Clang
Implements vec_insertl() and vec_inserth().
Differential Revision: https://reviews.llvm.org/D82365
diff --git a/clang/include/clang/Basic/BuiltinsPPC.def b/clang/include/clang/Basic/BuiltinsPPC.def
index 856c862..d0df5fc 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -320,6 +320,22 @@
BUILTIN(__builtin_altivec_vsldbi, "V16UcV16UcV16UcIi", "")
BUILTIN(__builtin_altivec_vsrdbi, "V16UcV16UcV16UcIi", "")
+// P10 Vector Insert built-ins.
+BUILTIN(__builtin_altivec_vinsblx, "V16UcV16UcULLiULLi", "")
+BUILTIN(__builtin_altivec_vinsbrx, "V16UcV16UcULLiULLi", "")
+BUILTIN(__builtin_altivec_vinshlx, "V8UsV8UsULLiULLi", "")
+BUILTIN(__builtin_altivec_vinshrx, "V8UsV8UsULLiULLi", "")
+BUILTIN(__builtin_altivec_vinswlx, "V4UiV4UiULLiULLi", "")
+BUILTIN(__builtin_altivec_vinswrx, "V4UiV4UiULLiULLi", "")
+BUILTIN(__builtin_altivec_vinsdlx, "V2ULLiV2ULLiULLiULLi", "")
+BUILTIN(__builtin_altivec_vinsdrx, "V2ULLiV2ULLiULLiULLi", "")
+BUILTIN(__builtin_altivec_vinsbvlx, "V16UcV16UcULLiV16Uc", "")
+BUILTIN(__builtin_altivec_vinsbvrx, "V16UcV16UcULLiV16Uc", "")
+BUILTIN(__builtin_altivec_vinshvlx, "V8UsV8UsULLiV8Us", "")
+BUILTIN(__builtin_altivec_vinshvrx, "V8UsV8UsULLiV8Us", "")
+BUILTIN(__builtin_altivec_vinswvlx, "V4UiV4UiULLiV4Ui", "")
+BUILTIN(__builtin_altivec_vinswvrx, "V4UiV4UiULLiV4Ui", "")
+
// VSX built-ins.
BUILTIN(__builtin_vsx_lxvd2x, "V2divC*", "")
diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index 39eebb7..38d5c00 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -16889,6 +16889,136 @@
#define vec_srdb(__a, __b, __c) __builtin_altivec_vsrdbi(__a, __b, (__c & 0x7))
+/* vec_insertl */
+
+static __inline__ vector unsigned char __ATTRS_o_ai
+vec_insertl(unsigned char __a, vector unsigned char __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+ return __builtin_altivec_vinsbrx(__b, __c, __a);
+#else
+ return __builtin_altivec_vinsblx(__b, __c, __a);
+#endif
+}
+
+static __inline__ vector unsigned short __ATTRS_o_ai
+vec_insertl(unsigned short __a, vector unsigned short __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+ return __builtin_altivec_vinshrx(__b, __c, __a);
+#else
+ return __builtin_altivec_vinshlx(__b, __c, __a);
+#endif
+}
+
+static __inline__ vector unsigned int __ATTRS_o_ai
+vec_insertl(unsigned int __a, vector unsigned int __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+ return __builtin_altivec_vinswrx(__b, __c, __a);
+#else
+ return __builtin_altivec_vinswlx(__b, __c, __a);
+#endif
+}
+
+static __inline__ vector unsigned long long __ATTRS_o_ai vec_insertl(
+ unsigned long long __a, vector unsigned long long __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+ return __builtin_altivec_vinsdrx(__b, __c, __a);
+#else
+ return __builtin_altivec_vinsdlx(__b, __c, __a);
+#endif
+}
+
+static __inline__ vector unsigned char __ATTRS_o_ai vec_insertl(
+ vector unsigned char __a, vector unsigned char __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+ return __builtin_altivec_vinsbvrx(__b, __c, __a);
+#else
+ return __builtin_altivec_vinsbvlx(__b, __c, __a);
+#endif
+}
+
+static __inline__ vector unsigned short __ATTRS_o_ai vec_insertl(
+ vector unsigned short __a, vector unsigned short __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+ return __builtin_altivec_vinshvrx(__b, __c, __a);
+#else
+ return __builtin_altivec_vinshvlx(__b, __c, __a);
+#endif
+}
+
+static __inline__ vector unsigned int __ATTRS_o_ai vec_insertl(
+ vector unsigned int __a, vector unsigned int __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+ return __builtin_altivec_vinswvrx(__b, __c, __a);
+#else
+ return __builtin_altivec_vinswvlx(__b, __c, __a);
+#endif
+}
+
+/* vec_inserth */
+
+static __inline__ vector unsigned char __ATTRS_o_ai
+vec_inserth(unsigned char __a, vector unsigned char __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+ return __builtin_altivec_vinsblx(__b, __c, __a);
+#else
+ return __builtin_altivec_vinsbrx(__b, __c, __a);
+#endif
+}
+
+static __inline__ vector unsigned short __ATTRS_o_ai
+vec_inserth(unsigned short __a, vector unsigned short __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+ return __builtin_altivec_vinshlx(__b, __c, __a);
+#else
+ return __builtin_altivec_vinshrx(__b, __c, __a);
+#endif
+}
+
+static __inline__ vector unsigned int __ATTRS_o_ai
+vec_inserth(unsigned int __a, vector unsigned int __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+ return __builtin_altivec_vinswlx(__b, __c, __a);
+#else
+ return __builtin_altivec_vinswrx(__b, __c, __a);
+#endif
+}
+
+static __inline__ vector unsigned long long __ATTRS_o_ai vec_inserth(
+ unsigned long long __a, vector unsigned long long __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+ return __builtin_altivec_vinsdlx(__b, __c, __a);
+#else
+ return __builtin_altivec_vinsdrx(__b, __c, __a);
+#endif
+}
+
+static __inline__ vector unsigned char __ATTRS_o_ai vec_inserth(
+ vector unsigned char __a, vector unsigned char __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+ return __builtin_altivec_vinsbvlx(__b, __c, __a);
+#else
+ return __builtin_altivec_vinsbvrx(__b, __c, __a);
+#endif
+}
+
+static __inline__ vector unsigned short __ATTRS_o_ai vec_inserth(
+ vector unsigned short __a, vector unsigned short __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+ return __builtin_altivec_vinshvlx(__b, __c, __a);
+#else
+ return __builtin_altivec_vinshvrx(__b, __c, __a);
+#endif
+}
+
+static __inline__ vector unsigned int __ATTRS_o_ai vec_inserth(
+ vector unsigned int __a, vector unsigned int __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+ return __builtin_altivec_vinswvlx(__b, __c, __a);
+#else
+ return __builtin_altivec_vinswvrx(__b, __c, __a);
+#endif
+}
+
#ifdef __VSX__
/* vec_permx */
diff --git a/clang/test/CodeGen/builtins-ppc-p10vector.c b/clang/test/CodeGen/builtins-ppc-p10vector.c
index 51f1028..b0602dd 100644
--- a/clang/test/CodeGen/builtins-ppc-p10vector.c
+++ b/clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -3,6 +3,14 @@
// RUN: -target-cpu pwr10 -triple powerpc64le-unknown-unknown -emit-llvm %s \
// RUN: -o - | FileCheck %s
+// RUN: %clang_cc1 -target-feature +vsx -target-feature +altivec \
+// RUN: -target-cpu pwr10 -triple powerpc64-unknown-unknown -emit-llvm %s \
+// RUN: -o - | FileCheck %s -check-prefix=CHECK-BE
+
+// RUN: %clang_cc1 -target-feature +vsx -target-feature +altivec \
+// RUN: -target-cpu pwr10 -triple powerpc64le-unknown-unknown -emit-llvm %s \
+// RUN: -o - | FileCheck %s -check-prefix=CHECK-LE
+
#include <altivec.h>
vector signed char vsca, vscb;
@@ -16,7 +24,10 @@
vector unsigned __int128 vui128a, vui128b, vui128c;
vector float vfa, vfb;
vector double vda, vdb;
-unsigned int uia;
+unsigned int uia, uib;
+unsigned char uca;
+unsigned short usa;
+unsigned long long ulla;
vector unsigned long long test_vpdepd(void) {
// CHECK: @llvm.ppc.altivec.vpdepd(<2 x i64>
@@ -389,3 +400,115 @@
// CHECK-NEXT: ret <2 x double>
return vec_blendv(vda, vdb, vullc);
}
+
+vector unsigned char test_vec_insertl_uc(void) {
+ // CHECK-BE: @llvm.ppc.altivec.vinsblx(<16 x i8> %{{.+}}, i64 %{{.+}}, i64
+ // CHECK-BE-NEXT: ret <16 x i8>
+ // CHECK-LE: @llvm.ppc.altivec.vinsbrx(<16 x i8> %{{.+}}, i64 %{{.+}}, i64
+ // CHECK-LE-NEXT: ret <16 x i8>
+ return vec_insertl(uca, vuca, uia);
+}
+
+vector unsigned short test_vec_insertl_us(void) {
+ // CHECK-BE: @llvm.ppc.altivec.vinshlx(<8 x i16> %{{.+}}, i64 %{{.+}}, i64
+ // CHECK-BE-NEXT: ret <8 x i16>
+ // CHECK-LE: @llvm.ppc.altivec.vinshrx(<8 x i16> %{{.+}}, i64 %{{.+}}, i64
+ // CHECK-LE-NEXT: ret <8 x i16>
+ return vec_insertl(usa, vusa, uia);
+}
+
+vector unsigned int test_vec_insertl_ui(void) {
+ // CHECK-BE: @llvm.ppc.altivec.vinswlx(<4 x i32> %{{.+}}, i64 %{{.+}}, i64
+ // CHECK-BE-NEXT: ret <4 x i32>
+ // CHECK-LE: @llvm.ppc.altivec.vinswrx(<4 x i32> %{{.+}}, i64 %{{.+}}, i64
+ // CHECK-LE-NEXT: ret <4 x i32>
+ return vec_insertl(uib, vuia, uia);
+}
+
+vector unsigned long long test_vec_insertl_ul(void) {
+ // CHECK-BE: @llvm.ppc.altivec.vinsdlx(<2 x i64> %{{.+}}, i64 %{{.+}}, i64
+ // CHECK-BE-NEXT: ret <2 x i64>
+ // CHECK-LE: @llvm.ppc.altivec.vinsdrx(<2 x i64> %{{.+}}, i64 %{{.+}}, i64
+ // CHECK-LE-NEXT: ret <2 x i64>
+ return vec_insertl(ulla, vulla, uia);
+}
+
+vector unsigned char test_vec_insertl_ucv(void) {
+ // CHECK-BE: @llvm.ppc.altivec.vinsbvlx(<16 x i8> %{{.+}}, i64 %{{.+}}, <16 x i8>
+ // CHECK-BE-NEXT: ret <16 x i8>
+ // CHECK-LE: @llvm.ppc.altivec.vinsbvrx(<16 x i8> %{{.+}}, i64 %{{.+}}, <16 x i8>
+ // CHECK-LE-NEXT: ret <16 x i8>
+ return vec_insertl(vuca, vucb, uia);
+}
+
+vector unsigned short test_vec_insertl_usv(void) {
+ // CHECK-BE: @llvm.ppc.altivec.vinshvlx(<8 x i16> %{{.+}}, i64 %{{.+}}, <8 x i16>
+ // CHECK-BE-NEXT: ret <8 x i16>
+ // CHECK-LE: @llvm.ppc.altivec.vinshvrx(<8 x i16> %{{.+}}, i64 %{{.+}}, <8 x i16>
+ // CHECK-LE-NEXT: ret <8 x i16>
+ return vec_insertl(vusa, vusb, uia);
+}
+
+vector unsigned int test_vec_insertl_uiv(void) {
+ // CHECK-BE: @llvm.ppc.altivec.vinswvlx(<4 x i32> %{{.+}}, i64 %{{.+}}, <4 x i32>
+ // CHECK-BE-NEXT: ret <4 x i32>
+ // CHECK-LE: @llvm.ppc.altivec.vinswvrx(<4 x i32> %{{.+}}, i64 %{{.+}}, <4 x i32>
+ // CHECK-LE-NEXT: ret <4 x i32>
+ return vec_insertl(vuia, vuib, uia);
+}
+
+vector unsigned char test_vec_inserth_uc(void) {
+ // CHECK-BE: @llvm.ppc.altivec.vinsbrx(<16 x i8> %{{.+}}, i64 %{{.+}}, i64
+ // CHECK-BE-NEXT: ret <16 x i8>
+ // CHECK-LE: @llvm.ppc.altivec.vinsblx(<16 x i8> %{{.+}}, i64 %{{.+}}, i64
+ // CHECK-LE-NEXT: ret <16 x i8>
+ return vec_inserth(uca, vuca, uia);
+}
+
+vector unsigned short test_vec_inserth_us(void) {
+ // CHECK-BE: @llvm.ppc.altivec.vinshrx(<8 x i16> %{{.+}}, i64 %{{.+}}, i64
+ // CHECK-BE-NEXT: ret <8 x i16>
+ // CHECK-LE: @llvm.ppc.altivec.vinshlx(<8 x i16> %{{.+}}, i64 %{{.+}}, i64
+ // CHECK-LE-NEXT: ret <8 x i16>
+ return vec_inserth(usa, vusa, uia);
+}
+
+vector unsigned int test_vec_inserth_ui(void) {
+ // CHECK-BE: @llvm.ppc.altivec.vinswrx(<4 x i32> %{{.+}}, i64 %{{.+}}, i64
+ // CHECK-BE-NEXT: ret <4 x i32>
+ // CHECK-LE: @llvm.ppc.altivec.vinswlx(<4 x i32> %{{.+}}, i64 %{{.+}}, i64
+ // CHECK-LE-NEXT: ret <4 x i32>
+ return vec_inserth(uib, vuia, uia);
+}
+
+vector unsigned long long test_vec_inserth_ul(void) {
+ // CHECK-BE: @llvm.ppc.altivec.vinsdrx(<2 x i64> %{{.+}}, i64 %{{.+}}, i64
+ // CHECK-BE-NEXT: ret <2 x i64>
+ // CHECK-LE: @llvm.ppc.altivec.vinsdlx(<2 x i64> %{{.+}}, i64 %{{.+}}, i64
+ // CHECK-LE-NEXT: ret <2 x i64>
+ return vec_inserth(ulla, vulla, uia);
+}
+
+vector unsigned char test_vec_inserth_ucv(void) {
+ // CHECK-BE: @llvm.ppc.altivec.vinsbvrx(<16 x i8> %{{.+}}, i64 %{{.+}}, <16 x i8>
+ // CHECK-BE-NEXT: ret <16 x i8>
+ // CHECK-LE: @llvm.ppc.altivec.vinsbvlx(<16 x i8> %{{.+}}, i64 %{{.+}}, <16 x i8>
+ // CHECK-LE-NEXT: ret <16 x i8>
+ return vec_inserth(vuca, vucb, uia);
+}
+
+vector unsigned short test_vec_inserth_usv(void) {
+ // CHECK-BE: @llvm.ppc.altivec.vinshvrx(<8 x i16> %{{.+}}, i64 %{{.+}}, <8 x i16>
+ // CHECK-BE-NEXT: ret <8 x i16>
+ // CHECK-LE: @llvm.ppc.altivec.vinshvlx(<8 x i16> %{{.+}}, i64 %{{.+}}, <8 x i16>
+ // CHECK-LE-NEXT: ret <8 x i16>
+ return vec_inserth(vusa, vusb, uia);
+}
+
+vector unsigned int test_vec_inserth_uiv(void) {
+ // CHECK-BE: @llvm.ppc.altivec.vinswvrx(<4 x i32> %{{.+}}, i64 %{{.+}}, <4 x i32>
+ // CHECK-BE-NEXT: ret <4 x i32>
+ // CHECK-LE: @llvm.ppc.altivec.vinswvlx(<4 x i32> %{{.+}}, i64 %{{.+}}, <4 x i32>
+ // CHECK-LE-NEXT: ret <4 x i32>
+ return vec_inserth(vuia, vuib, uia);
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index 572b356..6aa0c35 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -464,6 +464,64 @@
Intrinsic<[llvm_v16i8_ty],
[llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty],
[IntrNoMem, ImmArg<ArgIndex<2>>]>;
+
+ // P10 Vector Insert.
+ def int_ppc_altivec_vinsblx : GCCBuiltin<"__builtin_altivec_vinsblx">,
+ Intrinsic<[llvm_v16i8_ty],
+ [llvm_v16i8_ty, llvm_i64_ty, llvm_i64_ty],
+ [IntrNoMem]>;
+ def int_ppc_altivec_vinsbrx : GCCBuiltin<"__builtin_altivec_vinsbrx">,
+ Intrinsic<[llvm_v16i8_ty],
+ [llvm_v16i8_ty, llvm_i64_ty, llvm_i64_ty],
+ [IntrNoMem]>;
+ def int_ppc_altivec_vinshlx : GCCBuiltin<"__builtin_altivec_vinshlx">,
+ Intrinsic<[llvm_v8i16_ty],
+ [llvm_v8i16_ty, llvm_i64_ty, llvm_i64_ty],
+ [IntrNoMem]>;
+ def int_ppc_altivec_vinshrx : GCCBuiltin<"__builtin_altivec_vinshrx">,
+ Intrinsic<[llvm_v8i16_ty],
+ [llvm_v8i16_ty, llvm_i64_ty, llvm_i64_ty],
+ [IntrNoMem]>;
+ def int_ppc_altivec_vinswlx : GCCBuiltin<"__builtin_altivec_vinswlx">,
+ Intrinsic<[llvm_v4i32_ty],
+ [llvm_v4i32_ty, llvm_i64_ty, llvm_i64_ty],
+ [IntrNoMem]>;
+ def int_ppc_altivec_vinswrx : GCCBuiltin<"__builtin_altivec_vinswrx">,
+ Intrinsic<[llvm_v4i32_ty],
+ [llvm_v4i32_ty, llvm_i64_ty, llvm_i64_ty],
+ [IntrNoMem]>;
+ def int_ppc_altivec_vinsdlx : GCCBuiltin<"__builtin_altivec_vinsdlx">,
+ Intrinsic<[llvm_v2i64_ty],
+ [llvm_v2i64_ty, llvm_i64_ty, llvm_i64_ty],
+ [IntrNoMem]>;
+ def int_ppc_altivec_vinsdrx : GCCBuiltin<"__builtin_altivec_vinsdrx">,
+ Intrinsic<[llvm_v2i64_ty],
+ [llvm_v2i64_ty, llvm_i64_ty, llvm_i64_ty],
+ [IntrNoMem]>;
+ def int_ppc_altivec_vinsbvlx : GCCBuiltin<"__builtin_altivec_vinsbvlx">,
+ Intrinsic<[llvm_v16i8_ty],
+ [llvm_v16i8_ty, llvm_i64_ty, llvm_v16i8_ty],
+ [IntrNoMem]>;
+ def int_ppc_altivec_vinsbvrx : GCCBuiltin<"__builtin_altivec_vinsbvrx">,
+ Intrinsic<[llvm_v16i8_ty],
+ [llvm_v16i8_ty, llvm_i64_ty, llvm_v16i8_ty],
+ [IntrNoMem]>;
+ def int_ppc_altivec_vinshvlx : GCCBuiltin<"__builtin_altivec_vinshvlx">,
+ Intrinsic<[llvm_v8i16_ty],
+ [llvm_v8i16_ty, llvm_i64_ty, llvm_v8i16_ty],
+ [IntrNoMem]>;
+ def int_ppc_altivec_vinshvrx : GCCBuiltin<"__builtin_altivec_vinshvrx">,
+ Intrinsic<[llvm_v8i16_ty],
+ [llvm_v8i16_ty, llvm_i64_ty, llvm_v8i16_ty],
+ [IntrNoMem]>;
+ def int_ppc_altivec_vinswvlx : GCCBuiltin<"__builtin_altivec_vinswvlx">,
+ Intrinsic<[llvm_v4i32_ty],
+ [llvm_v4i32_ty, llvm_i64_ty, llvm_v4i32_ty],
+ [IntrNoMem]>;
+ def int_ppc_altivec_vinswvrx : GCCBuiltin<"__builtin_altivec_vinswvrx">,
+ Intrinsic<[llvm_v4i32_ty],
+ [llvm_v4i32_ty, llvm_i64_ty, llvm_v4i32_ty],
+ [IntrNoMem]>;
}
// Vector average.
diff --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
index ac08026..9933455 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -777,20 +777,77 @@
i32:$SH))]>;
def VINSW : VXForm_VRT5_UIM5_RB5_ins<207, "vinsw", []>;
def VINSD : VXForm_VRT5_UIM5_RB5_ins<463, "vinsd", []>;
- def VINSBVLX : VXForm_VTB5_RA5_ins<15, "vinsbvlx", []>;
- def VINSBVRX : VXForm_VTB5_RA5_ins<271, "vinsbvrx", []>;
- def VINSHVLX : VXForm_VTB5_RA5_ins<79, "vinshvlx", []>;
- def VINSHVRX : VXForm_VTB5_RA5_ins<335, "vinshvrx", []>;
- def VINSWVLX : VXForm_VTB5_RA5_ins<143, "vinswvlx", []>;
- def VINSWVRX : VXForm_VTB5_RA5_ins<399, "vinswvrx", []>;
- def VINSBLX : VXForm_VRT5_RAB5_ins<527, "vinsblx", []>;
- def VINSBRX : VXForm_VRT5_RAB5_ins<783, "vinsbrx", []>;
- def VINSHLX : VXForm_VRT5_RAB5_ins<591, "vinshlx", []>;
- def VINSHRX : VXForm_VRT5_RAB5_ins<847, "vinshrx", []>;
- def VINSWLX : VXForm_VRT5_RAB5_ins<655, "vinswlx", []>;
- def VINSWRX : VXForm_VRT5_RAB5_ins<911, "vinswrx", []>;
- def VINSDLX : VXForm_VRT5_RAB5_ins<719, "vinsdlx", []>;
- def VINSDRX : VXForm_VRT5_RAB5_ins<975, "vinsdrx", []>;
+ def VINSBVLX :
+ VXForm_VTB5_RA5_ins<15, "vinsbvlx",
+ [(set v16i8:$vD,
+ (int_ppc_altivec_vinsbvlx v16i8:$vDi, i64:$rA,
+ v16i8:$vB))]>;
+ def VINSBVRX :
+ VXForm_VTB5_RA5_ins<271, "vinsbvrx",
+ [(set v16i8:$vD,
+ (int_ppc_altivec_vinsbvrx v16i8:$vDi, i64:$rA,
+ v16i8:$vB))]>;
+ def VINSHVLX :
+ VXForm_VTB5_RA5_ins<79, "vinshvlx",
+ [(set v8i16:$vD,
+ (int_ppc_altivec_vinshvlx v8i16:$vDi, i64:$rA,
+ v8i16:$vB))]>;
+ def VINSHVRX :
+ VXForm_VTB5_RA5_ins<335, "vinshvrx",
+ [(set v8i16:$vD,
+ (int_ppc_altivec_vinshvrx v8i16:$vDi, i64:$rA,
+ v8i16:$vB))]>;
+ def VINSWVLX :
+ VXForm_VTB5_RA5_ins<143, "vinswvlx",
+ [(set v4i32:$vD,
+ (int_ppc_altivec_vinswvlx v4i32:$vDi, i64:$rA,
+ v4i32:$vB))]>;
+ def VINSWVRX :
+ VXForm_VTB5_RA5_ins<399, "vinswvrx",
+ [(set v4i32:$vD,
+ (int_ppc_altivec_vinswvrx v4i32:$vDi, i64:$rA,
+ v4i32:$vB))]>;
+ def VINSBLX :
+ VXForm_VRT5_RAB5_ins<527, "vinsblx",
+ [(set v16i8:$vD,
+ (int_ppc_altivec_vinsblx v16i8:$vDi, i64:$rA,
+ i64:$rB))]>;
+ def VINSBRX :
+ VXForm_VRT5_RAB5_ins<783, "vinsbrx",
+ [(set v16i8:$vD,
+ (int_ppc_altivec_vinsbrx v16i8:$vDi, i64:$rA,
+ i64:$rB))]>;
+ def VINSHLX :
+ VXForm_VRT5_RAB5_ins<591, "vinshlx",
+ [(set v8i16:$vD,
+ (int_ppc_altivec_vinshlx v8i16:$vDi, i64:$rA,
+ i64:$rB))]>;
+ def VINSHRX :
+ VXForm_VRT5_RAB5_ins<847, "vinshrx",
+ [(set v8i16:$vD,
+ (int_ppc_altivec_vinshrx v8i16:$vDi, i64:$rA,
+ i64:$rB))]>;
+ def VINSWLX :
+ VXForm_VRT5_RAB5_ins<655, "vinswlx",
+ [(set v4i32:$vD,
+ (int_ppc_altivec_vinswlx v4i32:$vDi, i64:$rA,
+ i64:$rB))]>;
+ def VINSWRX :
+ VXForm_VRT5_RAB5_ins<911, "vinswrx",
+ [(set v4i32:$vD,
+ (int_ppc_altivec_vinswrx v4i32:$vDi, i64:$rA,
+ i64:$rB))]>;
+ def VINSDLX :
+ VXForm_VRT5_RAB5_ins<719, "vinsdlx",
+ [(set v2i64:$vD,
+ (int_ppc_altivec_vinsdlx v2i64:$vDi, i64:$rA,
+ i64:$rB))]>;
+ def VINSDRX :
+ VXForm_VRT5_RAB5_ins<975, "vinsdrx",
+ [(set v2i64:$vD,
+ (int_ppc_altivec_vinsdrx v2i64:$vDi, i64:$rA,
+ i64:$rB))]>;
+
def VPDEPD : VXForm_1<1485, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vpdepd $vD, $vA, $vB", IIC_VecGeneral,
[(set v2i64:$vD,
diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll
index 61facf3..577bb21 100644
--- a/llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll
+++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll
@@ -81,3 +81,153 @@
ret <2 x i64> %0
}
declare <2 x i64> @llvm.ppc.vsx.xxblendvd(<2 x i64>, <2 x i64>, <2 x i64>)
+
+define <16 x i8> @testVINSBLX(<16 x i8> %a, i64 %b, i64 %c) {
+; CHECK-LABEL: testVINSBLX:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vinsblx v2, r5, r6
+; CHECK-NEXT: blr
+entry:
+ %0 = tail call <16 x i8> @llvm.ppc.altivec.vinsblx(<16 x i8> %a, i64 %b, i64 %c)
+ ret <16 x i8> %0
+}
+declare <16 x i8> @llvm.ppc.altivec.vinsblx(<16 x i8>, i64, i64)
+
+define <16 x i8> @testVINSBRX(<16 x i8> %a, i64 %b, i64 %c) {
+; CHECK-LABEL: testVINSBRX:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vinsbrx v2, r5, r6
+; CHECK-NEXT: blr
+entry:
+ %0 = tail call <16 x i8> @llvm.ppc.altivec.vinsbrx(<16 x i8> %a, i64 %b, i64 %c)
+ ret <16 x i8> %0
+}
+declare <16 x i8> @llvm.ppc.altivec.vinsbrx(<16 x i8>, i64, i64)
+
+define <8 x i16> @testVINSHLX(<8 x i16> %a, i64 %b, i64 %c) {
+; CHECK-LABEL: testVINSHLX:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vinshlx v2, r5, r6
+; CHECK-NEXT: blr
+entry:
+ %0 = tail call <8 x i16> @llvm.ppc.altivec.vinshlx(<8 x i16> %a, i64 %b, i64 %c)
+ ret <8 x i16> %0
+}
+declare <8 x i16> @llvm.ppc.altivec.vinshlx(<8 x i16>, i64, i64)
+
+define <8 x i16> @testVINSHRX(<8 x i16> %a, i64 %b, i64 %c) {
+; CHECK-LABEL: testVINSHRX:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vinshrx v2, r5, r6
+; CHECK-NEXT: blr
+entry:
+ %0 = tail call <8 x i16> @llvm.ppc.altivec.vinshrx(<8 x i16> %a, i64 %b, i64 %c)
+ ret <8 x i16> %0
+}
+declare <8 x i16> @llvm.ppc.altivec.vinshrx(<8 x i16>, i64, i64)
+
+define <4 x i32> @testVINSWLX(<4 x i32> %a, i64 %b, i64 %c) {
+; CHECK-LABEL: testVINSWLX:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vinswlx v2, r5, r6
+; CHECK-NEXT: blr
+entry:
+ %0 = tail call <4 x i32> @llvm.ppc.altivec.vinswlx(<4 x i32> %a, i64 %b, i64 %c)
+ ret <4 x i32> %0
+}
+declare <4 x i32> @llvm.ppc.altivec.vinswlx(<4 x i32>, i64, i64)
+
+define <4 x i32> @testVINSWRX(<4 x i32> %a, i64 %b, i64 %c) {
+; CHECK-LABEL: testVINSWRX:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vinswrx v2, r5, r6
+; CHECK-NEXT: blr
+entry:
+ %0 = tail call <4 x i32> @llvm.ppc.altivec.vinswrx(<4 x i32> %a, i64 %b, i64 %c)
+ ret <4 x i32> %0
+}
+declare <4 x i32> @llvm.ppc.altivec.vinswrx(<4 x i32>, i64, i64)
+
+define <2 x i64> @testVINSDLX(<2 x i64> %a, i64 %b, i64 %c) {
+; CHECK-LABEL: testVINSDLX:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vinsdlx v2, r5, r6
+; CHECK-NEXT: blr
+entry:
+ %0 = tail call <2 x i64> @llvm.ppc.altivec.vinsdlx(<2 x i64> %a, i64 %b, i64 %c)
+ ret <2 x i64> %0
+}
+declare <2 x i64> @llvm.ppc.altivec.vinsdlx(<2 x i64>, i64, i64)
+
+define <2 x i64> @testVINSDRX(<2 x i64> %a, i64 %b, i64 %c) {
+; CHECK-LABEL: testVINSDRX:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vinsdrx v2, r5, r6
+; CHECK-NEXT: blr
+entry:
+ %0 = tail call <2 x i64> @llvm.ppc.altivec.vinsdrx(<2 x i64> %a, i64 %b, i64 %c)
+ ret <2 x i64> %0
+}
+declare <2 x i64> @llvm.ppc.altivec.vinsdrx(<2 x i64>, i64, i64)
+
+define <16 x i8> @testVINSBVLX(<16 x i8> %a, i64 %b, <16 x i8> %c) {
+; CHECK-LABEL: testVINSBVLX:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vinsbvlx v2, r5, v3
+; CHECK-NEXT: blr
+entry:
+ %0 = tail call <16 x i8> @llvm.ppc.altivec.vinsbvlx(<16 x i8> %a, i64 %b, <16 x i8> %c)
+ ret <16 x i8> %0
+}
+declare <16 x i8> @llvm.ppc.altivec.vinsbvlx(<16 x i8>, i64, <16 x i8>)
+
+define <16 x i8> @testVINSBVRX(<16 x i8> %a, i64 %b, <16 x i8> %c) {
+; CHECK-LABEL: testVINSBVRX:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vinsbvrx v2, r5, v3
+; CHECK-NEXT: blr
+entry:
+ %0 = tail call <16 x i8> @llvm.ppc.altivec.vinsbvrx(<16 x i8> %a, i64 %b, <16 x i8> %c)
+ ret <16 x i8> %0
+}
+declare <16 x i8> @llvm.ppc.altivec.vinsbvrx(<16 x i8>, i64, <16 x i8>)
+
+define <8 x i16> @testVINSHVLX(<8 x i16> %a, i64 %b, <8 x i16> %c) {
+; CHECK-LABEL: testVINSHVLX:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vinshvlx v2, r5, v3
+; CHECK-NEXT: blr
+entry:
+ %0 = tail call <8 x i16> @llvm.ppc.altivec.vinshvlx(<8 x i16> %a, i64 %b, <8 x i16> %c)
+ ret <8 x i16> %0
+}
+declare <8 x i16> @llvm.ppc.altivec.vinshvlx(<8 x i16>, i64, <8 x i16>)
+
+define <8 x i16> @testVINSHVRX(<8 x i16> %a, i64 %b, <8 x i16> %c) {
+entry:
+ %0 = tail call <8 x i16> @llvm.ppc.altivec.vinshvrx(<8 x i16> %a, i64 %b, <8 x i16> %c)
+ ret <8 x i16> %0
+}
+declare <8 x i16> @llvm.ppc.altivec.vinshvrx(<8 x i16>, i64, <8 x i16>)
+
+define <4 x i32> @testVINSWVLX(<4 x i32> %a, i64 %b, <4 x i32> %c) {
+; CHECK-LABEL: testVINSWVLX:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vinswvlx v2, r5, v3
+; CHECK-NEXT: blr
+entry:
+ %0 = tail call <4 x i32> @llvm.ppc.altivec.vinswvlx(<4 x i32> %a, i64 %b, <4 x i32> %c)
+ ret <4 x i32> %0
+}
+declare <4 x i32> @llvm.ppc.altivec.vinswvlx(<4 x i32>, i64, <4 x i32>)
+
+define <4 x i32> @testVINSWVRX(<4 x i32> %a, i64 %b, <4 x i32> %c) {
+; CHECK-LABEL: testVINSWVRX:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vinswvrx v2, r5, v3
+; CHECK-NEXT: blr
+entry:
+ %0 = tail call <4 x i32> @llvm.ppc.altivec.vinswvrx(<4 x i32> %a, i64 %b, <4 x i32> %c)
+ ret <4 x i32> %0
+}
+declare <4 x i32> @llvm.ppc.altivec.vinswvrx(<4 x i32>, i64, <4 x i32>)
