llvm/test/CodeGen/AArch64/sme2-intrinsics-cvtl.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme-f16f16 -force-streaming -verify-machineinstrs < %s | FileCheck %s

define {<vscale x 4 x float>, <vscale x 4 x float>}  @multi_vector_cvtl_widen_x2_f16(<vscale x 8 x half> %zn0) {
; CHECK-LABEL: multi_vector_cvtl_widen_x2_f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtl { z0.s, z1.s }, z0.h
; CHECK-NEXT:    ret
  %res = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fcvtl.widen.x2.nxv4f32(<vscale x 8 x half> %zn0)
  ret {<vscale x 4 x float>, <vscale x 4 x float>} %res
}