| # Check that modifying X5 register is not a problem for machine outliner | 
 |  | 
 | # RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \ | 
 | # RUN: | FileCheck -check-prefixes=CHECK,RV32I-MO %s | 
 | # RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \ | 
 | # RUN: | FileCheck -check-prefixes=CHECK,RV64I-MO %s | 
 |  | 
 | --- | | 
 |   define i32 @outline_tail_1(i32 %a, i32 %b) { ret i32 0 } | 
 |  | 
 |   define i32 @outline_tail_2(i32 %a, i32 %b) { ret i32 0 } | 
 | ... | 
 | --- | 
 | name:            outline_tail_1 | 
 | tracksRegLiveness: true | 
 | isOutlined: false | 
 | body:             | | 
 |   bb.0: | 
 |     liveins: $x10, $x11, $x5 | 
 |     ; RV32I-MO-LABEL: name: outline_tail_1 | 
 |     ; RV32I-MO:         PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x5, implicit $x10, implicit $x11 | 
 |     ; | 
 |     ; RV64I-MO-LABEL: name: outline_tail_1 | 
 |     ; RV64I-MO:         PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x5, implicit $x10, implicit $x11 | 
 |     $x11 = ORI $x11, 1023 | 
 |     $x12 = ADDI $x10, 17 | 
 |     $x10 = ADD $x10, $x5 | 
 |     $x11 = AND $x12, $x11 | 
 |     $x10 = SUB $x10, $x11 | 
 |     PseudoRET implicit $x10 | 
 | ... | 
 | --- | 
 | name:            outline_tail_2 | 
 | tracksRegLiveness: true | 
 | isOutlined: false | 
 | body:             | | 
 |   bb.0: | 
 |     liveins: $x10, $x11, $x5 | 
 |     ; RV32I-MO-LABEL: name: outline_tail_2 | 
 |     ; RV32I-MO:         PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x5, implicit $x10, implicit $x11 | 
 |     ; | 
 |     ; RV64I-MO-LABEL: name: outline_tail_2 | 
 |     ; RV64I-MO:         PseudoTAIL target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit $x2, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x2, implicit $x5, implicit $x10, implicit $x11 | 
 |     $x11 = ORI $x11, 1023 | 
 |     $x12 = ADDI $x10, 17 | 
 |     $x10 = ADD $x10, $x5 | 
 |     $x11 = AND $x12, $x11 | 
 |     $x10 = SUB $x10, $x11 | 
 |     PseudoRET implicit $x10 | 
 | ... | 
 |  | 
 |  | 
 | # CHECK-LABEL: name: OUTLINED_FUNCTION_0 | 
 | # CHECK: isOutlined: true |