llvm/test/CodeGen/PowerPC/smulfixsat.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=ppc32 | FileCheck %s

declare  i32 @llvm.smul.fix.sat.i32  (i32, i32, i32)

define i32 @func1(i32 %x, i32 %y) nounwind {
; CHECK-LABEL: func1:
; CHECK:       # %bb.0:
; CHECK-NEXT:    mulhw 5, 3, 4
; CHECK-NEXT:    mullw 3, 3, 4
; CHECK-NEXT:    srawi 4, 3, 31
; CHECK-NEXT:    cmplw 5, 4
; CHECK-NEXT:    beqlr 0
; CHECK-NEXT:  # %bb.1:
; CHECK-NEXT:    srawi 3, 5, 31
; CHECK-NEXT:    xori 3, 3, 65535
; CHECK-NEXT:    xoris 3, 3, 32767
; CHECK-NEXT:    blr
  %tmp = call i32 @llvm.smul.fix.sat.i32(i32 %x, i32 %y, i32 0)
  ret i32 %tmp
}

define i32 @func2(i32 %x, i32 %y) nounwind {
; CHECK-LABEL: func2:
; CHECK:       # %bb.0:
; CHECK-NEXT:    mulhw. 5, 3, 4
; CHECK-NEXT:    bgt 0, .LBB1_2
; CHECK-NEXT:  # %bb.1:
; CHECK-NEXT:    mullw 3, 3, 4
; CHECK-NEXT:    rotlwi 4, 3, 31
; CHECK-NEXT:    rlwimi 4, 5, 31, 0, 0
; CHECK-NEXT:    b .LBB1_3
; CHECK-NEXT:  .LBB1_2:
; CHECK-NEXT:    lis 3, 32767
; CHECK-NEXT:    ori 4, 3, 65535
; CHECK-NEXT:  .LBB1_3:
; CHECK-NEXT:    cmpwi 5, -1
; CHECK-NEXT:    lis 3, -32768
; CHECK-NEXT:    bltlr 0
; CHECK-NEXT:  # %bb.4:
; CHECK-NEXT:    mr 3, 4
; CHECK-NEXT:    blr
  %tmp = call i32 @llvm.smul.fix.sat.i32(i32 %x, i32 %y, i32 1)
  ret i32 %tmp
}