llvm/test/CodeGen/PowerPC/peephole-subreg-def.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=powerpc64le -simplify-mir -verify-machineinstrs \
# RUN:   -run-pass=peephole-opt %s -o - | FileCheck %s

# This tests to make sure that we do not generate subreg def
# as it is illegal to generate subreg defs in machine SSA phase.

---
name:            test_peephole_subreg_def
alignment:       16
tracksRegLiveness: true
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.0.entry:
    liveins: $x3

    ; CHECK-LABEL: name: test_peephole_subreg_def
    ; CHECK: liveins: $x3
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x3
    ; CHECK-NEXT: [[ADDI8_:%[0-9]+]]:g8rc = ADDI8 [[COPY]], 1
    ; CHECK-NEXT: [[EXTSW:%[0-9]+]]:g8rc_and_g8rc_nox0 = EXTSW [[ADDI8_]]
    ; CHECK-NEXT: [[LI8_:%[0-9]+]]:g8rc = LI8 0
    ; CHECK-NEXT: STB8 [[LI8_]], 0, [[EXTSW]]
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprc_and_gprc_nor0 = COPY [[EXTSW]].sub_32
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gprc_and_gprc_nor0 = COPY [[EXTSW]].sub_32
    ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gprc = ADDI killed [[COPY2]], 1
    ; CHECK-NEXT: [[EXTSW_32_64_:%[0-9]+]]:g8rc_and_g8rc_nox0 = EXTSW_32_64 killed [[ADDI]]
    ; CHECK-NEXT: STB8 [[LI8_]], 0, killed [[EXTSW_32_64_]]
    %0:g8rc_and_g8rc_nox0 = COPY $x3
    %1:g8rc = ADDI8 %0, 1
    %2:g8rc_and_g8rc_nox0 = EXTSW %1
    %3:g8rc = LI8 0
    STB8 %3, 0, killed %2
    %4:gprc_and_gprc_nor0 = COPY %1.sub_32
    %5:gprc = ADDI killed %4, 1
    %6:g8rc_and_g8rc_nox0 = EXTSW_32_64 killed %5
    STB8 %3, 0, killed %6

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