llvm/test/CodeGen/PowerPC/fold-zero.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-crbits | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck --check-prefix=CHECK-CRB %s
; RUN: llc -verify-machineinstrs -mattr=-isel < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck --check-prefix=CHECK-NO-ISEL %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"

define i32 @test1(i1 %a, i32 %c) nounwind  {
; CHECK-LABEL: test1:
; CHECK:       # %bb.0:
; CHECK-NEXT:    andi. 3, 3, 1
; CHECK-NEXT:    iseleq 3, 0, 4
; CHECK-NEXT:    blr
;
; CHECK-CRB-LABEL: test1:
; CHECK-CRB:       # %bb.0:
; CHECK-CRB-NEXT:    andi. 3, 3, 1
; CHECK-CRB-NEXT:    li 3, 0
; CHECK-CRB-NEXT:    iselgt 3, 4, 3
; CHECK-CRB-NEXT:    blr
;
; CHECK-NO-ISEL-LABEL: test1:
; CHECK-NO-ISEL:       # %bb.0:
; CHECK-NO-ISEL-NEXT:    andi. 3, 3, 1
; CHECK-NO-ISEL-NEXT:    bc 12, 1, .LBB0_2
; CHECK-NO-ISEL-NEXT:  # %bb.1:
; CHECK-NO-ISEL-NEXT:    li 4, 0
; CHECK-NO-ISEL-NEXT:  .LBB0_2:
; CHECK-NO-ISEL-NEXT:    mr 3, 4
; CHECK-NO-ISEL-NEXT:    blr
  %x = select i1 %a, i32 %c, i32 0
  ret i32 %x

}

define i32 @test2(i1 %a, i32 %c) nounwind  {
; CHECK-LABEL: test2:
; CHECK:       # %bb.0:
; CHECK-NEXT:    andi. 3, 3, 1
; CHECK-NEXT:    li 3, 0
; CHECK-NEXT:    iseleq 3, 4, 3
; CHECK-NEXT:    blr
;
; CHECK-CRB-LABEL: test2:
; CHECK-CRB:       # %bb.0:
; CHECK-CRB-NEXT:    andi. 3, 3, 1
; CHECK-CRB-NEXT:    iselgt 3, 0, 4
; CHECK-CRB-NEXT:    blr
;
; CHECK-NO-ISEL-LABEL: test2:
; CHECK-NO-ISEL:       # %bb.0:
; CHECK-NO-ISEL-NEXT:    andi. 3, 3, 1
; CHECK-NO-ISEL-NEXT:    li 3, 0
; CHECK-NO-ISEL-NEXT:    bclr 12, 1, 0
; CHECK-NO-ISEL-NEXT:  # %bb.1:
; CHECK-NO-ISEL-NEXT:    mr 3, 4
; CHECK-NO-ISEL-NEXT:    blr
  %x = select i1 %a, i32 0, i32 %c
  ret i32 %x

}