llvm/test/CodeGen/PowerPC/builtins-ppc-bcd-assist.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux \
; RUN:   --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
; RUN:   --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s

define i64 @cdtbcd_test(i64 noundef %ll) {
; CHECK-LABEL: cdtbcd_test:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    cdtbcd r3, r3
; CHECK-NEXT:    blr
entry:
  %0 = tail call i64 @llvm.ppc.cdtbcdd(i64 %ll)
  ret i64 %0
}

define zeroext i32 @cdtbcd_test_ui(i32 noundef zeroext %ui) {
; CHECK-LABEL: cdtbcd_test_ui:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    cdtbcd r3, r3
; CHECK-NEXT:    clrldi r3, r3, 32
; CHECK-NEXT:    blr
entry:
  %conv = zext i32 %ui to i64
  %0 = tail call i64 @llvm.ppc.cdtbcdd(i64 %conv)
  %conv1 = trunc i64 %0 to i32
  ret i32 %conv1
}

define i64 @cbcdtd_test(i64 noundef %ll) {
; CHECK-LABEL: cbcdtd_test:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    cbcdtd r3, r3
; CHECK-NEXT:    blr
entry:
  %0 = tail call i64 @llvm.ppc.cbcdtdd(i64 %ll)
  ret i64 %0
}

define zeroext i32 @cbcdtd_test_ui(i32 noundef zeroext %ui) {
; CHECK-LABEL: cbcdtd_test_ui:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    cbcdtd r3, r3
; CHECK-NEXT:    clrldi r3, r3, 32
; CHECK-NEXT:    blr
entry:
  %conv = zext i32 %ui to i64
  %0 = tail call i64 @llvm.ppc.cbcdtdd(i64 %conv)
  %conv1 = trunc i64 %0 to i32
  ret i32 %conv1
}

define i64 @addg6s_test(i64 noundef %ll, i64 noundef %ll2) {
; CHECK-LABEL: addg6s_test:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    addg6s r3, r3, r4
; CHECK-NEXT:    blr
entry:
  %0 = tail call i64 @llvm.ppc.addg6sd(i64 %ll, i64 %ll2)
  ret i64 %0
}

define zeroext i32 @addg6s_test_ui(i32 noundef zeroext %ui, i32 noundef zeroext %ui2) {
; CHECK-LABEL: addg6s_test_ui:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    addg6s r3, r3, r4
; CHECK-NEXT:    clrldi r3, r3, 32
; CHECK-NEXT:    blr
entry:
  %conv = zext i32 %ui to i64
  %conv1 = zext i32 %ui2 to i64
  %0 = tail call i64 @llvm.ppc.addg6sd(i64 %conv, i64 %conv1)
  %conv2 = trunc i64 %0 to i32
  ret i32 %conv2
}

declare i64 @llvm.ppc.cdtbcdd(i64)
declare i64 @llvm.ppc.cbcdtdd(i64)
declare i64 @llvm.ppc.addg6sd(i64, i64)