llvm/test/CodeGen/AMDGPU/bug-sdag-emitcopyfromreg.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck %s -check-prefix=ISA
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -stop-before=si-fix-sgpr-copies < %s | FileCheck %s -check-prefix=MIR

define void @f(i32 %arg, ptr %ptr) {
; ISA-LABEL: f:
; ISA:       ; %bb.0: ; %bb
; ISA-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; ISA-NEXT:    s_mov_b64 s[4:5], 0
; ISA-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v0
; ISA-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x0
; ISA-NEXT:    v_mov_b32_e32 v6, 0
; ISA-NEXT:    s_waitcnt lgkmcnt(0)
; ISA-NEXT:    s_lshr_b32 s6, s5, 1
; ISA-NEXT:    s_lshr_b32 s7, 1, s4
; ISA-NEXT:    s_cmp_lg_u32 s4, 0
; ISA-NEXT:    s_cselect_b32 s4, -1, 0
; ISA-NEXT:    v_cndmask_b32_e64 v0, 0, 1.0, s4
; ISA-NEXT:    s_and_b32 s4, s4, exec_lo
; ISA-NEXT:    s_cselect_b32 s4, s6, 0
; ISA-NEXT:    s_cselect_b32 s6, s7, 0
; ISA-NEXT:    s_cselect_b32 s5, s5, 0
; ISA-NEXT:    v_cvt_f32_i32_e32 v3, s4
; ISA-NEXT:    v_cvt_f32_ubyte0_e32 v4, s6
; ISA-NEXT:    v_cvt_f32_i32_e32 v5, s5
; ISA-NEXT:    s_mov_b32 s4, 0
; ISA-NEXT:  .LBB0_1: ; %bb14
; ISA-NEXT:    ; =>This Inner Loop Header: Depth=1
; ISA-NEXT:    v_mov_b32_e32 v7, v6
; ISA-NEXT:    s_and_b32 s5, exec_lo, vcc_lo
; ISA-NEXT:    s_or_b32 s4, s5, s4
; ISA-NEXT:    v_add_f32_e32 v6, v7, v0
; ISA-NEXT:    v_add_f32_e64 v6, v6, |v3|
; ISA-NEXT:    v_add_f32_e32 v6, v6, v4
; ISA-NEXT:    v_add_f32_e32 v6, v6, v5
; ISA-NEXT:    s_andn2_b32 exec_lo, exec_lo, s4
; ISA-NEXT:    s_cbranch_execnz .LBB0_1
; ISA-NEXT:  ; %bb.2: ; %bb21
; ISA-NEXT:    s_or_b32 exec_lo, exec_lo, s4
; ISA-NEXT:    flat_store_dword v[1:2], v7
; ISA-NEXT:    s_waitcnt lgkmcnt(0)
; ISA-NEXT:    s_setpc_b64 s[30:31]
bb:
  %i = load <2 x i32>, ptr addrspace(4) null, align 4294967296
  %i1 = extractelement <2 x i32> %i, i64 1
  %i2 = extractelement <2 x i32> %i, i64 0
  %i3 = lshr i32 %i1, 1
  %i4 = icmp ne i32 %i2, 0
  %i5 = select i1 %i4, i32 %i3, i32 0
  %i6 = sitofp i32 %i5 to float
  %i7 = call float @llvm.fabs.f32(float %i6)
  %i8 = uitofp i1 %i4 to float
  %i9 = lshr i32 1, %i2
  %i10 = select i1 %i4, i32 %i9, i32 0
  %i11 = sitofp i32 %i10 to float
  %i12 = select i1 %i4, i32 %i1, i32 0
  %i13 = sitofp i32 %i12 to float
  br label %bb14

bb14:
  %i15 = phi float [ 0.0, %bb ], [ %i19, %bb14 ]
  %i16 = fadd float %i15, %i8
  %i17 = fadd float %i16, %i7
  %i18 = fadd float %i17, %i11
  %i19 = fadd float %i18, %i13
  %i20 = icmp sgt i32 %arg, 0
  br i1 %i20, label %bb14, label %bb21

bb21:
  store float %i15, ptr %ptr, align 4
  ret void
}

declare float @llvm.fabs.f32(float)
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; MIR: {{.*}}