| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 |
| |
| ; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s |
| ; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=VI %s |
| ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s |
| ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s |
| |
| define <12 x float> @bitcast_v12i32_to_v12f32(<12 x i32> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v12i32_to_v12f32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB0_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v11, vcc, 3, v11 |
| ; GCN-NEXT: v_add_i32_e32 v10, vcc, 3, v10 |
| ; GCN-NEXT: v_add_i32_e32 v9, vcc, 3, v9 |
| ; GCN-NEXT: v_add_i32_e32 v8, vcc, 3, v8 |
| ; GCN-NEXT: v_add_i32_e32 v7, vcc, 3, v7 |
| ; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v6 |
| ; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v5 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v4 |
| ; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v3 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v2 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v1 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0 |
| ; GCN-NEXT: .LBB0_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v12i32_to_v12f32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB0_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_u32_e32 v11, vcc, 3, v11 |
| ; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10 |
| ; VI-NEXT: v_add_u32_e32 v9, vcc, 3, v9 |
| ; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8 |
| ; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v7 |
| ; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6 |
| ; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v5 |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4 |
| ; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2 |
| ; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1 |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0 |
| ; VI-NEXT: .LBB0_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v12i32_to_v12f32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB0_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_u32_e32 v11, 3, v11 |
| ; GFX9-NEXT: v_add_u32_e32 v10, 3, v10 |
| ; GFX9-NEXT: v_add_u32_e32 v9, 3, v9 |
| ; GFX9-NEXT: v_add_u32_e32 v8, 3, v8 |
| ; GFX9-NEXT: v_add_u32_e32 v7, 3, v7 |
| ; GFX9-NEXT: v_add_u32_e32 v6, 3, v6 |
| ; GFX9-NEXT: v_add_u32_e32 v5, 3, v5 |
| ; GFX9-NEXT: v_add_u32_e32 v4, 3, v4 |
| ; GFX9-NEXT: v_add_u32_e32 v3, 3, v3 |
| ; GFX9-NEXT: v_add_u32_e32 v2, 3, v2 |
| ; GFX9-NEXT: v_add_u32_e32 v1, 3, v1 |
| ; GFX9-NEXT: v_add_u32_e32 v0, 3, v0 |
| ; GFX9-NEXT: .LBB0_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v12i32_to_v12f32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB0_2 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_nc_u32_e32 v11, 3, v11 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v10, 3, v10 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v9, 3, v9 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v8, 3, v8 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v7, 3, v7 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v6 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v5 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v3 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0 |
| ; GFX11-NEXT: .LBB0_2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <12 x i32> %a, splat (i32 3) |
| %a2 = bitcast <12 x i32> %a1 to <12 x float> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <12 x i32> %a to <12 x float> |
| br label %end |
| |
| end: |
| %phi = phi <12 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <12 x float> %phi |
| } |
| |
| define <12 x i32> @bitcast_v12f32_to_v12i32(<12 x float> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v12f32_to_v12i32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB1_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.true |
| ; GCN-NEXT: v_add_f32_e32 v11, 1.0, v11 |
| ; GCN-NEXT: v_add_f32_e32 v10, 1.0, v10 |
| ; GCN-NEXT: v_add_f32_e32 v9, 1.0, v9 |
| ; GCN-NEXT: v_add_f32_e32 v8, 1.0, v8 |
| ; GCN-NEXT: v_add_f32_e32 v7, 1.0, v7 |
| ; GCN-NEXT: v_add_f32_e32 v6, 1.0, v6 |
| ; GCN-NEXT: v_add_f32_e32 v5, 1.0, v5 |
| ; GCN-NEXT: v_add_f32_e32 v4, 1.0, v4 |
| ; GCN-NEXT: v_add_f32_e32 v3, 1.0, v3 |
| ; GCN-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; GCN-NEXT: v_add_f32_e32 v1, 1.0, v1 |
| ; GCN-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GCN-NEXT: .LBB1_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v12f32_to_v12i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB1_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_f32_e32 v11, 1.0, v11 |
| ; VI-NEXT: v_add_f32_e32 v10, 1.0, v10 |
| ; VI-NEXT: v_add_f32_e32 v9, 1.0, v9 |
| ; VI-NEXT: v_add_f32_e32 v8, 1.0, v8 |
| ; VI-NEXT: v_add_f32_e32 v7, 1.0, v7 |
| ; VI-NEXT: v_add_f32_e32 v6, 1.0, v6 |
| ; VI-NEXT: v_add_f32_e32 v5, 1.0, v5 |
| ; VI-NEXT: v_add_f32_e32 v4, 1.0, v4 |
| ; VI-NEXT: v_add_f32_e32 v3, 1.0, v3 |
| ; VI-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; VI-NEXT: v_add_f32_e32 v1, 1.0, v1 |
| ; VI-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; VI-NEXT: .LBB1_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v12f32_to_v12i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB1_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_f32_e32 v11, 1.0, v11 |
| ; GFX9-NEXT: v_add_f32_e32 v10, 1.0, v10 |
| ; GFX9-NEXT: v_add_f32_e32 v9, 1.0, v9 |
| ; GFX9-NEXT: v_add_f32_e32 v8, 1.0, v8 |
| ; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v7 |
| ; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v6 |
| ; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v5 |
| ; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4 |
| ; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v3 |
| ; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1 |
| ; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GFX9-NEXT: .LBB1_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v12f32_to_v12i32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_dual_add_f32 v11, 1.0, v11 :: v_dual_add_f32 v10, 1.0, v10 |
| ; GFX11-NEXT: v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8 |
| ; GFX11-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6 |
| ; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4 |
| ; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2 |
| ; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0 |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <12 x float> %a, splat (float 1.000000e+00) |
| %a2 = bitcast <12 x float> %a1 to <12 x i32> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <12 x float> %a to <12 x i32> |
| br label %end |
| |
| end: |
| %phi = phi <12 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <12 x i32> %phi |
| } |
| |
| define <6 x double> @bitcast_v12i32_to_v6f64(<12 x i32> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v12i32_to_v6f64: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB2_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v11, vcc, 3, v11 |
| ; GCN-NEXT: v_add_i32_e32 v10, vcc, 3, v10 |
| ; GCN-NEXT: v_add_i32_e32 v9, vcc, 3, v9 |
| ; GCN-NEXT: v_add_i32_e32 v8, vcc, 3, v8 |
| ; GCN-NEXT: v_add_i32_e32 v7, vcc, 3, v7 |
| ; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v6 |
| ; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v5 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v4 |
| ; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v3 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v2 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v1 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0 |
| ; GCN-NEXT: .LBB2_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v12i32_to_v6f64: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB2_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_u32_e32 v11, vcc, 3, v11 |
| ; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10 |
| ; VI-NEXT: v_add_u32_e32 v9, vcc, 3, v9 |
| ; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8 |
| ; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v7 |
| ; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6 |
| ; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v5 |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4 |
| ; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2 |
| ; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1 |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0 |
| ; VI-NEXT: .LBB2_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v12i32_to_v6f64: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB2_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_u32_e32 v11, 3, v11 |
| ; GFX9-NEXT: v_add_u32_e32 v10, 3, v10 |
| ; GFX9-NEXT: v_add_u32_e32 v9, 3, v9 |
| ; GFX9-NEXT: v_add_u32_e32 v8, 3, v8 |
| ; GFX9-NEXT: v_add_u32_e32 v7, 3, v7 |
| ; GFX9-NEXT: v_add_u32_e32 v6, 3, v6 |
| ; GFX9-NEXT: v_add_u32_e32 v5, 3, v5 |
| ; GFX9-NEXT: v_add_u32_e32 v4, 3, v4 |
| ; GFX9-NEXT: v_add_u32_e32 v3, 3, v3 |
| ; GFX9-NEXT: v_add_u32_e32 v2, 3, v2 |
| ; GFX9-NEXT: v_add_u32_e32 v1, 3, v1 |
| ; GFX9-NEXT: v_add_u32_e32 v0, 3, v0 |
| ; GFX9-NEXT: .LBB2_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v12i32_to_v6f64: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB2_2 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_nc_u32_e32 v11, 3, v11 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v10, 3, v10 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v9, 3, v9 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v8, 3, v8 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v7, 3, v7 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v6 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v5 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v3 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0 |
| ; GFX11-NEXT: .LBB2_2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <12 x i32> %a, splat (i32 3) |
| %a2 = bitcast <12 x i32> %a1 to <6 x double> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <12 x i32> %a to <6 x double> |
| br label %end |
| |
| end: |
| %phi = phi <6 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <6 x double> %phi |
| } |
| |
| define <12 x i32> @bitcast_v6f64_to_v12i32(<6 x double> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v6f64_to_v12i32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB3_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.true |
| ; GCN-NEXT: v_add_f64 v[10:11], v[10:11], 1.0 |
| ; GCN-NEXT: v_add_f64 v[8:9], v[8:9], 1.0 |
| ; GCN-NEXT: v_add_f64 v[6:7], v[6:7], 1.0 |
| ; GCN-NEXT: v_add_f64 v[4:5], v[4:5], 1.0 |
| ; GCN-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 |
| ; GCN-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 |
| ; GCN-NEXT: .LBB3_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v6f64_to_v12i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB3_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_f64 v[10:11], v[10:11], 1.0 |
| ; VI-NEXT: v_add_f64 v[8:9], v[8:9], 1.0 |
| ; VI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0 |
| ; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0 |
| ; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 |
| ; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 |
| ; VI-NEXT: .LBB3_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v6f64_to_v12i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB3_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_f64 v[10:11], v[10:11], 1.0 |
| ; GFX9-NEXT: v_add_f64 v[8:9], v[8:9], 1.0 |
| ; GFX9-NEXT: v_add_f64 v[6:7], v[6:7], 1.0 |
| ; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0 |
| ; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 |
| ; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 |
| ; GFX9-NEXT: .LBB3_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v6f64_to_v12i32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB3_2 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_f64 v[10:11], v[10:11], 1.0 |
| ; GFX11-NEXT: v_add_f64 v[8:9], v[8:9], 1.0 |
| ; GFX11-NEXT: v_add_f64 v[6:7], v[6:7], 1.0 |
| ; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0 |
| ; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 |
| ; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 |
| ; GFX11-NEXT: .LBB3_2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <6 x double> %a, splat (double 1.000000e+00) |
| %a2 = bitcast <6 x double> %a1 to <12 x i32> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <6 x double> %a to <12 x i32> |
| br label %end |
| |
| end: |
| %phi = phi <12 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <12 x i32> %phi |
| } |
| |
| define <6 x i64> @bitcast_v12i32_to_v6i64(<12 x i32> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v12i32_to_v6i64: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB4_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v11, vcc, 3, v11 |
| ; GCN-NEXT: v_add_i32_e32 v10, vcc, 3, v10 |
| ; GCN-NEXT: v_add_i32_e32 v9, vcc, 3, v9 |
| ; GCN-NEXT: v_add_i32_e32 v8, vcc, 3, v8 |
| ; GCN-NEXT: v_add_i32_e32 v7, vcc, 3, v7 |
| ; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v6 |
| ; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v5 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v4 |
| ; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v3 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v2 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v1 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0 |
| ; GCN-NEXT: .LBB4_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v12i32_to_v6i64: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB4_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_u32_e32 v11, vcc, 3, v11 |
| ; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10 |
| ; VI-NEXT: v_add_u32_e32 v9, vcc, 3, v9 |
| ; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8 |
| ; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v7 |
| ; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6 |
| ; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v5 |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4 |
| ; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2 |
| ; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1 |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0 |
| ; VI-NEXT: .LBB4_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v12i32_to_v6i64: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB4_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_u32_e32 v11, 3, v11 |
| ; GFX9-NEXT: v_add_u32_e32 v10, 3, v10 |
| ; GFX9-NEXT: v_add_u32_e32 v9, 3, v9 |
| ; GFX9-NEXT: v_add_u32_e32 v8, 3, v8 |
| ; GFX9-NEXT: v_add_u32_e32 v7, 3, v7 |
| ; GFX9-NEXT: v_add_u32_e32 v6, 3, v6 |
| ; GFX9-NEXT: v_add_u32_e32 v5, 3, v5 |
| ; GFX9-NEXT: v_add_u32_e32 v4, 3, v4 |
| ; GFX9-NEXT: v_add_u32_e32 v3, 3, v3 |
| ; GFX9-NEXT: v_add_u32_e32 v2, 3, v2 |
| ; GFX9-NEXT: v_add_u32_e32 v1, 3, v1 |
| ; GFX9-NEXT: v_add_u32_e32 v0, 3, v0 |
| ; GFX9-NEXT: .LBB4_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v12i32_to_v6i64: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB4_2 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_nc_u32_e32 v11, 3, v11 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v10, 3, v10 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v9, 3, v9 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v8, 3, v8 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v7, 3, v7 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v6 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v5 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v3 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0 |
| ; GFX11-NEXT: .LBB4_2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <12 x i32> %a, splat (i32 3) |
| %a2 = bitcast <12 x i32> %a1 to <6 x i64> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <12 x i32> %a to <6 x i64> |
| br label %end |
| |
| end: |
| %phi = phi <6 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <6 x i64> %phi |
| } |
| |
| define <12 x i32> @bitcast_v6i64_to_v12i32(<6 x i64> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v6i64_to_v12i32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB5_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v10, vcc, 3, v10 |
| ; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc |
| ; GCN-NEXT: v_add_i32_e32 v8, vcc, 3, v8 |
| ; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc |
| ; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v6 |
| ; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v4 |
| ; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v2 |
| ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0 |
| ; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc |
| ; GCN-NEXT: .LBB5_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v6i64_to_v12i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB5_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10 |
| ; VI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc |
| ; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8 |
| ; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc |
| ; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6 |
| ; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4 |
| ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2 |
| ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0 |
| ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc |
| ; VI-NEXT: .LBB5_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v6i64_to_v12i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB5_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, 3, v10 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc |
| ; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 3, v8 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc |
| ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 3, v6 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc |
| ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v4 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc |
| ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v2 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc |
| ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc |
| ; GFX9-NEXT: .LBB5_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v6i64_to_v12i32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB5_2 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_co_u32 v10, vcc_lo, v10, 3 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) |
| ; GFX11-NEXT: v_add_co_ci_u32_e64 v11, null, 0, v11, vcc_lo |
| ; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, v8, 3 |
| ; GFX11-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo |
| ; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v6, 3 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) |
| ; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo |
| ; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 3 |
| ; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo |
| ; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) |
| ; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo |
| ; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3 |
| ; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo |
| ; GFX11-NEXT: .LBB5_2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <6 x i64> %a, splat (i64 3) |
| %a2 = bitcast <6 x i64> %a1 to <12 x i32> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <6 x i64> %a to <12 x i32> |
| br label %end |
| |
| end: |
| %phi = phi <12 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <12 x i32> %phi |
| } |
| |
| define <24 x i16> @bitcast_v12i32_to_v24i16(<12 x i32> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v12i32_to_v24i16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v22, v11 |
| ; GCN-NEXT: v_mov_b32_e32 v20, v10 |
| ; GCN-NEXT: v_mov_b32_e32 v18, v9 |
| ; GCN-NEXT: v_mov_b32_e32 v16, v8 |
| ; GCN-NEXT: v_mov_b32_e32 v14, v7 |
| ; GCN-NEXT: v_mov_b32_e32 v24, v6 |
| ; GCN-NEXT: v_mov_b32_e32 v10, v5 |
| ; GCN-NEXT: v_mov_b32_e32 v8, v4 |
| ; GCN-NEXT: v_mov_b32_e32 v6, v3 |
| ; GCN-NEXT: v_mov_b32_e32 v4, v2 |
| ; GCN-NEXT: v_mov_b32_e32 v2, v1 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr9 |
| ; GCN-NEXT: ; implicit-def: $vgpr11 |
| ; GCN-NEXT: ; implicit-def: $vgpr13 |
| ; GCN-NEXT: ; implicit-def: $vgpr15 |
| ; GCN-NEXT: ; implicit-def: $vgpr17 |
| ; GCN-NEXT: ; implicit-def: $vgpr19 |
| ; GCN-NEXT: ; implicit-def: $vgpr21 |
| ; GCN-NEXT: ; implicit-def: $vgpr23 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB6_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.false |
| ; GCN-NEXT: v_alignbit_b32 v21, v22, v20, 16 |
| ; GCN-NEXT: v_alignbit_b32 v17, v18, v16, 16 |
| ; GCN-NEXT: v_alignbit_b32 v13, v14, v24, 16 |
| ; GCN-NEXT: v_alignbit_b32 v9, v10, v8, 16 |
| ; GCN-NEXT: v_alignbit_b32 v5, v6, v4, 16 |
| ; GCN-NEXT: v_alignbit_b32 v1, v2, v0, 16 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v22 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v18 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v14 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v10 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v6 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v2 |
| ; GCN-NEXT: .LBB6_2: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB6_4 |
| ; GCN-NEXT: ; %bb.3: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v2 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0 |
| ; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v6 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v4 |
| ; GCN-NEXT: v_add_i32_e32 v10, vcc, 3, v10 |
| ; GCN-NEXT: v_add_i32_e32 v8, vcc, 3, v8 |
| ; GCN-NEXT: v_add_i32_e32 v14, vcc, 3, v14 |
| ; GCN-NEXT: v_add_i32_e32 v24, vcc, 3, v24 |
| ; GCN-NEXT: v_add_i32_e32 v18, vcc, 3, v18 |
| ; GCN-NEXT: v_add_i32_e32 v16, vcc, 3, v16 |
| ; GCN-NEXT: v_add_i32_e32 v22, vcc, 3, v22 |
| ; GCN-NEXT: v_add_i32_e32 v20, vcc, 3, v20 |
| ; GCN-NEXT: v_alignbit_b32 v21, v22, v20, 16 |
| ; GCN-NEXT: v_alignbit_b32 v17, v18, v16, 16 |
| ; GCN-NEXT: v_alignbit_b32 v13, v14, v24, 16 |
| ; GCN-NEXT: v_alignbit_b32 v9, v10, v8, 16 |
| ; GCN-NEXT: v_alignbit_b32 v5, v6, v4, 16 |
| ; GCN-NEXT: v_alignbit_b32 v1, v2, v0, 16 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v22 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v18 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v14 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v10 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v6 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v2 |
| ; GCN-NEXT: .LBB6_4: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: v_mov_b32_e32 v12, v24 |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v12i32_to_v24i16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB6_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_u32_e32 v11, vcc, 3, v11 |
| ; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10 |
| ; VI-NEXT: v_add_u32_e32 v9, vcc, 3, v9 |
| ; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8 |
| ; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v7 |
| ; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6 |
| ; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v5 |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4 |
| ; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2 |
| ; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1 |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0 |
| ; VI-NEXT: .LBB6_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v12i32_to_v24i16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB6_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_u32_e32 v11, 3, v11 |
| ; GFX9-NEXT: v_add_u32_e32 v10, 3, v10 |
| ; GFX9-NEXT: v_add_u32_e32 v9, 3, v9 |
| ; GFX9-NEXT: v_add_u32_e32 v8, 3, v8 |
| ; GFX9-NEXT: v_add_u32_e32 v7, 3, v7 |
| ; GFX9-NEXT: v_add_u32_e32 v6, 3, v6 |
| ; GFX9-NEXT: v_add_u32_e32 v5, 3, v5 |
| ; GFX9-NEXT: v_add_u32_e32 v4, 3, v4 |
| ; GFX9-NEXT: v_add_u32_e32 v3, 3, v3 |
| ; GFX9-NEXT: v_add_u32_e32 v2, 3, v2 |
| ; GFX9-NEXT: v_add_u32_e32 v1, 3, v1 |
| ; GFX9-NEXT: v_add_u32_e32 v0, 3, v0 |
| ; GFX9-NEXT: .LBB6_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v12i32_to_v24i16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB6_2 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_nc_u32_e32 v11, 3, v11 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v10, 3, v10 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v9, 3, v9 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v8, 3, v8 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v7, 3, v7 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v6 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v5 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v3 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0 |
| ; GFX11-NEXT: .LBB6_2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <12 x i32> %a, splat (i32 3) |
| %a2 = bitcast <12 x i32> %a1 to <24 x i16> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <12 x i32> %a to <24 x i16> |
| br label %end |
| |
| end: |
| %phi = phi <24 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <24 x i16> %phi |
| } |
| |
| define <12 x i32> @bitcast_v24i16_to_v12i32(<24 x i16> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v24i16_to_v12i32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v30, v10 |
| ; GCN-NEXT: v_mov_b32_e32 v29, v8 |
| ; GCN-NEXT: v_mov_b32_e32 v28, v6 |
| ; GCN-NEXT: v_mov_b32_e32 v27, v4 |
| ; GCN-NEXT: v_mov_b32_e32 v26, v2 |
| ; GCN-NEXT: v_mov_b32_e32 v25, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v34, 16, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v35, 16, v3 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v24, 16, v5 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v31, 16, v7 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v32, 16, v9 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v33, 16, v11 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v13, 16, v13 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v17, 16, v17 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v19, 16, v19 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v21, 16, v21 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v23, 16, v23 |
| ; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB7_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB7_4 |
| ; GCN-NEXT: .LBB7_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB7_3: ; %cmp.false |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v25 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v26 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v34 |
| ; GCN-NEXT: v_or_b32_e32 v1, v1, v35 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v27 |
| ; GCN-NEXT: v_and_b32_e32 v3, 0xffff, v28 |
| ; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v29 |
| ; GCN-NEXT: v_and_b32_e32 v5, 0xffff, v30 |
| ; GCN-NEXT: v_and_b32_e32 v6, 0xffff, v12 |
| ; GCN-NEXT: v_and_b32_e32 v7, 0xffff, v14 |
| ; GCN-NEXT: v_and_b32_e32 v8, 0xffff, v16 |
| ; GCN-NEXT: v_and_b32_e32 v9, 0xffff, v18 |
| ; GCN-NEXT: v_and_b32_e32 v10, 0xffff, v20 |
| ; GCN-NEXT: v_and_b32_e32 v11, 0xffff, v22 |
| ; GCN-NEXT: v_or_b32_e32 v2, v2, v24 |
| ; GCN-NEXT: v_or_b32_e32 v3, v3, v31 |
| ; GCN-NEXT: v_or_b32_e32 v4, v4, v32 |
| ; GCN-NEXT: v_or_b32_e32 v5, v5, v33 |
| ; GCN-NEXT: v_or_b32_e32 v6, v6, v13 |
| ; GCN-NEXT: v_or_b32_e32 v7, v7, v15 |
| ; GCN-NEXT: v_or_b32_e32 v8, v8, v17 |
| ; GCN-NEXT: v_or_b32_e32 v9, v9, v19 |
| ; GCN-NEXT: v_or_b32_e32 v10, v10, v21 |
| ; GCN-NEXT: v_or_b32_e32 v11, v11, v23 |
| ; GCN-NEXT: ; implicit-def: $vgpr25 |
| ; GCN-NEXT: ; implicit-def: $vgpr26 |
| ; GCN-NEXT: ; implicit-def: $vgpr27 |
| ; GCN-NEXT: ; implicit-def: $vgpr28 |
| ; GCN-NEXT: ; implicit-def: $vgpr29 |
| ; GCN-NEXT: ; implicit-def: $vgpr30 |
| ; GCN-NEXT: ; implicit-def: $vgpr12 |
| ; GCN-NEXT: ; implicit-def: $vgpr14 |
| ; GCN-NEXT: ; implicit-def: $vgpr16 |
| ; GCN-NEXT: ; implicit-def: $vgpr18 |
| ; GCN-NEXT: ; implicit-def: $vgpr20 |
| ; GCN-NEXT: ; implicit-def: $vgpr22 |
| ; GCN-NEXT: ; implicit-def: $vgpr34 |
| ; GCN-NEXT: ; implicit-def: $vgpr35 |
| ; GCN-NEXT: ; implicit-def: $vgpr24 |
| ; GCN-NEXT: ; implicit-def: $vgpr31 |
| ; GCN-NEXT: ; implicit-def: $vgpr32 |
| ; GCN-NEXT: ; implicit-def: $vgpr33 |
| ; GCN-NEXT: ; implicit-def: $vgpr13 |
| ; GCN-NEXT: ; implicit-def: $vgpr15 |
| ; GCN-NEXT: ; implicit-def: $vgpr17 |
| ; GCN-NEXT: ; implicit-def: $vgpr19 |
| ; GCN-NEXT: ; implicit-def: $vgpr21 |
| ; GCN-NEXT: ; implicit-def: $vgpr23 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB7_2 |
| ; GCN-NEXT: .LBB7_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v25 |
| ; GCN-NEXT: s_mov_b32 s6, 0x30000 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v26 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v27 |
| ; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v28 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v29 |
| ; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v30 |
| ; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v12 |
| ; GCN-NEXT: v_add_i32_e32 v7, vcc, 3, v14 |
| ; GCN-NEXT: v_add_i32_e32 v8, vcc, 3, v16 |
| ; GCN-NEXT: v_add_i32_e32 v9, vcc, 3, v18 |
| ; GCN-NEXT: v_add_i32_e32 v10, vcc, 3, v20 |
| ; GCN-NEXT: v_add_i32_e32 v11, vcc, 3, v22 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v1 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2 |
| ; GCN-NEXT: v_and_b32_e32 v3, 0xffff, v3 |
| ; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v4 |
| ; GCN-NEXT: v_and_b32_e32 v5, 0xffff, v5 |
| ; GCN-NEXT: v_and_b32_e32 v6, 0xffff, v6 |
| ; GCN-NEXT: v_and_b32_e32 v7, 0xffff, v7 |
| ; GCN-NEXT: v_and_b32_e32 v8, 0xffff, v8 |
| ; GCN-NEXT: v_and_b32_e32 v9, 0xffff, v9 |
| ; GCN-NEXT: v_and_b32_e32 v10, 0xffff, v10 |
| ; GCN-NEXT: v_and_b32_e32 v11, 0xffff, v11 |
| ; GCN-NEXT: v_or_b32_e32 v0, v34, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v35, v1 |
| ; GCN-NEXT: v_or_b32_e32 v2, v24, v2 |
| ; GCN-NEXT: v_or_b32_e32 v3, v31, v3 |
| ; GCN-NEXT: v_or_b32_e32 v4, v32, v4 |
| ; GCN-NEXT: v_or_b32_e32 v5, v33, v5 |
| ; GCN-NEXT: v_or_b32_e32 v6, v13, v6 |
| ; GCN-NEXT: v_or_b32_e32 v7, v15, v7 |
| ; GCN-NEXT: v_or_b32_e32 v8, v17, v8 |
| ; GCN-NEXT: v_or_b32_e32 v9, v19, v9 |
| ; GCN-NEXT: v_or_b32_e32 v10, v21, v10 |
| ; GCN-NEXT: v_or_b32_e32 v11, v23, v11 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, s6, v1 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, s6, v2 |
| ; GCN-NEXT: v_add_i32_e32 v3, vcc, s6, v3 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, s6, v4 |
| ; GCN-NEXT: v_add_i32_e32 v5, vcc, s6, v5 |
| ; GCN-NEXT: v_add_i32_e32 v6, vcc, s6, v6 |
| ; GCN-NEXT: v_add_i32_e32 v7, vcc, s6, v7 |
| ; GCN-NEXT: v_add_i32_e32 v8, vcc, s6, v8 |
| ; GCN-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9 |
| ; GCN-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10 |
| ; GCN-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v24i16_to_v12i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB7_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v13, 3 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v11 |
| ; VI-NEXT: v_add_u16_sdwa v11, v11, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v11, v12, v11 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v10 |
| ; VI-NEXT: v_add_u16_sdwa v10, v10, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v10, v12, v10 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v9 |
| ; VI-NEXT: v_add_u16_sdwa v9, v9, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v9, v12, v9 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v8 |
| ; VI-NEXT: v_add_u16_sdwa v8, v8, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v8, v12, v8 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v7 |
| ; VI-NEXT: v_add_u16_sdwa v7, v7, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v7, v12, v7 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v6 |
| ; VI-NEXT: v_add_u16_sdwa v6, v6, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v6, v12, v6 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v5 |
| ; VI-NEXT: v_add_u16_sdwa v5, v5, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v5, v12, v5 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v4 |
| ; VI-NEXT: v_add_u16_sdwa v4, v4, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v4, v12, v4 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v3 |
| ; VI-NEXT: v_add_u16_sdwa v3, v3, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v3, v12, v3 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v2 |
| ; VI-NEXT: v_add_u16_sdwa v2, v2, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v2, v12, v2 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v1 |
| ; VI-NEXT: v_add_u16_sdwa v1, v1, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v1, v12, v1 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v0 |
| ; VI-NEXT: v_add_u16_sdwa v0, v0, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v0, v12, v0 |
| ; VI-NEXT: .LBB7_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v24i16_to_v12i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB7_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: .LBB7_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v24i16_to_v12i32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB7_2 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: .LBB7_2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <24 x i16> %a, splat (i16 3) |
| %a2 = bitcast <24 x i16> %a1 to <12 x i32> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <24 x i16> %a to <12 x i32> |
| br label %end |
| |
| end: |
| %phi = phi <12 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <12 x i32> %phi |
| } |
| |
| define <24 x half> @bitcast_v12i32_to_v24f16(<12 x i32> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v12i32_to_v24f16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v35, v11 |
| ; GCN-NEXT: v_mov_b32_e32 v34, v10 |
| ; GCN-NEXT: v_mov_b32_e32 v33, v9 |
| ; GCN-NEXT: v_mov_b32_e32 v32, v8 |
| ; GCN-NEXT: v_mov_b32_e32 v31, v7 |
| ; GCN-NEXT: v_mov_b32_e32 v30, v6 |
| ; GCN-NEXT: v_mov_b32_e32 v29, v5 |
| ; GCN-NEXT: v_mov_b32_e32 v28, v4 |
| ; GCN-NEXT: v_mov_b32_e32 v27, v3 |
| ; GCN-NEXT: v_mov_b32_e32 v26, v2 |
| ; GCN-NEXT: v_mov_b32_e32 v25, v1 |
| ; GCN-NEXT: v_mov_b32_e32 v24, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: ; implicit-def: $vgpr6 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr8 |
| ; GCN-NEXT: ; implicit-def: $vgpr9 |
| ; GCN-NEXT: ; implicit-def: $vgpr10 |
| ; GCN-NEXT: ; implicit-def: $vgpr11 |
| ; GCN-NEXT: ; implicit-def: $vgpr12 |
| ; GCN-NEXT: ; implicit-def: $vgpr13 |
| ; GCN-NEXT: ; implicit-def: $vgpr14 |
| ; GCN-NEXT: ; implicit-def: $vgpr15 |
| ; GCN-NEXT: ; implicit-def: $vgpr16 |
| ; GCN-NEXT: ; implicit-def: $vgpr17 |
| ; GCN-NEXT: ; implicit-def: $vgpr18 |
| ; GCN-NEXT: ; implicit-def: $vgpr19 |
| ; GCN-NEXT: ; implicit-def: $vgpr20 |
| ; GCN-NEXT: ; implicit-def: $vgpr21 |
| ; GCN-NEXT: ; implicit-def: $vgpr22 |
| ; GCN-NEXT: ; implicit-def: $vgpr23 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB8_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB8_4 |
| ; GCN-NEXT: .LBB8_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB8_3: ; %cmp.false |
| ; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v35 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v34 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v33 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v32 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v31 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v30 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v29 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v36, 16, v28 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v37, 16, v27 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v38, 16, v26 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v39, 16, v25 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v48, 16, v24 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v22, v35 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v20, v34 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v18, v33 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v16, v32 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v14, v31 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v12, v30 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v10, v29 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v8, v28 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v6, v27 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v4, v26 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v25 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v23, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v21, v1 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v19, v3 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v17, v5 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v15, v7 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v13, v9 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v11, v11 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v9, v36 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v7, v37 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v38 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v39 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v48 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v24 |
| ; GCN-NEXT: ; implicit-def: $vgpr24 |
| ; GCN-NEXT: ; implicit-def: $vgpr25 |
| ; GCN-NEXT: ; implicit-def: $vgpr26 |
| ; GCN-NEXT: ; implicit-def: $vgpr27 |
| ; GCN-NEXT: ; implicit-def: $vgpr28 |
| ; GCN-NEXT: ; implicit-def: $vgpr29 |
| ; GCN-NEXT: ; implicit-def: $vgpr30 |
| ; GCN-NEXT: ; implicit-def: $vgpr31 |
| ; GCN-NEXT: ; implicit-def: $vgpr32 |
| ; GCN-NEXT: ; implicit-def: $vgpr33 |
| ; GCN-NEXT: ; implicit-def: $vgpr34 |
| ; GCN-NEXT: ; implicit-def: $vgpr35 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB8_2 |
| ; GCN-NEXT: .LBB8_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v24 |
| ; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v25 |
| ; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v26 |
| ; GCN-NEXT: v_add_i32_e32 v7, vcc, 3, v27 |
| ; GCN-NEXT: v_add_i32_e32 v9, vcc, 3, v28 |
| ; GCN-NEXT: v_add_i32_e32 v11, vcc, 3, v29 |
| ; GCN-NEXT: v_add_i32_e32 v13, vcc, 3, v30 |
| ; GCN-NEXT: v_add_i32_e32 v15, vcc, 3, v31 |
| ; GCN-NEXT: v_add_i32_e32 v17, vcc, 3, v32 |
| ; GCN-NEXT: v_add_i32_e32 v19, vcc, 3, v33 |
| ; GCN-NEXT: v_add_i32_e32 v21, vcc, 3, v34 |
| ; GCN-NEXT: v_add_i32_e32 v23, vcc, 3, v35 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v22, v23 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v20, v21 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v18, v19 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v16, v17 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v14, v15 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v12, v13 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v10, v11 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v8, v9 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v6, v7 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v4, v5 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v3 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v1 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v23 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v21, 16, v21 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v19 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v17, 16, v17 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v15 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v13 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v11 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v9 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v1 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v23, v23 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v21, v21 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v19, v19 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v17, v17 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v15, v15 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v13, v13 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v11, v11 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v9, v9 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v7, v7 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v5 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v3 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v12i32_to_v24f16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB8_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_u32_e32 v11, vcc, 3, v11 |
| ; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10 |
| ; VI-NEXT: v_add_u32_e32 v9, vcc, 3, v9 |
| ; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8 |
| ; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v7 |
| ; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6 |
| ; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v5 |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4 |
| ; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2 |
| ; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1 |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0 |
| ; VI-NEXT: .LBB8_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v12i32_to_v24f16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB8_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_u32_e32 v11, 3, v11 |
| ; GFX9-NEXT: v_add_u32_e32 v10, 3, v10 |
| ; GFX9-NEXT: v_add_u32_e32 v9, 3, v9 |
| ; GFX9-NEXT: v_add_u32_e32 v8, 3, v8 |
| ; GFX9-NEXT: v_add_u32_e32 v7, 3, v7 |
| ; GFX9-NEXT: v_add_u32_e32 v6, 3, v6 |
| ; GFX9-NEXT: v_add_u32_e32 v5, 3, v5 |
| ; GFX9-NEXT: v_add_u32_e32 v4, 3, v4 |
| ; GFX9-NEXT: v_add_u32_e32 v3, 3, v3 |
| ; GFX9-NEXT: v_add_u32_e32 v2, 3, v2 |
| ; GFX9-NEXT: v_add_u32_e32 v1, 3, v1 |
| ; GFX9-NEXT: v_add_u32_e32 v0, 3, v0 |
| ; GFX9-NEXT: .LBB8_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v12i32_to_v24f16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB8_2 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_nc_u32_e32 v11, 3, v11 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v10, 3, v10 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v9, 3, v9 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v8, 3, v8 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v7, 3, v7 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v6 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v5 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v3 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1 |
| ; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0 |
| ; GFX11-NEXT: .LBB8_2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <12 x i32> %a, splat (i32 3) |
| %a2 = bitcast <12 x i32> %a1 to <24 x half> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <12 x i32> %a to <24 x half> |
| br label %end |
| |
| end: |
| %phi = phi <24 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <24 x half> %phi |
| } |
| |
| define <12 x i32> @bitcast_v24f16_to_v12i32(<24 x half> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v24f16_to_v12i32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v48, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v39, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v38, v3 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v37, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v36, v5 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v32, v4 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v35, v7 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v30, v6 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v34, v9 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v28, v8 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v33, v11 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v26, v10 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v31, v13 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v25, v12 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v29, v15 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v24, v14 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v27, v17 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v16, v16 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v19, v19 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v14, v18 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v17, v21 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v13, v20 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v15, v23 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v12, v22 |
| ; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB9_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB9_4 |
| ; GCN-NEXT: .LBB9_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB9_3: ; %cmp.false |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v48 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v38 |
| ; GCN-NEXT: v_or_b32_e32 v0, v39, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v37, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v36 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v35 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v34 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v33 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v31 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v29 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v27 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v9, 16, v19 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v17 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v15 |
| ; GCN-NEXT: v_or_b32_e32 v2, v32, v2 |
| ; GCN-NEXT: v_or_b32_e32 v3, v30, v3 |
| ; GCN-NEXT: v_or_b32_e32 v4, v28, v4 |
| ; GCN-NEXT: v_or_b32_e32 v5, v26, v5 |
| ; GCN-NEXT: v_or_b32_e32 v6, v25, v6 |
| ; GCN-NEXT: v_or_b32_e32 v7, v24, v7 |
| ; GCN-NEXT: v_or_b32_e32 v8, v16, v8 |
| ; GCN-NEXT: v_or_b32_e32 v9, v14, v9 |
| ; GCN-NEXT: v_or_b32_e32 v10, v13, v10 |
| ; GCN-NEXT: v_or_b32_e32 v11, v12, v11 |
| ; GCN-NEXT: ; implicit-def: $vgpr48 |
| ; GCN-NEXT: ; implicit-def: $vgpr39 |
| ; GCN-NEXT: ; implicit-def: $vgpr38 |
| ; GCN-NEXT: ; implicit-def: $vgpr37 |
| ; GCN-NEXT: ; implicit-def: $vgpr36 |
| ; GCN-NEXT: ; implicit-def: $vgpr32 |
| ; GCN-NEXT: ; implicit-def: $vgpr35 |
| ; GCN-NEXT: ; implicit-def: $vgpr30 |
| ; GCN-NEXT: ; implicit-def: $vgpr34 |
| ; GCN-NEXT: ; implicit-def: $vgpr28 |
| ; GCN-NEXT: ; implicit-def: $vgpr33 |
| ; GCN-NEXT: ; implicit-def: $vgpr26 |
| ; GCN-NEXT: ; implicit-def: $vgpr31 |
| ; GCN-NEXT: ; implicit-def: $vgpr25 |
| ; GCN-NEXT: ; implicit-def: $vgpr29 |
| ; GCN-NEXT: ; implicit-def: $vgpr24 |
| ; GCN-NEXT: ; implicit-def: $vgpr27 |
| ; GCN-NEXT: ; implicit-def: $vgpr16 |
| ; GCN-NEXT: ; implicit-def: $vgpr19 |
| ; GCN-NEXT: ; implicit-def: $vgpr14 |
| ; GCN-NEXT: ; implicit-def: $vgpr17 |
| ; GCN-NEXT: ; implicit-def: $vgpr13 |
| ; GCN-NEXT: ; implicit-def: $vgpr15 |
| ; GCN-NEXT: ; implicit-def: $vgpr12 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB9_2 |
| ; GCN-NEXT: .LBB9_4: ; %cmp.true |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v48 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v39 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v38 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v37 |
| ; GCN-NEXT: v_add_f32_e32 v0, 0x38000000, v0 |
| ; GCN-NEXT: v_add_f32_e32 v1, 0x38000000, v1 |
| ; GCN-NEXT: v_add_f32_e32 v2, 0x38000000, v2 |
| ; GCN-NEXT: v_add_f32_e32 v3, 0x38000000, v3 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 |
| ; GCN-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v3, v2 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v36 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v32 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v4, v35 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v30 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v6, v34 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v7, v28 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v8, v33 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v9, v26 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v10, v31 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v11, v25 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v18, v29 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v20, v24 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v21, v27 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v16, v16 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v19, v19 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v14, v14 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v17, v17 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v13, v13 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v15, v15 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v12, v12 |
| ; GCN-NEXT: v_add_f32_e32 v2, 0x38000000, v2 |
| ; GCN-NEXT: v_add_f32_e32 v3, 0x38000000, v3 |
| ; GCN-NEXT: v_add_f32_e32 v4, 0x38000000, v4 |
| ; GCN-NEXT: v_add_f32_e32 v5, 0x38000000, v5 |
| ; GCN-NEXT: v_add_f32_e32 v6, 0x38000000, v6 |
| ; GCN-NEXT: v_add_f32_e32 v7, 0x38000000, v7 |
| ; GCN-NEXT: v_add_f32_e32 v8, 0x38000000, v8 |
| ; GCN-NEXT: v_add_f32_e32 v9, 0x38000000, v9 |
| ; GCN-NEXT: v_add_f32_e32 v10, 0x38000000, v10 |
| ; GCN-NEXT: v_add_f32_e32 v11, 0x38000000, v11 |
| ; GCN-NEXT: v_add_f32_e32 v18, 0x38000000, v18 |
| ; GCN-NEXT: v_add_f32_e32 v20, 0x38000000, v20 |
| ; GCN-NEXT: v_add_f32_e32 v21, 0x38000000, v21 |
| ; GCN-NEXT: v_add_f32_e32 v16, 0x38000000, v16 |
| ; GCN-NEXT: v_add_f32_e32 v19, 0x38000000, v19 |
| ; GCN-NEXT: v_add_f32_e32 v14, 0x38000000, v14 |
| ; GCN-NEXT: v_add_f32_e32 v17, 0x38000000, v17 |
| ; GCN-NEXT: v_add_f32_e32 v13, 0x38000000, v13 |
| ; GCN-NEXT: v_add_f32_e32 v15, 0x38000000, v15 |
| ; GCN-NEXT: v_add_f32_e32 v12, 0x38000000, v12 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v4, v4 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v5, v5 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v6, v6 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v7, v7 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v8, v8 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v9, v9 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v10, v10 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v11, v11 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v18, v18 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v20, v20 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v21, v21 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v16, v16 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v19, v19 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v14, v14 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v17, v17 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v13, v13 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v15, v15 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v12, v12 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v4 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v6 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v8 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v10 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v18, 16, v18 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v21, 16, v21 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v19, 16, v19 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v17, 16, v17 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15 |
| ; GCN-NEXT: v_or_b32_e32 v2, v3, v2 |
| ; GCN-NEXT: v_or_b32_e32 v3, v5, v4 |
| ; GCN-NEXT: v_or_b32_e32 v4, v7, v6 |
| ; GCN-NEXT: v_or_b32_e32 v5, v9, v8 |
| ; GCN-NEXT: v_or_b32_e32 v6, v11, v10 |
| ; GCN-NEXT: v_or_b32_e32 v7, v20, v18 |
| ; GCN-NEXT: v_or_b32_e32 v8, v16, v21 |
| ; GCN-NEXT: v_or_b32_e32 v9, v14, v19 |
| ; GCN-NEXT: v_or_b32_e32 v10, v13, v17 |
| ; GCN-NEXT: v_or_b32_e32 v11, v12, v15 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v24f16_to_v12i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB9_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v12, 0x200 |
| ; VI-NEXT: v_add_f16_sdwa v13, v11, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v11, 0x200, v11 |
| ; VI-NEXT: v_or_b32_e32 v11, v11, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v10, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v10, 0x200, v10 |
| ; VI-NEXT: v_or_b32_e32 v10, v10, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v9, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v9, 0x200, v9 |
| ; VI-NEXT: v_or_b32_e32 v9, v9, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v8, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v8, 0x200, v8 |
| ; VI-NEXT: v_or_b32_e32 v8, v8, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v7, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v7, 0x200, v7 |
| ; VI-NEXT: v_or_b32_e32 v7, v7, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v6, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v6, 0x200, v6 |
| ; VI-NEXT: v_or_b32_e32 v6, v6, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v5, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v5, 0x200, v5 |
| ; VI-NEXT: v_or_b32_e32 v5, v5, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v4, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v4, 0x200, v4 |
| ; VI-NEXT: v_or_b32_e32 v4, v4, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v3, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v3, 0x200, v3 |
| ; VI-NEXT: v_or_b32_e32 v3, v3, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v2, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v2, 0x200, v2 |
| ; VI-NEXT: v_or_b32_e32 v2, v2, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v1, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v1, 0x200, v1 |
| ; VI-NEXT: v_add_f16_sdwa v12, v0, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v0, 0x200, v0 |
| ; VI-NEXT: v_or_b32_e32 v1, v1, v13 |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v12 |
| ; VI-NEXT: .LBB9_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v24f16_to_v12i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB9_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: s_movk_i32 s6, 0x200 |
| ; GFX9-NEXT: v_pk_add_f16 v11, v11, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v10, v10, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v9, v9, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v8, v8, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: .LBB9_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v24f16_to_v12i32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB9_2 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1] |
| ; GFX11-NEXT: .LBB9_2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <24 x half> %a, splat (half 0xH0200) |
| %a2 = bitcast <24 x half> %a1 to <12 x i32> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <24 x half> %a to <12 x i32> |
| br label %end |
| |
| end: |
| %phi = phi <12 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <12 x i32> %phi |
| } |
| |
| define <6 x double> @bitcast_v12f32_to_v6f64(<12 x float> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v12f32_to_v6f64: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB10_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.true |
| ; GCN-NEXT: v_add_f32_e32 v11, 1.0, v11 |
| ; GCN-NEXT: v_add_f32_e32 v10, 1.0, v10 |
| ; GCN-NEXT: v_add_f32_e32 v9, 1.0, v9 |
| ; GCN-NEXT: v_add_f32_e32 v8, 1.0, v8 |
| ; GCN-NEXT: v_add_f32_e32 v7, 1.0, v7 |
| ; GCN-NEXT: v_add_f32_e32 v6, 1.0, v6 |
| ; GCN-NEXT: v_add_f32_e32 v5, 1.0, v5 |
| ; GCN-NEXT: v_add_f32_e32 v4, 1.0, v4 |
| ; GCN-NEXT: v_add_f32_e32 v3, 1.0, v3 |
| ; GCN-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; GCN-NEXT: v_add_f32_e32 v1, 1.0, v1 |
| ; GCN-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GCN-NEXT: .LBB10_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v12f32_to_v6f64: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB10_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_f32_e32 v11, 1.0, v11 |
| ; VI-NEXT: v_add_f32_e32 v10, 1.0, v10 |
| ; VI-NEXT: v_add_f32_e32 v9, 1.0, v9 |
| ; VI-NEXT: v_add_f32_e32 v8, 1.0, v8 |
| ; VI-NEXT: v_add_f32_e32 v7, 1.0, v7 |
| ; VI-NEXT: v_add_f32_e32 v6, 1.0, v6 |
| ; VI-NEXT: v_add_f32_e32 v5, 1.0, v5 |
| ; VI-NEXT: v_add_f32_e32 v4, 1.0, v4 |
| ; VI-NEXT: v_add_f32_e32 v3, 1.0, v3 |
| ; VI-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; VI-NEXT: v_add_f32_e32 v1, 1.0, v1 |
| ; VI-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; VI-NEXT: .LBB10_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v12f32_to_v6f64: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB10_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_f32_e32 v11, 1.0, v11 |
| ; GFX9-NEXT: v_add_f32_e32 v10, 1.0, v10 |
| ; GFX9-NEXT: v_add_f32_e32 v9, 1.0, v9 |
| ; GFX9-NEXT: v_add_f32_e32 v8, 1.0, v8 |
| ; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v7 |
| ; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v6 |
| ; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v5 |
| ; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4 |
| ; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v3 |
| ; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1 |
| ; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GFX9-NEXT: .LBB10_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v12f32_to_v6f64: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_dual_add_f32 v11, 1.0, v11 :: v_dual_add_f32 v10, 1.0, v10 |
| ; GFX11-NEXT: v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8 |
| ; GFX11-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6 |
| ; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4 |
| ; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2 |
| ; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0 |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <12 x float> %a, splat (float 1.000000e+00) |
| %a2 = bitcast <12 x float> %a1 to <6 x double> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <12 x float> %a to <6 x double> |
| br label %end |
| |
| end: |
| %phi = phi <6 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <6 x double> %phi |
| } |
| |
| define <12 x float> @bitcast_v6f64_to_v12f32(<6 x double> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v6f64_to_v12f32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB11_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.true |
| ; GCN-NEXT: v_add_f64 v[10:11], v[10:11], 1.0 |
| ; GCN-NEXT: v_add_f64 v[8:9], v[8:9], 1.0 |
| ; GCN-NEXT: v_add_f64 v[6:7], v[6:7], 1.0 |
| ; GCN-NEXT: v_add_f64 v[4:5], v[4:5], 1.0 |
| ; GCN-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 |
| ; GCN-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 |
| ; GCN-NEXT: .LBB11_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v6f64_to_v12f32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB11_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_f64 v[10:11], v[10:11], 1.0 |
| ; VI-NEXT: v_add_f64 v[8:9], v[8:9], 1.0 |
| ; VI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0 |
| ; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0 |
| ; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 |
| ; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 |
| ; VI-NEXT: .LBB11_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v6f64_to_v12f32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB11_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_f64 v[10:11], v[10:11], 1.0 |
| ; GFX9-NEXT: v_add_f64 v[8:9], v[8:9], 1.0 |
| ; GFX9-NEXT: v_add_f64 v[6:7], v[6:7], 1.0 |
| ; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0 |
| ; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 |
| ; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 |
| ; GFX9-NEXT: .LBB11_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v6f64_to_v12f32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB11_2 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_f64 v[10:11], v[10:11], 1.0 |
| ; GFX11-NEXT: v_add_f64 v[8:9], v[8:9], 1.0 |
| ; GFX11-NEXT: v_add_f64 v[6:7], v[6:7], 1.0 |
| ; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0 |
| ; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 |
| ; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 |
| ; GFX11-NEXT: .LBB11_2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <6 x double> %a, splat (double 1.000000e+00) |
| %a2 = bitcast <6 x double> %a1 to <12 x float> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <6 x double> %a to <12 x float> |
| br label %end |
| |
| end: |
| %phi = phi <12 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <12 x float> %phi |
| } |
| |
| define <6 x i64> @bitcast_v12f32_to_v6i64(<12 x float> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v12f32_to_v6i64: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB12_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.true |
| ; GCN-NEXT: v_add_f32_e32 v11, 1.0, v11 |
| ; GCN-NEXT: v_add_f32_e32 v10, 1.0, v10 |
| ; GCN-NEXT: v_add_f32_e32 v9, 1.0, v9 |
| ; GCN-NEXT: v_add_f32_e32 v8, 1.0, v8 |
| ; GCN-NEXT: v_add_f32_e32 v7, 1.0, v7 |
| ; GCN-NEXT: v_add_f32_e32 v6, 1.0, v6 |
| ; GCN-NEXT: v_add_f32_e32 v5, 1.0, v5 |
| ; GCN-NEXT: v_add_f32_e32 v4, 1.0, v4 |
| ; GCN-NEXT: v_add_f32_e32 v3, 1.0, v3 |
| ; GCN-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; GCN-NEXT: v_add_f32_e32 v1, 1.0, v1 |
| ; GCN-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GCN-NEXT: .LBB12_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v12f32_to_v6i64: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB12_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_f32_e32 v11, 1.0, v11 |
| ; VI-NEXT: v_add_f32_e32 v10, 1.0, v10 |
| ; VI-NEXT: v_add_f32_e32 v9, 1.0, v9 |
| ; VI-NEXT: v_add_f32_e32 v8, 1.0, v8 |
| ; VI-NEXT: v_add_f32_e32 v7, 1.0, v7 |
| ; VI-NEXT: v_add_f32_e32 v6, 1.0, v6 |
| ; VI-NEXT: v_add_f32_e32 v5, 1.0, v5 |
| ; VI-NEXT: v_add_f32_e32 v4, 1.0, v4 |
| ; VI-NEXT: v_add_f32_e32 v3, 1.0, v3 |
| ; VI-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; VI-NEXT: v_add_f32_e32 v1, 1.0, v1 |
| ; VI-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; VI-NEXT: .LBB12_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v12f32_to_v6i64: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB12_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_f32_e32 v11, 1.0, v11 |
| ; GFX9-NEXT: v_add_f32_e32 v10, 1.0, v10 |
| ; GFX9-NEXT: v_add_f32_e32 v9, 1.0, v9 |
| ; GFX9-NEXT: v_add_f32_e32 v8, 1.0, v8 |
| ; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v7 |
| ; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v6 |
| ; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v5 |
| ; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4 |
| ; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v3 |
| ; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1 |
| ; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GFX9-NEXT: .LBB12_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v12f32_to_v6i64: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_dual_add_f32 v11, 1.0, v11 :: v_dual_add_f32 v10, 1.0, v10 |
| ; GFX11-NEXT: v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8 |
| ; GFX11-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6 |
| ; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4 |
| ; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2 |
| ; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0 |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <12 x float> %a, splat (float 1.000000e+00) |
| %a2 = bitcast <12 x float> %a1 to <6 x i64> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <12 x float> %a to <6 x i64> |
| br label %end |
| |
| end: |
| %phi = phi <6 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <6 x i64> %phi |
| } |
| |
| define <12 x float> @bitcast_v6i64_to_v12f32(<6 x i64> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v6i64_to_v12f32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB13_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v10, vcc, 3, v10 |
| ; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc |
| ; GCN-NEXT: v_add_i32_e32 v8, vcc, 3, v8 |
| ; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc |
| ; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v6 |
| ; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v4 |
| ; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v2 |
| ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0 |
| ; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc |
| ; GCN-NEXT: .LBB13_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v6i64_to_v12f32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB13_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10 |
| ; VI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc |
| ; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8 |
| ; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc |
| ; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6 |
| ; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4 |
| ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2 |
| ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0 |
| ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc |
| ; VI-NEXT: .LBB13_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v6i64_to_v12f32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB13_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, 3, v10 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc |
| ; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 3, v8 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc |
| ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 3, v6 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc |
| ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v4 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc |
| ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v2 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc |
| ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc |
| ; GFX9-NEXT: .LBB13_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v6i64_to_v12f32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB13_2 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_co_u32 v10, vcc_lo, v10, 3 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) |
| ; GFX11-NEXT: v_add_co_ci_u32_e64 v11, null, 0, v11, vcc_lo |
| ; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, v8, 3 |
| ; GFX11-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo |
| ; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v6, 3 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) |
| ; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo |
| ; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 3 |
| ; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo |
| ; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) |
| ; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo |
| ; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3 |
| ; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo |
| ; GFX11-NEXT: .LBB13_2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <6 x i64> %a, splat (i64 3) |
| %a2 = bitcast <6 x i64> %a1 to <12 x float> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <6 x i64> %a to <12 x float> |
| br label %end |
| |
| end: |
| %phi = phi <12 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <12 x float> %phi |
| } |
| |
| define <24 x i16> @bitcast_v12f32_to_v24i16(<12 x float> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v12f32_to_v24i16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v22, v11 |
| ; GCN-NEXT: v_mov_b32_e32 v20, v10 |
| ; GCN-NEXT: v_mov_b32_e32 v18, v9 |
| ; GCN-NEXT: v_mov_b32_e32 v16, v8 |
| ; GCN-NEXT: v_mov_b32_e32 v14, v7 |
| ; GCN-NEXT: v_mov_b32_e32 v24, v6 |
| ; GCN-NEXT: v_mov_b32_e32 v10, v5 |
| ; GCN-NEXT: v_mov_b32_e32 v8, v4 |
| ; GCN-NEXT: v_mov_b32_e32 v6, v3 |
| ; GCN-NEXT: v_mov_b32_e32 v4, v2 |
| ; GCN-NEXT: v_mov_b32_e32 v2, v1 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr9 |
| ; GCN-NEXT: ; implicit-def: $vgpr11 |
| ; GCN-NEXT: ; implicit-def: $vgpr13 |
| ; GCN-NEXT: ; implicit-def: $vgpr15 |
| ; GCN-NEXT: ; implicit-def: $vgpr17 |
| ; GCN-NEXT: ; implicit-def: $vgpr19 |
| ; GCN-NEXT: ; implicit-def: $vgpr21 |
| ; GCN-NEXT: ; implicit-def: $vgpr23 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB14_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.false |
| ; GCN-NEXT: v_alignbit_b32 v21, v22, v20, 16 |
| ; GCN-NEXT: v_alignbit_b32 v17, v18, v16, 16 |
| ; GCN-NEXT: v_alignbit_b32 v13, v14, v24, 16 |
| ; GCN-NEXT: v_alignbit_b32 v9, v10, v8, 16 |
| ; GCN-NEXT: v_alignbit_b32 v5, v6, v4, 16 |
| ; GCN-NEXT: v_alignbit_b32 v1, v2, v0, 16 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v22 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v18 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v14 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v10 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v6 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v2 |
| ; GCN-NEXT: .LBB14_2: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB14_4 |
| ; GCN-NEXT: ; %bb.3: ; %cmp.true |
| ; GCN-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; GCN-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GCN-NEXT: v_add_f32_e32 v6, 1.0, v6 |
| ; GCN-NEXT: v_add_f32_e32 v4, 1.0, v4 |
| ; GCN-NEXT: v_add_f32_e32 v10, 1.0, v10 |
| ; GCN-NEXT: v_add_f32_e32 v8, 1.0, v8 |
| ; GCN-NEXT: v_add_f32_e32 v14, 1.0, v14 |
| ; GCN-NEXT: v_add_f32_e32 v24, 1.0, v24 |
| ; GCN-NEXT: v_add_f32_e32 v18, 1.0, v18 |
| ; GCN-NEXT: v_add_f32_e32 v16, 1.0, v16 |
| ; GCN-NEXT: v_add_f32_e32 v22, 1.0, v22 |
| ; GCN-NEXT: v_add_f32_e32 v20, 1.0, v20 |
| ; GCN-NEXT: v_alignbit_b32 v21, v22, v20, 16 |
| ; GCN-NEXT: v_alignbit_b32 v17, v18, v16, 16 |
| ; GCN-NEXT: v_alignbit_b32 v13, v14, v24, 16 |
| ; GCN-NEXT: v_alignbit_b32 v9, v10, v8, 16 |
| ; GCN-NEXT: v_alignbit_b32 v5, v6, v4, 16 |
| ; GCN-NEXT: v_alignbit_b32 v1, v2, v0, 16 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v22 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v18 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v14 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v10 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v6 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v2 |
| ; GCN-NEXT: .LBB14_4: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: v_mov_b32_e32 v12, v24 |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v12f32_to_v24i16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB14_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_f32_e32 v11, 1.0, v11 |
| ; VI-NEXT: v_add_f32_e32 v10, 1.0, v10 |
| ; VI-NEXT: v_add_f32_e32 v9, 1.0, v9 |
| ; VI-NEXT: v_add_f32_e32 v8, 1.0, v8 |
| ; VI-NEXT: v_add_f32_e32 v7, 1.0, v7 |
| ; VI-NEXT: v_add_f32_e32 v6, 1.0, v6 |
| ; VI-NEXT: v_add_f32_e32 v5, 1.0, v5 |
| ; VI-NEXT: v_add_f32_e32 v4, 1.0, v4 |
| ; VI-NEXT: v_add_f32_e32 v3, 1.0, v3 |
| ; VI-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; VI-NEXT: v_add_f32_e32 v1, 1.0, v1 |
| ; VI-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; VI-NEXT: .LBB14_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v12f32_to_v24i16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB14_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_f32_e32 v11, 1.0, v11 |
| ; GFX9-NEXT: v_add_f32_e32 v10, 1.0, v10 |
| ; GFX9-NEXT: v_add_f32_e32 v9, 1.0, v9 |
| ; GFX9-NEXT: v_add_f32_e32 v8, 1.0, v8 |
| ; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v7 |
| ; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v6 |
| ; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v5 |
| ; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4 |
| ; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v3 |
| ; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1 |
| ; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GFX9-NEXT: .LBB14_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v12f32_to_v24i16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_dual_add_f32 v11, 1.0, v11 :: v_dual_add_f32 v10, 1.0, v10 |
| ; GFX11-NEXT: v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8 |
| ; GFX11-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6 |
| ; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4 |
| ; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2 |
| ; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0 |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <12 x float> %a, splat (float 1.000000e+00) |
| %a2 = bitcast <12 x float> %a1 to <24 x i16> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <12 x float> %a to <24 x i16> |
| br label %end |
| |
| end: |
| %phi = phi <24 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <24 x i16> %phi |
| } |
| |
| define <12 x float> @bitcast_v24i16_to_v12f32(<24 x i16> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v24i16_to_v12f32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v30, v10 |
| ; GCN-NEXT: v_mov_b32_e32 v29, v8 |
| ; GCN-NEXT: v_mov_b32_e32 v28, v6 |
| ; GCN-NEXT: v_mov_b32_e32 v27, v4 |
| ; GCN-NEXT: v_mov_b32_e32 v26, v2 |
| ; GCN-NEXT: v_mov_b32_e32 v25, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v34, 16, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v35, 16, v3 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v24, 16, v5 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v31, 16, v7 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v32, 16, v9 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v33, 16, v11 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v13, 16, v13 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v17, 16, v17 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v19, 16, v19 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v21, 16, v21 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v23, 16, v23 |
| ; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB15_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB15_4 |
| ; GCN-NEXT: .LBB15_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB15_3: ; %cmp.false |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v25 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v26 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v34 |
| ; GCN-NEXT: v_or_b32_e32 v1, v1, v35 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v27 |
| ; GCN-NEXT: v_and_b32_e32 v3, 0xffff, v28 |
| ; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v29 |
| ; GCN-NEXT: v_and_b32_e32 v5, 0xffff, v30 |
| ; GCN-NEXT: v_and_b32_e32 v6, 0xffff, v12 |
| ; GCN-NEXT: v_and_b32_e32 v7, 0xffff, v14 |
| ; GCN-NEXT: v_and_b32_e32 v8, 0xffff, v16 |
| ; GCN-NEXT: v_and_b32_e32 v9, 0xffff, v18 |
| ; GCN-NEXT: v_and_b32_e32 v10, 0xffff, v20 |
| ; GCN-NEXT: v_and_b32_e32 v11, 0xffff, v22 |
| ; GCN-NEXT: v_or_b32_e32 v2, v2, v24 |
| ; GCN-NEXT: v_or_b32_e32 v3, v3, v31 |
| ; GCN-NEXT: v_or_b32_e32 v4, v4, v32 |
| ; GCN-NEXT: v_or_b32_e32 v5, v5, v33 |
| ; GCN-NEXT: v_or_b32_e32 v6, v6, v13 |
| ; GCN-NEXT: v_or_b32_e32 v7, v7, v15 |
| ; GCN-NEXT: v_or_b32_e32 v8, v8, v17 |
| ; GCN-NEXT: v_or_b32_e32 v9, v9, v19 |
| ; GCN-NEXT: v_or_b32_e32 v10, v10, v21 |
| ; GCN-NEXT: v_or_b32_e32 v11, v11, v23 |
| ; GCN-NEXT: ; implicit-def: $vgpr25 |
| ; GCN-NEXT: ; implicit-def: $vgpr26 |
| ; GCN-NEXT: ; implicit-def: $vgpr27 |
| ; GCN-NEXT: ; implicit-def: $vgpr28 |
| ; GCN-NEXT: ; implicit-def: $vgpr29 |
| ; GCN-NEXT: ; implicit-def: $vgpr30 |
| ; GCN-NEXT: ; implicit-def: $vgpr12 |
| ; GCN-NEXT: ; implicit-def: $vgpr14 |
| ; GCN-NEXT: ; implicit-def: $vgpr16 |
| ; GCN-NEXT: ; implicit-def: $vgpr18 |
| ; GCN-NEXT: ; implicit-def: $vgpr20 |
| ; GCN-NEXT: ; implicit-def: $vgpr22 |
| ; GCN-NEXT: ; implicit-def: $vgpr34 |
| ; GCN-NEXT: ; implicit-def: $vgpr35 |
| ; GCN-NEXT: ; implicit-def: $vgpr24 |
| ; GCN-NEXT: ; implicit-def: $vgpr31 |
| ; GCN-NEXT: ; implicit-def: $vgpr32 |
| ; GCN-NEXT: ; implicit-def: $vgpr33 |
| ; GCN-NEXT: ; implicit-def: $vgpr13 |
| ; GCN-NEXT: ; implicit-def: $vgpr15 |
| ; GCN-NEXT: ; implicit-def: $vgpr17 |
| ; GCN-NEXT: ; implicit-def: $vgpr19 |
| ; GCN-NEXT: ; implicit-def: $vgpr21 |
| ; GCN-NEXT: ; implicit-def: $vgpr23 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB15_2 |
| ; GCN-NEXT: .LBB15_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v25 |
| ; GCN-NEXT: s_mov_b32 s6, 0x30000 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v26 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v27 |
| ; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v28 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v29 |
| ; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v30 |
| ; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v12 |
| ; GCN-NEXT: v_add_i32_e32 v7, vcc, 3, v14 |
| ; GCN-NEXT: v_add_i32_e32 v8, vcc, 3, v16 |
| ; GCN-NEXT: v_add_i32_e32 v9, vcc, 3, v18 |
| ; GCN-NEXT: v_add_i32_e32 v10, vcc, 3, v20 |
| ; GCN-NEXT: v_add_i32_e32 v11, vcc, 3, v22 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v1 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2 |
| ; GCN-NEXT: v_and_b32_e32 v3, 0xffff, v3 |
| ; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v4 |
| ; GCN-NEXT: v_and_b32_e32 v5, 0xffff, v5 |
| ; GCN-NEXT: v_and_b32_e32 v6, 0xffff, v6 |
| ; GCN-NEXT: v_and_b32_e32 v7, 0xffff, v7 |
| ; GCN-NEXT: v_and_b32_e32 v8, 0xffff, v8 |
| ; GCN-NEXT: v_and_b32_e32 v9, 0xffff, v9 |
| ; GCN-NEXT: v_and_b32_e32 v10, 0xffff, v10 |
| ; GCN-NEXT: v_and_b32_e32 v11, 0xffff, v11 |
| ; GCN-NEXT: v_or_b32_e32 v0, v34, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v35, v1 |
| ; GCN-NEXT: v_or_b32_e32 v2, v24, v2 |
| ; GCN-NEXT: v_or_b32_e32 v3, v31, v3 |
| ; GCN-NEXT: v_or_b32_e32 v4, v32, v4 |
| ; GCN-NEXT: v_or_b32_e32 v5, v33, v5 |
| ; GCN-NEXT: v_or_b32_e32 v6, v13, v6 |
| ; GCN-NEXT: v_or_b32_e32 v7, v15, v7 |
| ; GCN-NEXT: v_or_b32_e32 v8, v17, v8 |
| ; GCN-NEXT: v_or_b32_e32 v9, v19, v9 |
| ; GCN-NEXT: v_or_b32_e32 v10, v21, v10 |
| ; GCN-NEXT: v_or_b32_e32 v11, v23, v11 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, s6, v1 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, s6, v2 |
| ; GCN-NEXT: v_add_i32_e32 v3, vcc, s6, v3 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, s6, v4 |
| ; GCN-NEXT: v_add_i32_e32 v5, vcc, s6, v5 |
| ; GCN-NEXT: v_add_i32_e32 v6, vcc, s6, v6 |
| ; GCN-NEXT: v_add_i32_e32 v7, vcc, s6, v7 |
| ; GCN-NEXT: v_add_i32_e32 v8, vcc, s6, v8 |
| ; GCN-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9 |
| ; GCN-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10 |
| ; GCN-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v24i16_to_v12f32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB15_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v13, 3 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v11 |
| ; VI-NEXT: v_add_u16_sdwa v11, v11, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v11, v12, v11 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v10 |
| ; VI-NEXT: v_add_u16_sdwa v10, v10, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v10, v12, v10 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v9 |
| ; VI-NEXT: v_add_u16_sdwa v9, v9, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v9, v12, v9 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v8 |
| ; VI-NEXT: v_add_u16_sdwa v8, v8, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v8, v12, v8 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v7 |
| ; VI-NEXT: v_add_u16_sdwa v7, v7, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v7, v12, v7 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v6 |
| ; VI-NEXT: v_add_u16_sdwa v6, v6, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v6, v12, v6 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v5 |
| ; VI-NEXT: v_add_u16_sdwa v5, v5, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v5, v12, v5 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v4 |
| ; VI-NEXT: v_add_u16_sdwa v4, v4, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v4, v12, v4 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v3 |
| ; VI-NEXT: v_add_u16_sdwa v3, v3, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v3, v12, v3 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v2 |
| ; VI-NEXT: v_add_u16_sdwa v2, v2, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v2, v12, v2 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v1 |
| ; VI-NEXT: v_add_u16_sdwa v1, v1, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v1, v12, v1 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v0 |
| ; VI-NEXT: v_add_u16_sdwa v0, v0, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v0, v12, v0 |
| ; VI-NEXT: .LBB15_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v24i16_to_v12f32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB15_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: .LBB15_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v24i16_to_v12f32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB15_2 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: .LBB15_2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <24 x i16> %a, splat (i16 3) |
| %a2 = bitcast <24 x i16> %a1 to <12 x float> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <24 x i16> %a to <12 x float> |
| br label %end |
| |
| end: |
| %phi = phi <12 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <12 x float> %phi |
| } |
| |
| define <24 x half> @bitcast_v12f32_to_v24f16(<12 x float> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v12f32_to_v24f16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v35, v11 |
| ; GCN-NEXT: v_mov_b32_e32 v34, v10 |
| ; GCN-NEXT: v_mov_b32_e32 v33, v9 |
| ; GCN-NEXT: v_mov_b32_e32 v32, v8 |
| ; GCN-NEXT: v_mov_b32_e32 v31, v7 |
| ; GCN-NEXT: v_mov_b32_e32 v30, v6 |
| ; GCN-NEXT: v_mov_b32_e32 v29, v5 |
| ; GCN-NEXT: v_mov_b32_e32 v28, v4 |
| ; GCN-NEXT: v_mov_b32_e32 v27, v3 |
| ; GCN-NEXT: v_mov_b32_e32 v26, v2 |
| ; GCN-NEXT: v_mov_b32_e32 v25, v1 |
| ; GCN-NEXT: v_mov_b32_e32 v24, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: ; implicit-def: $vgpr6 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr8 |
| ; GCN-NEXT: ; implicit-def: $vgpr9 |
| ; GCN-NEXT: ; implicit-def: $vgpr10 |
| ; GCN-NEXT: ; implicit-def: $vgpr11 |
| ; GCN-NEXT: ; implicit-def: $vgpr12 |
| ; GCN-NEXT: ; implicit-def: $vgpr13 |
| ; GCN-NEXT: ; implicit-def: $vgpr14 |
| ; GCN-NEXT: ; implicit-def: $vgpr15 |
| ; GCN-NEXT: ; implicit-def: $vgpr16 |
| ; GCN-NEXT: ; implicit-def: $vgpr17 |
| ; GCN-NEXT: ; implicit-def: $vgpr18 |
| ; GCN-NEXT: ; implicit-def: $vgpr19 |
| ; GCN-NEXT: ; implicit-def: $vgpr20 |
| ; GCN-NEXT: ; implicit-def: $vgpr21 |
| ; GCN-NEXT: ; implicit-def: $vgpr22 |
| ; GCN-NEXT: ; implicit-def: $vgpr23 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB16_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB16_4 |
| ; GCN-NEXT: .LBB16_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB16_3: ; %cmp.false |
| ; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v35 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v34 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v33 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v32 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v31 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v30 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v29 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v36, 16, v28 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v37, 16, v27 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v38, 16, v26 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v39, 16, v25 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v48, 16, v24 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v22, v35 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v20, v34 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v18, v33 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v16, v32 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v14, v31 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v12, v30 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v10, v29 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v8, v28 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v6, v27 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v4, v26 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v25 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v23, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v21, v1 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v19, v3 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v17, v5 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v15, v7 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v13, v9 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v11, v11 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v9, v36 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v7, v37 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v38 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v39 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v48 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v24 |
| ; GCN-NEXT: ; implicit-def: $vgpr24 |
| ; GCN-NEXT: ; implicit-def: $vgpr25 |
| ; GCN-NEXT: ; implicit-def: $vgpr26 |
| ; GCN-NEXT: ; implicit-def: $vgpr27 |
| ; GCN-NEXT: ; implicit-def: $vgpr28 |
| ; GCN-NEXT: ; implicit-def: $vgpr29 |
| ; GCN-NEXT: ; implicit-def: $vgpr30 |
| ; GCN-NEXT: ; implicit-def: $vgpr31 |
| ; GCN-NEXT: ; implicit-def: $vgpr32 |
| ; GCN-NEXT: ; implicit-def: $vgpr33 |
| ; GCN-NEXT: ; implicit-def: $vgpr34 |
| ; GCN-NEXT: ; implicit-def: $vgpr35 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB16_2 |
| ; GCN-NEXT: .LBB16_4: ; %cmp.true |
| ; GCN-NEXT: v_add_f32_e32 v1, 1.0, v24 |
| ; GCN-NEXT: v_add_f32_e32 v3, 1.0, v25 |
| ; GCN-NEXT: v_add_f32_e32 v5, 1.0, v26 |
| ; GCN-NEXT: v_add_f32_e32 v7, 1.0, v27 |
| ; GCN-NEXT: v_add_f32_e32 v9, 1.0, v28 |
| ; GCN-NEXT: v_add_f32_e32 v11, 1.0, v29 |
| ; GCN-NEXT: v_add_f32_e32 v13, 1.0, v30 |
| ; GCN-NEXT: v_add_f32_e32 v15, 1.0, v31 |
| ; GCN-NEXT: v_add_f32_e32 v17, 1.0, v32 |
| ; GCN-NEXT: v_add_f32_e32 v19, 1.0, v33 |
| ; GCN-NEXT: v_add_f32_e32 v21, 1.0, v34 |
| ; GCN-NEXT: v_add_f32_e32 v23, 1.0, v35 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v22, v23 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v20, v21 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v18, v19 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v16, v17 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v14, v15 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v12, v13 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v10, v11 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v8, v9 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v6, v7 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v4, v5 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v3 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v1 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v23 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v21, 16, v21 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v19 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v17, 16, v17 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v15 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v13 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v11 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v9 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v7 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v3 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v1 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v23, v23 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v21, v21 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v19, v19 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v17, v17 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v15, v15 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v13, v13 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v11, v11 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v9, v9 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v7, v7 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v5 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v3 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v12f32_to_v24f16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB16_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_f32_e32 v11, 1.0, v11 |
| ; VI-NEXT: v_add_f32_e32 v10, 1.0, v10 |
| ; VI-NEXT: v_add_f32_e32 v9, 1.0, v9 |
| ; VI-NEXT: v_add_f32_e32 v8, 1.0, v8 |
| ; VI-NEXT: v_add_f32_e32 v7, 1.0, v7 |
| ; VI-NEXT: v_add_f32_e32 v6, 1.0, v6 |
| ; VI-NEXT: v_add_f32_e32 v5, 1.0, v5 |
| ; VI-NEXT: v_add_f32_e32 v4, 1.0, v4 |
| ; VI-NEXT: v_add_f32_e32 v3, 1.0, v3 |
| ; VI-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; VI-NEXT: v_add_f32_e32 v1, 1.0, v1 |
| ; VI-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; VI-NEXT: .LBB16_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v12f32_to_v24f16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB16_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_f32_e32 v11, 1.0, v11 |
| ; GFX9-NEXT: v_add_f32_e32 v10, 1.0, v10 |
| ; GFX9-NEXT: v_add_f32_e32 v9, 1.0, v9 |
| ; GFX9-NEXT: v_add_f32_e32 v8, 1.0, v8 |
| ; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v7 |
| ; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v6 |
| ; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v5 |
| ; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4 |
| ; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v3 |
| ; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1 |
| ; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GFX9-NEXT: .LBB16_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v12f32_to_v24f16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_dual_add_f32 v11, 1.0, v11 :: v_dual_add_f32 v10, 1.0, v10 |
| ; GFX11-NEXT: v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8 |
| ; GFX11-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6 |
| ; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4 |
| ; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2 |
| ; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0 |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <12 x float> %a, splat (float 1.000000e+00) |
| %a2 = bitcast <12 x float> %a1 to <24 x half> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <12 x float> %a to <24 x half> |
| br label %end |
| |
| end: |
| %phi = phi <24 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <24 x half> %phi |
| } |
| |
| define <12 x float> @bitcast_v24f16_to_v12f32(<24 x half> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v24f16_to_v12f32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v48, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v39, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v38, v3 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v37, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v36, v5 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v32, v4 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v35, v7 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v30, v6 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v34, v9 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v28, v8 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v33, v11 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v26, v10 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v31, v13 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v25, v12 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v29, v15 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v24, v14 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v27, v17 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v16, v16 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v19, v19 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v14, v18 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v17, v21 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v13, v20 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v15, v23 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v12, v22 |
| ; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB17_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB17_4 |
| ; GCN-NEXT: .LBB17_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB17_3: ; %cmp.false |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v48 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v38 |
| ; GCN-NEXT: v_or_b32_e32 v0, v39, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v37, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v36 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v35 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v34 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v33 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v31 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v29 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v27 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v9, 16, v19 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v17 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v15 |
| ; GCN-NEXT: v_or_b32_e32 v2, v32, v2 |
| ; GCN-NEXT: v_or_b32_e32 v3, v30, v3 |
| ; GCN-NEXT: v_or_b32_e32 v4, v28, v4 |
| ; GCN-NEXT: v_or_b32_e32 v5, v26, v5 |
| ; GCN-NEXT: v_or_b32_e32 v6, v25, v6 |
| ; GCN-NEXT: v_or_b32_e32 v7, v24, v7 |
| ; GCN-NEXT: v_or_b32_e32 v8, v16, v8 |
| ; GCN-NEXT: v_or_b32_e32 v9, v14, v9 |
| ; GCN-NEXT: v_or_b32_e32 v10, v13, v10 |
| ; GCN-NEXT: v_or_b32_e32 v11, v12, v11 |
| ; GCN-NEXT: ; implicit-def: $vgpr48 |
| ; GCN-NEXT: ; implicit-def: $vgpr39 |
| ; GCN-NEXT: ; implicit-def: $vgpr38 |
| ; GCN-NEXT: ; implicit-def: $vgpr37 |
| ; GCN-NEXT: ; implicit-def: $vgpr36 |
| ; GCN-NEXT: ; implicit-def: $vgpr32 |
| ; GCN-NEXT: ; implicit-def: $vgpr35 |
| ; GCN-NEXT: ; implicit-def: $vgpr30 |
| ; GCN-NEXT: ; implicit-def: $vgpr34 |
| ; GCN-NEXT: ; implicit-def: $vgpr28 |
| ; GCN-NEXT: ; implicit-def: $vgpr33 |
| ; GCN-NEXT: ; implicit-def: $vgpr26 |
| ; GCN-NEXT: ; implicit-def: $vgpr31 |
| ; GCN-NEXT: ; implicit-def: $vgpr25 |
| ; GCN-NEXT: ; implicit-def: $vgpr29 |
| ; GCN-NEXT: ; implicit-def: $vgpr24 |
| ; GCN-NEXT: ; implicit-def: $vgpr27 |
| ; GCN-NEXT: ; implicit-def: $vgpr16 |
| ; GCN-NEXT: ; implicit-def: $vgpr19 |
| ; GCN-NEXT: ; implicit-def: $vgpr14 |
| ; GCN-NEXT: ; implicit-def: $vgpr17 |
| ; GCN-NEXT: ; implicit-def: $vgpr13 |
| ; GCN-NEXT: ; implicit-def: $vgpr15 |
| ; GCN-NEXT: ; implicit-def: $vgpr12 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB17_2 |
| ; GCN-NEXT: .LBB17_4: ; %cmp.true |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v48 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v39 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v38 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v37 |
| ; GCN-NEXT: v_add_f32_e32 v0, 0x38000000, v0 |
| ; GCN-NEXT: v_add_f32_e32 v1, 0x38000000, v1 |
| ; GCN-NEXT: v_add_f32_e32 v2, 0x38000000, v2 |
| ; GCN-NEXT: v_add_f32_e32 v3, 0x38000000, v3 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 |
| ; GCN-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v3, v2 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v36 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v32 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v4, v35 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v30 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v6, v34 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v7, v28 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v8, v33 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v9, v26 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v10, v31 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v11, v25 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v18, v29 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v20, v24 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v21, v27 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v16, v16 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v19, v19 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v14, v14 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v17, v17 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v13, v13 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v15, v15 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v12, v12 |
| ; GCN-NEXT: v_add_f32_e32 v2, 0x38000000, v2 |
| ; GCN-NEXT: v_add_f32_e32 v3, 0x38000000, v3 |
| ; GCN-NEXT: v_add_f32_e32 v4, 0x38000000, v4 |
| ; GCN-NEXT: v_add_f32_e32 v5, 0x38000000, v5 |
| ; GCN-NEXT: v_add_f32_e32 v6, 0x38000000, v6 |
| ; GCN-NEXT: v_add_f32_e32 v7, 0x38000000, v7 |
| ; GCN-NEXT: v_add_f32_e32 v8, 0x38000000, v8 |
| ; GCN-NEXT: v_add_f32_e32 v9, 0x38000000, v9 |
| ; GCN-NEXT: v_add_f32_e32 v10, 0x38000000, v10 |
| ; GCN-NEXT: v_add_f32_e32 v11, 0x38000000, v11 |
| ; GCN-NEXT: v_add_f32_e32 v18, 0x38000000, v18 |
| ; GCN-NEXT: v_add_f32_e32 v20, 0x38000000, v20 |
| ; GCN-NEXT: v_add_f32_e32 v21, 0x38000000, v21 |
| ; GCN-NEXT: v_add_f32_e32 v16, 0x38000000, v16 |
| ; GCN-NEXT: v_add_f32_e32 v19, 0x38000000, v19 |
| ; GCN-NEXT: v_add_f32_e32 v14, 0x38000000, v14 |
| ; GCN-NEXT: v_add_f32_e32 v17, 0x38000000, v17 |
| ; GCN-NEXT: v_add_f32_e32 v13, 0x38000000, v13 |
| ; GCN-NEXT: v_add_f32_e32 v15, 0x38000000, v15 |
| ; GCN-NEXT: v_add_f32_e32 v12, 0x38000000, v12 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v4, v4 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v5, v5 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v6, v6 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v7, v7 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v8, v8 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v9, v9 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v10, v10 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v11, v11 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v18, v18 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v20, v20 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v21, v21 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v16, v16 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v19, v19 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v14, v14 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v17, v17 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v13, v13 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v15, v15 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v12, v12 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v4 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v6 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v8 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v10 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v18, 16, v18 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v21, 16, v21 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v19, 16, v19 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v17, 16, v17 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v15, 16, v15 |
| ; GCN-NEXT: v_or_b32_e32 v2, v3, v2 |
| ; GCN-NEXT: v_or_b32_e32 v3, v5, v4 |
| ; GCN-NEXT: v_or_b32_e32 v4, v7, v6 |
| ; GCN-NEXT: v_or_b32_e32 v5, v9, v8 |
| ; GCN-NEXT: v_or_b32_e32 v6, v11, v10 |
| ; GCN-NEXT: v_or_b32_e32 v7, v20, v18 |
| ; GCN-NEXT: v_or_b32_e32 v8, v16, v21 |
| ; GCN-NEXT: v_or_b32_e32 v9, v14, v19 |
| ; GCN-NEXT: v_or_b32_e32 v10, v13, v17 |
| ; GCN-NEXT: v_or_b32_e32 v11, v12, v15 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v24f16_to_v12f32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB17_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v12, 0x200 |
| ; VI-NEXT: v_add_f16_sdwa v13, v11, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v11, 0x200, v11 |
| ; VI-NEXT: v_or_b32_e32 v11, v11, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v10, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v10, 0x200, v10 |
| ; VI-NEXT: v_or_b32_e32 v10, v10, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v9, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v9, 0x200, v9 |
| ; VI-NEXT: v_or_b32_e32 v9, v9, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v8, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v8, 0x200, v8 |
| ; VI-NEXT: v_or_b32_e32 v8, v8, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v7, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v7, 0x200, v7 |
| ; VI-NEXT: v_or_b32_e32 v7, v7, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v6, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v6, 0x200, v6 |
| ; VI-NEXT: v_or_b32_e32 v6, v6, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v5, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v5, 0x200, v5 |
| ; VI-NEXT: v_or_b32_e32 v5, v5, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v4, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v4, 0x200, v4 |
| ; VI-NEXT: v_or_b32_e32 v4, v4, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v3, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v3, 0x200, v3 |
| ; VI-NEXT: v_or_b32_e32 v3, v3, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v2, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v2, 0x200, v2 |
| ; VI-NEXT: v_or_b32_e32 v2, v2, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v1, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v1, 0x200, v1 |
| ; VI-NEXT: v_add_f16_sdwa v12, v0, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v0, 0x200, v0 |
| ; VI-NEXT: v_or_b32_e32 v1, v1, v13 |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v12 |
| ; VI-NEXT: .LBB17_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v24f16_to_v12f32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB17_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: s_movk_i32 s6, 0x200 |
| ; GFX9-NEXT: v_pk_add_f16 v11, v11, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v10, v10, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v9, v9, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v8, v8, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: .LBB17_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v24f16_to_v12f32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB17_2 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1] |
| ; GFX11-NEXT: .LBB17_2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <24 x half> %a, splat (half 0xH0200) |
| %a2 = bitcast <24 x half> %a1 to <12 x float> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <24 x half> %a to <12 x float> |
| br label %end |
| |
| end: |
| %phi = phi <12 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <12 x float> %phi |
| } |
| |
| define <6 x i64> @bitcast_v6f64_to_v6i64(<6 x double> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v6f64_to_v6i64: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB18_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.true |
| ; GCN-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 |
| ; GCN-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 |
| ; GCN-NEXT: v_add_f64 v[4:5], v[4:5], 1.0 |
| ; GCN-NEXT: v_add_f64 v[6:7], v[6:7], 1.0 |
| ; GCN-NEXT: v_add_f64 v[8:9], v[8:9], 1.0 |
| ; GCN-NEXT: v_add_f64 v[10:11], v[10:11], 1.0 |
| ; GCN-NEXT: .LBB18_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v6f64_to_v6i64: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB18_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 |
| ; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 |
| ; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0 |
| ; VI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0 |
| ; VI-NEXT: v_add_f64 v[8:9], v[8:9], 1.0 |
| ; VI-NEXT: v_add_f64 v[10:11], v[10:11], 1.0 |
| ; VI-NEXT: .LBB18_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v6f64_to_v6i64: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB18_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 |
| ; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 |
| ; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0 |
| ; GFX9-NEXT: v_add_f64 v[6:7], v[6:7], 1.0 |
| ; GFX9-NEXT: v_add_f64 v[8:9], v[8:9], 1.0 |
| ; GFX9-NEXT: v_add_f64 v[10:11], v[10:11], 1.0 |
| ; GFX9-NEXT: .LBB18_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v6f64_to_v6i64: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB18_2 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 |
| ; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 |
| ; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0 |
| ; GFX11-NEXT: v_add_f64 v[6:7], v[6:7], 1.0 |
| ; GFX11-NEXT: v_add_f64 v[8:9], v[8:9], 1.0 |
| ; GFX11-NEXT: v_add_f64 v[10:11], v[10:11], 1.0 |
| ; GFX11-NEXT: .LBB18_2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <6 x double> %a, splat (double 1.000000e+00) |
| %a2 = bitcast <6 x double> %a1 to <6 x i64> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <6 x double> %a to <6 x i64> |
| br label %end |
| |
| end: |
| %phi = phi <6 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <6 x i64> %phi |
| } |
| |
| define <6 x double> @bitcast_v6i64_to_v6f64(<6 x i64> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v6i64_to_v6f64: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB19_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0 |
| ; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v2 |
| ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v4 |
| ; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc |
| ; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v6 |
| ; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc |
| ; GCN-NEXT: v_add_i32_e32 v8, vcc, 3, v8 |
| ; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc |
| ; GCN-NEXT: v_add_i32_e32 v10, vcc, 3, v10 |
| ; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc |
| ; GCN-NEXT: .LBB19_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v6i64_to_v6f64: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB19_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0 |
| ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2 |
| ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4 |
| ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc |
| ; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6 |
| ; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc |
| ; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8 |
| ; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc |
| ; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10 |
| ; VI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc |
| ; VI-NEXT: .LBB19_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v6i64_to_v6f64: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB19_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc |
| ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v2 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc |
| ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v4 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc |
| ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 3, v6 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc |
| ; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 3, v8 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc |
| ; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, 3, v10 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc |
| ; GFX9-NEXT: .LBB19_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v6i64_to_v6f64: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB19_2 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) |
| ; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo |
| ; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3 |
| ; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo |
| ; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 3 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) |
| ; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo |
| ; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v6, 3 |
| ; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo |
| ; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, v8, 3 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) |
| ; GFX11-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo |
| ; GFX11-NEXT: v_add_co_u32 v10, vcc_lo, v10, 3 |
| ; GFX11-NEXT: v_add_co_ci_u32_e64 v11, null, 0, v11, vcc_lo |
| ; GFX11-NEXT: .LBB19_2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <6 x i64> %a, splat (i64 3) |
| %a2 = bitcast <6 x i64> %a1 to <6 x double> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <6 x i64> %a to <6 x double> |
| br label %end |
| |
| end: |
| %phi = phi <6 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <6 x double> %phi |
| } |
| |
| define <24 x i16> @bitcast_v6f64_to_v24i16(<6 x double> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v6f64_to_v24i16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v34, v11 |
| ; GCN-NEXT: v_mov_b32_e32 v33, v10 |
| ; GCN-NEXT: v_mov_b32_e32 v32, v9 |
| ; GCN-NEXT: v_mov_b32_e32 v31, v8 |
| ; GCN-NEXT: v_mov_b32_e32 v30, v7 |
| ; GCN-NEXT: v_mov_b32_e32 v29, v6 |
| ; GCN-NEXT: v_mov_b32_e32 v28, v5 |
| ; GCN-NEXT: v_mov_b32_e32 v27, v4 |
| ; GCN-NEXT: v_mov_b32_e32 v26, v3 |
| ; GCN-NEXT: v_mov_b32_e32 v25, v2 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GCN-NEXT: ; implicit-def: $vgpr24 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr9 |
| ; GCN-NEXT: ; implicit-def: $vgpr11 |
| ; GCN-NEXT: ; implicit-def: $vgpr13 |
| ; GCN-NEXT: ; implicit-def: $vgpr15 |
| ; GCN-NEXT: ; implicit-def: $vgpr17 |
| ; GCN-NEXT: ; implicit-def: $vgpr19 |
| ; GCN-NEXT: ; implicit-def: $vgpr21 |
| ; GCN-NEXT: ; implicit-def: $vgpr23 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB20_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.false |
| ; GCN-NEXT: v_alignbit_b32 v21, v34, v33, 16 |
| ; GCN-NEXT: v_alignbit_b32 v17, v32, v31, 16 |
| ; GCN-NEXT: v_alignbit_b32 v13, v30, v29, 16 |
| ; GCN-NEXT: v_alignbit_b32 v9, v28, v27, 16 |
| ; GCN-NEXT: v_alignbit_b32 v5, v26, v25, 16 |
| ; GCN-NEXT: v_alignbit_b32 v24, v1, v0, 16 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v34 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v32 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v30 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v28 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v26 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v1 |
| ; GCN-NEXT: .LBB20_2: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB20_4 |
| ; GCN-NEXT: ; %bb.3: ; %cmp.true |
| ; GCN-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 |
| ; GCN-NEXT: v_add_f64 v[25:26], v[25:26], 1.0 |
| ; GCN-NEXT: v_add_f64 v[27:28], v[27:28], 1.0 |
| ; GCN-NEXT: v_add_f64 v[29:30], v[29:30], 1.0 |
| ; GCN-NEXT: v_add_f64 v[31:32], v[31:32], 1.0 |
| ; GCN-NEXT: v_add_f64 v[33:34], v[33:34], 1.0 |
| ; GCN-NEXT: v_alignbit_b32 v21, v34, v33, 16 |
| ; GCN-NEXT: v_alignbit_b32 v17, v32, v31, 16 |
| ; GCN-NEXT: v_alignbit_b32 v13, v30, v29, 16 |
| ; GCN-NEXT: v_alignbit_b32 v9, v28, v27, 16 |
| ; GCN-NEXT: v_alignbit_b32 v5, v26, v25, 16 |
| ; GCN-NEXT: v_alignbit_b32 v24, v1, v0, 16 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v34 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v32 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v30 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v28 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v26 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v1 |
| ; GCN-NEXT: .LBB20_4: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: v_mov_b32_e32 v2, v1 |
| ; GCN-NEXT: v_mov_b32_e32 v4, v25 |
| ; GCN-NEXT: v_mov_b32_e32 v6, v26 |
| ; GCN-NEXT: v_mov_b32_e32 v8, v27 |
| ; GCN-NEXT: v_mov_b32_e32 v10, v28 |
| ; GCN-NEXT: v_mov_b32_e32 v12, v29 |
| ; GCN-NEXT: v_mov_b32_e32 v14, v30 |
| ; GCN-NEXT: v_mov_b32_e32 v16, v31 |
| ; GCN-NEXT: v_mov_b32_e32 v18, v32 |
| ; GCN-NEXT: v_mov_b32_e32 v20, v33 |
| ; GCN-NEXT: v_mov_b32_e32 v22, v34 |
| ; GCN-NEXT: v_mov_b32_e32 v1, v24 |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v6f64_to_v24i16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB20_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_f64 v[10:11], v[10:11], 1.0 |
| ; VI-NEXT: v_add_f64 v[8:9], v[8:9], 1.0 |
| ; VI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0 |
| ; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0 |
| ; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 |
| ; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 |
| ; VI-NEXT: .LBB20_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v6f64_to_v24i16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB20_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_f64 v[10:11], v[10:11], 1.0 |
| ; GFX9-NEXT: v_add_f64 v[8:9], v[8:9], 1.0 |
| ; GFX9-NEXT: v_add_f64 v[6:7], v[6:7], 1.0 |
| ; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0 |
| ; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 |
| ; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 |
| ; GFX9-NEXT: .LBB20_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v6f64_to_v24i16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB20_2 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_f64 v[10:11], v[10:11], 1.0 |
| ; GFX11-NEXT: v_add_f64 v[8:9], v[8:9], 1.0 |
| ; GFX11-NEXT: v_add_f64 v[6:7], v[6:7], 1.0 |
| ; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0 |
| ; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 |
| ; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 |
| ; GFX11-NEXT: .LBB20_2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <6 x double> %a, splat (double 1.000000e+00) |
| %a2 = bitcast <6 x double> %a1 to <24 x i16> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <6 x double> %a to <24 x i16> |
| br label %end |
| |
| end: |
| %phi = phi <24 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <24 x i16> %phi |
| } |
| |
| define <6 x double> @bitcast_v24i16_to_v6f64(<24 x i16> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v24i16_to_v6f64: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v32, v14 |
| ; GCN-NEXT: v_mov_b32_e32 v31, v12 |
| ; GCN-NEXT: v_mov_b32_e32 v30, v10 |
| ; GCN-NEXT: v_mov_b32_e32 v29, v8 |
| ; GCN-NEXT: v_mov_b32_e32 v28, v6 |
| ; GCN-NEXT: v_mov_b32_e32 v25, v4 |
| ; GCN-NEXT: v_mov_b32_e32 v26, v2 |
| ; GCN-NEXT: v_mov_b32_e32 v27, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v38, 16, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v39, 16, v3 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v24, 16, v5 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v33, 16, v7 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v34, 16, v9 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v35, 16, v11 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v36, 16, v13 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v37, 16, v15 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v17, 16, v17 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v19, 16, v19 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v21, 16, v21 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v23, 16, v23 |
| ; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB21_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB21_4 |
| ; GCN-NEXT: .LBB21_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB21_3: ; %cmp.false |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v27 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v26 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v38 |
| ; GCN-NEXT: v_or_b32_e32 v1, v1, v39 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v25 |
| ; GCN-NEXT: v_and_b32_e32 v3, 0xffff, v28 |
| ; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v29 |
| ; GCN-NEXT: v_and_b32_e32 v5, 0xffff, v30 |
| ; GCN-NEXT: v_and_b32_e32 v6, 0xffff, v31 |
| ; GCN-NEXT: v_and_b32_e32 v7, 0xffff, v32 |
| ; GCN-NEXT: v_and_b32_e32 v8, 0xffff, v16 |
| ; GCN-NEXT: v_and_b32_e32 v9, 0xffff, v18 |
| ; GCN-NEXT: v_and_b32_e32 v10, 0xffff, v20 |
| ; GCN-NEXT: v_and_b32_e32 v11, 0xffff, v22 |
| ; GCN-NEXT: v_or_b32_e32 v2, v2, v24 |
| ; GCN-NEXT: v_or_b32_e32 v3, v3, v33 |
| ; GCN-NEXT: v_or_b32_e32 v4, v4, v34 |
| ; GCN-NEXT: v_or_b32_e32 v5, v5, v35 |
| ; GCN-NEXT: v_or_b32_e32 v6, v6, v36 |
| ; GCN-NEXT: v_or_b32_e32 v7, v7, v37 |
| ; GCN-NEXT: v_or_b32_e32 v8, v8, v17 |
| ; GCN-NEXT: v_or_b32_e32 v9, v9, v19 |
| ; GCN-NEXT: v_or_b32_e32 v10, v10, v21 |
| ; GCN-NEXT: v_or_b32_e32 v11, v11, v23 |
| ; GCN-NEXT: ; implicit-def: $vgpr27 |
| ; GCN-NEXT: ; implicit-def: $vgpr26 |
| ; GCN-NEXT: ; implicit-def: $vgpr25 |
| ; GCN-NEXT: ; implicit-def: $vgpr28 |
| ; GCN-NEXT: ; implicit-def: $vgpr29 |
| ; GCN-NEXT: ; implicit-def: $vgpr30 |
| ; GCN-NEXT: ; implicit-def: $vgpr31 |
| ; GCN-NEXT: ; implicit-def: $vgpr32 |
| ; GCN-NEXT: ; implicit-def: $vgpr16 |
| ; GCN-NEXT: ; implicit-def: $vgpr18 |
| ; GCN-NEXT: ; implicit-def: $vgpr20 |
| ; GCN-NEXT: ; implicit-def: $vgpr22 |
| ; GCN-NEXT: ; implicit-def: $vgpr38 |
| ; GCN-NEXT: ; implicit-def: $vgpr39 |
| ; GCN-NEXT: ; implicit-def: $vgpr24 |
| ; GCN-NEXT: ; implicit-def: $vgpr33 |
| ; GCN-NEXT: ; implicit-def: $vgpr34 |
| ; GCN-NEXT: ; implicit-def: $vgpr35 |
| ; GCN-NEXT: ; implicit-def: $vgpr36 |
| ; GCN-NEXT: ; implicit-def: $vgpr37 |
| ; GCN-NEXT: ; implicit-def: $vgpr17 |
| ; GCN-NEXT: ; implicit-def: $vgpr19 |
| ; GCN-NEXT: ; implicit-def: $vgpr21 |
| ; GCN-NEXT: ; implicit-def: $vgpr23 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB21_2 |
| ; GCN-NEXT: .LBB21_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v27 |
| ; GCN-NEXT: s_mov_b32 s6, 0x30000 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v26 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v25 |
| ; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v28 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v29 |
| ; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v30 |
| ; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v31 |
| ; GCN-NEXT: v_add_i32_e32 v7, vcc, 3, v32 |
| ; GCN-NEXT: v_add_i32_e32 v8, vcc, 3, v16 |
| ; GCN-NEXT: v_add_i32_e32 v9, vcc, 3, v18 |
| ; GCN-NEXT: v_add_i32_e32 v10, vcc, 3, v20 |
| ; GCN-NEXT: v_add_i32_e32 v11, vcc, 3, v22 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v1 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2 |
| ; GCN-NEXT: v_and_b32_e32 v3, 0xffff, v3 |
| ; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v4 |
| ; GCN-NEXT: v_and_b32_e32 v5, 0xffff, v5 |
| ; GCN-NEXT: v_and_b32_e32 v6, 0xffff, v6 |
| ; GCN-NEXT: v_and_b32_e32 v7, 0xffff, v7 |
| ; GCN-NEXT: v_and_b32_e32 v8, 0xffff, v8 |
| ; GCN-NEXT: v_and_b32_e32 v9, 0xffff, v9 |
| ; GCN-NEXT: v_and_b32_e32 v10, 0xffff, v10 |
| ; GCN-NEXT: v_and_b32_e32 v11, 0xffff, v11 |
| ; GCN-NEXT: v_or_b32_e32 v0, v38, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v39, v1 |
| ; GCN-NEXT: v_or_b32_e32 v2, v24, v2 |
| ; GCN-NEXT: v_or_b32_e32 v3, v33, v3 |
| ; GCN-NEXT: v_or_b32_e32 v4, v34, v4 |
| ; GCN-NEXT: v_or_b32_e32 v5, v35, v5 |
| ; GCN-NEXT: v_or_b32_e32 v6, v36, v6 |
| ; GCN-NEXT: v_or_b32_e32 v7, v37, v7 |
| ; GCN-NEXT: v_or_b32_e32 v8, v17, v8 |
| ; GCN-NEXT: v_or_b32_e32 v9, v19, v9 |
| ; GCN-NEXT: v_or_b32_e32 v10, v21, v10 |
| ; GCN-NEXT: v_or_b32_e32 v11, v23, v11 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, s6, v1 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, s6, v2 |
| ; GCN-NEXT: v_add_i32_e32 v3, vcc, s6, v3 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, s6, v4 |
| ; GCN-NEXT: v_add_i32_e32 v5, vcc, s6, v5 |
| ; GCN-NEXT: v_add_i32_e32 v6, vcc, s6, v6 |
| ; GCN-NEXT: v_add_i32_e32 v7, vcc, s6, v7 |
| ; GCN-NEXT: v_add_i32_e32 v8, vcc, s6, v8 |
| ; GCN-NEXT: v_add_i32_e32 v9, vcc, s6, v9 |
| ; GCN-NEXT: v_add_i32_e32 v10, vcc, s6, v10 |
| ; GCN-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v24i16_to_v6f64: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB21_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v13, 3 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v11 |
| ; VI-NEXT: v_add_u16_sdwa v11, v11, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v11, v12, v11 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v10 |
| ; VI-NEXT: v_add_u16_sdwa v10, v10, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v10, v12, v10 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v9 |
| ; VI-NEXT: v_add_u16_sdwa v9, v9, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v9, v12, v9 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v8 |
| ; VI-NEXT: v_add_u16_sdwa v8, v8, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v8, v12, v8 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v7 |
| ; VI-NEXT: v_add_u16_sdwa v7, v7, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v7, v12, v7 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v6 |
| ; VI-NEXT: v_add_u16_sdwa v6, v6, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v6, v12, v6 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v5 |
| ; VI-NEXT: v_add_u16_sdwa v5, v5, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v5, v12, v5 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v4 |
| ; VI-NEXT: v_add_u16_sdwa v4, v4, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v4, v12, v4 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v3 |
| ; VI-NEXT: v_add_u16_sdwa v3, v3, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v3, v12, v3 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v2 |
| ; VI-NEXT: v_add_u16_sdwa v2, v2, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v2, v12, v2 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v1 |
| ; VI-NEXT: v_add_u16_sdwa v1, v1, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v1, v12, v1 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v0 |
| ; VI-NEXT: v_add_u16_sdwa v0, v0, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v0, v12, v0 |
| ; VI-NEXT: .LBB21_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v24i16_to_v6f64: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB21_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: .LBB21_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v24i16_to_v6f64: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB21_2 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: .LBB21_2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <24 x i16> %a, splat (i16 3) |
| %a2 = bitcast <24 x i16> %a1 to <6 x double> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <24 x i16> %a to <6 x double> |
| br label %end |
| |
| end: |
| %phi = phi <6 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <6 x double> %phi |
| } |
| |
| define <24 x half> @bitcast_v6f64_to_v24f16(<6 x double> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v6f64_to_v24f16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GCN-NEXT: ; implicit-def: $vgpr29 |
| ; GCN-NEXT: ; implicit-def: $vgpr35 |
| ; GCN-NEXT: ; implicit-def: $vgpr24 |
| ; GCN-NEXT: ; implicit-def: $vgpr34 |
| ; GCN-NEXT: ; implicit-def: $vgpr25 |
| ; GCN-NEXT: ; implicit-def: $vgpr33 |
| ; GCN-NEXT: ; implicit-def: $vgpr26 |
| ; GCN-NEXT: ; implicit-def: $vgpr32 |
| ; GCN-NEXT: ; implicit-def: $vgpr27 |
| ; GCN-NEXT: ; implicit-def: $vgpr31 |
| ; GCN-NEXT: ; implicit-def: $vgpr28 |
| ; GCN-NEXT: ; implicit-def: $vgpr30 |
| ; GCN-NEXT: ; implicit-def: $vgpr12 |
| ; GCN-NEXT: ; implicit-def: $vgpr13 |
| ; GCN-NEXT: ; implicit-def: $vgpr14 |
| ; GCN-NEXT: ; implicit-def: $vgpr15 |
| ; GCN-NEXT: ; implicit-def: $vgpr16 |
| ; GCN-NEXT: ; implicit-def: $vgpr17 |
| ; GCN-NEXT: ; implicit-def: $vgpr18 |
| ; GCN-NEXT: ; implicit-def: $vgpr19 |
| ; GCN-NEXT: ; implicit-def: $vgpr20 |
| ; GCN-NEXT: ; implicit-def: $vgpr21 |
| ; GCN-NEXT: ; implicit-def: $vgpr22 |
| ; GCN-NEXT: ; implicit-def: $vgpr23 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB22_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.false |
| ; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v11 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v10 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v17, 16, v9 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v29, 16, v8 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v30, 16, v7 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v31, 16, v6 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v32, 16, v5 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v33, 16, v4 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v34, 16, v3 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v35, 16, v2 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v36, 16, v1 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v37, 16, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v22, v11 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v20, v10 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v18, v9 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v16, v8 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v14, v7 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v12, v6 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v28, v5 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v27, v4 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v26, v3 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v25, v2 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v24, v1 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v23, v13 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v21, v15 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v19, v17 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v17, v29 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v15, v30 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v13, v31 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v30, v32 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v31, v33 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v32, v34 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v33, v35 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v34, v36 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v35, v37 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v29, v0 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: ; implicit-def: $vgpr6 |
| ; GCN-NEXT: ; implicit-def: $vgpr8 |
| ; GCN-NEXT: ; implicit-def: $vgpr10 |
| ; GCN-NEXT: .LBB22_2: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB22_4 |
| ; GCN-NEXT: ; %bb.3: ; %cmp.true |
| ; GCN-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 |
| ; GCN-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 |
| ; GCN-NEXT: v_add_f64 v[4:5], v[4:5], 1.0 |
| ; GCN-NEXT: v_add_f64 v[6:7], v[6:7], 1.0 |
| ; GCN-NEXT: v_add_f64 v[8:9], v[8:9], 1.0 |
| ; GCN-NEXT: v_add_f64 v[10:11], v[10:11], 1.0 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v35, 16, v0 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v34, 16, v1 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v33, 16, v2 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v32, 16, v3 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v31, 16, v4 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v30, 16, v5 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v6 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v7 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v17, 16, v8 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v9 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v21, 16, v10 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v11 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v22, v11 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v20, v10 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v18, v9 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v16, v8 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v14, v7 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v12, v6 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v28, v5 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v27, v4 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v26, v3 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v25, v2 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v24, v1 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v29, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v23, v23 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v21, v21 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v19, v19 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v17, v17 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v15, v15 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v13, v13 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v30, v30 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v31, v31 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v32, v32 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v33, v33 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v34, v34 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v35, v35 |
| ; GCN-NEXT: .LBB22_4: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: v_mov_b32_e32 v0, v29 |
| ; GCN-NEXT: v_mov_b32_e32 v1, v35 |
| ; GCN-NEXT: v_mov_b32_e32 v2, v24 |
| ; GCN-NEXT: v_mov_b32_e32 v3, v34 |
| ; GCN-NEXT: v_mov_b32_e32 v4, v25 |
| ; GCN-NEXT: v_mov_b32_e32 v5, v33 |
| ; GCN-NEXT: v_mov_b32_e32 v6, v26 |
| ; GCN-NEXT: v_mov_b32_e32 v7, v32 |
| ; GCN-NEXT: v_mov_b32_e32 v8, v27 |
| ; GCN-NEXT: v_mov_b32_e32 v9, v31 |
| ; GCN-NEXT: v_mov_b32_e32 v10, v28 |
| ; GCN-NEXT: v_mov_b32_e32 v11, v30 |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v6f64_to_v24f16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB22_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_f64 v[10:11], v[10:11], 1.0 |
| ; VI-NEXT: v_add_f64 v[8:9], v[8:9], 1.0 |
| ; VI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0 |
| ; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0 |
| ; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 |
| ; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 |
| ; VI-NEXT: .LBB22_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v6f64_to_v24f16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB22_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_f64 v[10:11], v[10:11], 1.0 |
| ; GFX9-NEXT: v_add_f64 v[8:9], v[8:9], 1.0 |
| ; GFX9-NEXT: v_add_f64 v[6:7], v[6:7], 1.0 |
| ; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0 |
| ; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 |
| ; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 |
| ; GFX9-NEXT: .LBB22_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v6f64_to_v24f16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB22_2 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_f64 v[10:11], v[10:11], 1.0 |
| ; GFX11-NEXT: v_add_f64 v[8:9], v[8:9], 1.0 |
| ; GFX11-NEXT: v_add_f64 v[6:7], v[6:7], 1.0 |
| ; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0 |
| ; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 |
| ; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 |
| ; GFX11-NEXT: .LBB22_2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <6 x double> %a, splat (double 1.000000e+00) |
| %a2 = bitcast <6 x double> %a1 to <24 x half> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <6 x double> %a to <24 x half> |
| br label %end |
| |
| end: |
| %phi = phi <24 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <24 x half> %phi |
| } |
| |
| define <6 x double> @bitcast_v24f16_to_v6f64(<24 x half> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v24f16_to_v6f64: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v50, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v49, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v48, v3 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v39, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v38, v5 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v34, v4 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v37, v7 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v32, v6 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v36, v9 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v30, v8 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v35, v11 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v28, v10 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v33, v13 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v27, v12 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v31, v15 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v25, v14 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v29, v17 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v24, v16 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v26, v19 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v18, v18 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v21, v21 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v17, v20 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v19, v23 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v16, v22 |
| ; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB23_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB23_4 |
| ; GCN-NEXT: .LBB23_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB23_3: ; %cmp.false |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v50 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v48 |
| ; GCN-NEXT: v_or_b32_e32 v0, v49, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v39, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v38 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v37 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v36 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v35 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v33 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v31 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v29 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v9, 16, v26 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v21 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v19 |
| ; GCN-NEXT: v_or_b32_e32 v2, v34, v2 |
| ; GCN-NEXT: v_or_b32_e32 v3, v32, v3 |
| ; GCN-NEXT: v_or_b32_e32 v4, v30, v4 |
| ; GCN-NEXT: v_or_b32_e32 v5, v28, v5 |
| ; GCN-NEXT: v_or_b32_e32 v6, v27, v6 |
| ; GCN-NEXT: v_or_b32_e32 v7, v25, v7 |
| ; GCN-NEXT: v_or_b32_e32 v8, v24, v8 |
| ; GCN-NEXT: v_or_b32_e32 v9, v18, v9 |
| ; GCN-NEXT: v_or_b32_e32 v10, v17, v10 |
| ; GCN-NEXT: v_or_b32_e32 v11, v16, v11 |
| ; GCN-NEXT: ; implicit-def: $vgpr50 |
| ; GCN-NEXT: ; implicit-def: $vgpr49 |
| ; GCN-NEXT: ; implicit-def: $vgpr48 |
| ; GCN-NEXT: ; implicit-def: $vgpr39 |
| ; GCN-NEXT: ; implicit-def: $vgpr38 |
| ; GCN-NEXT: ; implicit-def: $vgpr34 |
| ; GCN-NEXT: ; implicit-def: $vgpr37 |
| ; GCN-NEXT: ; implicit-def: $vgpr32 |
| ; GCN-NEXT: ; implicit-def: $vgpr36 |
| ; GCN-NEXT: ; implicit-def: $vgpr30 |
| ; GCN-NEXT: ; implicit-def: $vgpr35 |
| ; GCN-NEXT: ; implicit-def: $vgpr28 |
| ; GCN-NEXT: ; implicit-def: $vgpr33 |
| ; GCN-NEXT: ; implicit-def: $vgpr27 |
| ; GCN-NEXT: ; implicit-def: $vgpr31 |
| ; GCN-NEXT: ; implicit-def: $vgpr25 |
| ; GCN-NEXT: ; implicit-def: $vgpr29 |
| ; GCN-NEXT: ; implicit-def: $vgpr24 |
| ; GCN-NEXT: ; implicit-def: $vgpr26 |
| ; GCN-NEXT: ; implicit-def: $vgpr18 |
| ; GCN-NEXT: ; implicit-def: $vgpr21 |
| ; GCN-NEXT: ; implicit-def: $vgpr17 |
| ; GCN-NEXT: ; implicit-def: $vgpr19 |
| ; GCN-NEXT: ; implicit-def: $vgpr16 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB23_2 |
| ; GCN-NEXT: .LBB23_4: ; %cmp.true |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v50 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v49 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v48 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v39 |
| ; GCN-NEXT: v_add_f32_e32 v0, 0x38000000, v0 |
| ; GCN-NEXT: v_add_f32_e32 v1, 0x38000000, v1 |
| ; GCN-NEXT: v_add_f32_e32 v2, 0x38000000, v2 |
| ; GCN-NEXT: v_add_f32_e32 v3, 0x38000000, v3 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 |
| ; GCN-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v3, v2 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v38 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v34 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v4, v37 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v32 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v6, v36 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v7, v30 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v8, v35 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v9, v28 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v10, v33 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v11, v27 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v12, v31 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v13, v25 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v14, v29 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v15, v24 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v20, v26 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v18, v18 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v21, v21 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v17, v17 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v19, v19 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v16, v16 |
| ; GCN-NEXT: v_add_f32_e32 v2, 0x38000000, v2 |
| ; GCN-NEXT: v_add_f32_e32 v3, 0x38000000, v3 |
| ; GCN-NEXT: v_add_f32_e32 v4, 0x38000000, v4 |
| ; GCN-NEXT: v_add_f32_e32 v5, 0x38000000, v5 |
| ; GCN-NEXT: v_add_f32_e32 v6, 0x38000000, v6 |
| ; GCN-NEXT: v_add_f32_e32 v7, 0x38000000, v7 |
| ; GCN-NEXT: v_add_f32_e32 v8, 0x38000000, v8 |
| ; GCN-NEXT: v_add_f32_e32 v9, 0x38000000, v9 |
| ; GCN-NEXT: v_add_f32_e32 v10, 0x38000000, v10 |
| ; GCN-NEXT: v_add_f32_e32 v11, 0x38000000, v11 |
| ; GCN-NEXT: v_add_f32_e32 v12, 0x38000000, v12 |
| ; GCN-NEXT: v_add_f32_e32 v13, 0x38000000, v13 |
| ; GCN-NEXT: v_add_f32_e32 v14, 0x38000000, v14 |
| ; GCN-NEXT: v_add_f32_e32 v15, 0x38000000, v15 |
| ; GCN-NEXT: v_add_f32_e32 v20, 0x38000000, v20 |
| ; GCN-NEXT: v_add_f32_e32 v18, 0x38000000, v18 |
| ; GCN-NEXT: v_add_f32_e32 v21, 0x38000000, v21 |
| ; GCN-NEXT: v_add_f32_e32 v17, 0x38000000, v17 |
| ; GCN-NEXT: v_add_f32_e32 v19, 0x38000000, v19 |
| ; GCN-NEXT: v_add_f32_e32 v16, 0x38000000, v16 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v4, v4 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v5, v5 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v6, v6 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v7, v7 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v8, v8 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v9, v9 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v10, v10 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v11, v11 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v12, v12 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v13, v13 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v14, v14 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v15, v15 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v20, v20 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v18, v18 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v21, v21 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v17, v17 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v19, v19 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v16, v16 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v4 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v6 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v8 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v10 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v12 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v14 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v20, 16, v20 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v21, 16, v21 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v19, 16, v19 |
| ; GCN-NEXT: v_or_b32_e32 v2, v3, v2 |
| ; GCN-NEXT: v_or_b32_e32 v3, v5, v4 |
| ; GCN-NEXT: v_or_b32_e32 v4, v7, v6 |
| ; GCN-NEXT: v_or_b32_e32 v5, v9, v8 |
| ; GCN-NEXT: v_or_b32_e32 v6, v11, v10 |
| ; GCN-NEXT: v_or_b32_e32 v7, v13, v12 |
| ; GCN-NEXT: v_or_b32_e32 v8, v15, v14 |
| ; GCN-NEXT: v_or_b32_e32 v9, v18, v20 |
| ; GCN-NEXT: v_or_b32_e32 v10, v17, v21 |
| ; GCN-NEXT: v_or_b32_e32 v11, v16, v19 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v24f16_to_v6f64: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB23_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v12, 0x200 |
| ; VI-NEXT: v_add_f16_sdwa v13, v11, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v11, 0x200, v11 |
| ; VI-NEXT: v_or_b32_e32 v11, v11, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v10, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v10, 0x200, v10 |
| ; VI-NEXT: v_or_b32_e32 v10, v10, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v9, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v9, 0x200, v9 |
| ; VI-NEXT: v_or_b32_e32 v9, v9, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v8, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v8, 0x200, v8 |
| ; VI-NEXT: v_or_b32_e32 v8, v8, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v7, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v7, 0x200, v7 |
| ; VI-NEXT: v_or_b32_e32 v7, v7, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v6, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v6, 0x200, v6 |
| ; VI-NEXT: v_or_b32_e32 v6, v6, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v5, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v5, 0x200, v5 |
| ; VI-NEXT: v_or_b32_e32 v5, v5, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v4, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v4, 0x200, v4 |
| ; VI-NEXT: v_or_b32_e32 v4, v4, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v3, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v3, 0x200, v3 |
| ; VI-NEXT: v_or_b32_e32 v3, v3, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v2, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v2, 0x200, v2 |
| ; VI-NEXT: v_or_b32_e32 v2, v2, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v1, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v1, 0x200, v1 |
| ; VI-NEXT: v_add_f16_sdwa v12, v0, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v0, 0x200, v0 |
| ; VI-NEXT: v_or_b32_e32 v1, v1, v13 |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v12 |
| ; VI-NEXT: .LBB23_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v24f16_to_v6f64: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB23_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: s_movk_i32 s6, 0x200 |
| ; GFX9-NEXT: v_pk_add_f16 v11, v11, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v10, v10, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v9, v9, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v8, v8, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: .LBB23_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v24f16_to_v6f64: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB23_2 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1] |
| ; GFX11-NEXT: .LBB23_2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <24 x half> %a, splat (half 0xH0200) |
| %a2 = bitcast <24 x half> %a1 to <6 x double> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <24 x half> %a to <6 x double> |
| br label %end |
| |
| end: |
| %phi = phi <6 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <6 x double> %phi |
| } |
| |
| define <24 x i16> @bitcast_v6i64_to_v24i16(<6 x i64> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v6i64_to_v24i16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v22, v11 |
| ; GCN-NEXT: v_mov_b32_e32 v20, v10 |
| ; GCN-NEXT: v_mov_b32_e32 v18, v9 |
| ; GCN-NEXT: v_mov_b32_e32 v16, v8 |
| ; GCN-NEXT: v_mov_b32_e32 v14, v7 |
| ; GCN-NEXT: v_mov_b32_e32 v24, v6 |
| ; GCN-NEXT: v_mov_b32_e32 v10, v5 |
| ; GCN-NEXT: v_mov_b32_e32 v8, v4 |
| ; GCN-NEXT: v_mov_b32_e32 v6, v3 |
| ; GCN-NEXT: v_mov_b32_e32 v4, v2 |
| ; GCN-NEXT: v_mov_b32_e32 v2, v1 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr9 |
| ; GCN-NEXT: ; implicit-def: $vgpr11 |
| ; GCN-NEXT: ; implicit-def: $vgpr13 |
| ; GCN-NEXT: ; implicit-def: $vgpr15 |
| ; GCN-NEXT: ; implicit-def: $vgpr17 |
| ; GCN-NEXT: ; implicit-def: $vgpr19 |
| ; GCN-NEXT: ; implicit-def: $vgpr21 |
| ; GCN-NEXT: ; implicit-def: $vgpr23 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB24_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.false |
| ; GCN-NEXT: v_alignbit_b32 v21, v22, v20, 16 |
| ; GCN-NEXT: v_alignbit_b32 v17, v18, v16, 16 |
| ; GCN-NEXT: v_alignbit_b32 v13, v14, v24, 16 |
| ; GCN-NEXT: v_alignbit_b32 v9, v10, v8, 16 |
| ; GCN-NEXT: v_alignbit_b32 v5, v6, v4, 16 |
| ; GCN-NEXT: v_alignbit_b32 v1, v2, v0, 16 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v22 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v18 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v14 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v10 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v6 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v2 |
| ; GCN-NEXT: .LBB24_2: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB24_4 |
| ; GCN-NEXT: ; %bb.3: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0 |
| ; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v4 |
| ; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc |
| ; GCN-NEXT: v_add_i32_e32 v8, vcc, 3, v8 |
| ; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v10, vcc |
| ; GCN-NEXT: v_add_i32_e32 v24, vcc, 3, v24 |
| ; GCN-NEXT: v_addc_u32_e32 v14, vcc, 0, v14, vcc |
| ; GCN-NEXT: v_add_i32_e32 v16, vcc, 3, v16 |
| ; GCN-NEXT: v_addc_u32_e32 v18, vcc, 0, v18, vcc |
| ; GCN-NEXT: v_add_i32_e32 v20, vcc, 3, v20 |
| ; GCN-NEXT: v_addc_u32_e32 v22, vcc, 0, v22, vcc |
| ; GCN-NEXT: v_alignbit_b32 v21, v22, v20, 16 |
| ; GCN-NEXT: v_alignbit_b32 v17, v18, v16, 16 |
| ; GCN-NEXT: v_alignbit_b32 v13, v14, v24, 16 |
| ; GCN-NEXT: v_alignbit_b32 v9, v10, v8, 16 |
| ; GCN-NEXT: v_alignbit_b32 v5, v6, v4, 16 |
| ; GCN-NEXT: v_alignbit_b32 v1, v2, v0, 16 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v22 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v18 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v14 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v10 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v6 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v2 |
| ; GCN-NEXT: .LBB24_4: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: v_mov_b32_e32 v12, v24 |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v6i64_to_v24i16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB24_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10 |
| ; VI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc |
| ; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8 |
| ; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc |
| ; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6 |
| ; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4 |
| ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2 |
| ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0 |
| ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc |
| ; VI-NEXT: .LBB24_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v6i64_to_v24i16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB24_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, 3, v10 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc |
| ; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 3, v8 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc |
| ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 3, v6 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc |
| ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v4 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc |
| ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v2 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc |
| ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc |
| ; GFX9-NEXT: .LBB24_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v6i64_to_v24i16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB24_2 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_co_u32 v10, vcc_lo, v10, 3 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) |
| ; GFX11-NEXT: v_add_co_ci_u32_e64 v11, null, 0, v11, vcc_lo |
| ; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, v8, 3 |
| ; GFX11-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo |
| ; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v6, 3 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) |
| ; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo |
| ; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 3 |
| ; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo |
| ; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) |
| ; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo |
| ; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3 |
| ; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo |
| ; GFX11-NEXT: .LBB24_2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <6 x i64> %a, splat (i64 3) |
| %a2 = bitcast <6 x i64> %a1 to <24 x i16> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <6 x i64> %a to <24 x i16> |
| br label %end |
| |
| end: |
| %phi = phi <24 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <24 x i16> %phi |
| } |
| |
| define <6 x i64> @bitcast_v24i16_to_v6i64(<24 x i16> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v24i16_to_v6i64: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v32, v14 |
| ; GCN-NEXT: v_mov_b32_e32 v31, v12 |
| ; GCN-NEXT: v_mov_b32_e32 v30, v10 |
| ; GCN-NEXT: v_mov_b32_e32 v29, v8 |
| ; GCN-NEXT: v_mov_b32_e32 v28, v6 |
| ; GCN-NEXT: v_mov_b32_e32 v25, v4 |
| ; GCN-NEXT: v_mov_b32_e32 v26, v2 |
| ; GCN-NEXT: v_mov_b32_e32 v27, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v38, 16, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v39, 16, v3 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v24, 16, v5 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v33, 16, v7 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v34, 16, v9 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v35, 16, v11 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v36, 16, v13 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v37, 16, v15 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v17, 16, v17 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v19, 16, v19 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v21, 16, v21 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v23, 16, v23 |
| ; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB25_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB25_4 |
| ; GCN-NEXT: .LBB25_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB25_3: ; %cmp.false |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v27 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v26 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v38 |
| ; GCN-NEXT: v_or_b32_e32 v1, v1, v39 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v25 |
| ; GCN-NEXT: v_and_b32_e32 v3, 0xffff, v28 |
| ; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v29 |
| ; GCN-NEXT: v_and_b32_e32 v5, 0xffff, v30 |
| ; GCN-NEXT: v_and_b32_e32 v6, 0xffff, v31 |
| ; GCN-NEXT: v_and_b32_e32 v7, 0xffff, v32 |
| ; GCN-NEXT: v_and_b32_e32 v8, 0xffff, v16 |
| ; GCN-NEXT: v_and_b32_e32 v9, 0xffff, v18 |
| ; GCN-NEXT: v_and_b32_e32 v10, 0xffff, v20 |
| ; GCN-NEXT: v_and_b32_e32 v11, 0xffff, v22 |
| ; GCN-NEXT: v_or_b32_e32 v2, v2, v24 |
| ; GCN-NEXT: v_or_b32_e32 v3, v3, v33 |
| ; GCN-NEXT: v_or_b32_e32 v4, v4, v34 |
| ; GCN-NEXT: v_or_b32_e32 v5, v5, v35 |
| ; GCN-NEXT: v_or_b32_e32 v6, v6, v36 |
| ; GCN-NEXT: v_or_b32_e32 v7, v7, v37 |
| ; GCN-NEXT: v_or_b32_e32 v8, v8, v17 |
| ; GCN-NEXT: v_or_b32_e32 v9, v9, v19 |
| ; GCN-NEXT: v_or_b32_e32 v10, v10, v21 |
| ; GCN-NEXT: v_or_b32_e32 v11, v11, v23 |
| ; GCN-NEXT: ; implicit-def: $vgpr27 |
| ; GCN-NEXT: ; implicit-def: $vgpr26 |
| ; GCN-NEXT: ; implicit-def: $vgpr25 |
| ; GCN-NEXT: ; implicit-def: $vgpr28 |
| ; GCN-NEXT: ; implicit-def: $vgpr29 |
| ; GCN-NEXT: ; implicit-def: $vgpr30 |
| ; GCN-NEXT: ; implicit-def: $vgpr31 |
| ; GCN-NEXT: ; implicit-def: $vgpr32 |
| ; GCN-NEXT: ; implicit-def: $vgpr16 |
| ; GCN-NEXT: ; implicit-def: $vgpr18 |
| ; GCN-NEXT: ; implicit-def: $vgpr20 |
| ; GCN-NEXT: ; implicit-def: $vgpr22 |
| ; GCN-NEXT: ; implicit-def: $vgpr38 |
| ; GCN-NEXT: ; implicit-def: $vgpr39 |
| ; GCN-NEXT: ; implicit-def: $vgpr24 |
| ; GCN-NEXT: ; implicit-def: $vgpr33 |
| ; GCN-NEXT: ; implicit-def: $vgpr34 |
| ; GCN-NEXT: ; implicit-def: $vgpr35 |
| ; GCN-NEXT: ; implicit-def: $vgpr36 |
| ; GCN-NEXT: ; implicit-def: $vgpr37 |
| ; GCN-NEXT: ; implicit-def: $vgpr17 |
| ; GCN-NEXT: ; implicit-def: $vgpr19 |
| ; GCN-NEXT: ; implicit-def: $vgpr21 |
| ; GCN-NEXT: ; implicit-def: $vgpr23 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB25_2 |
| ; GCN-NEXT: .LBB25_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v27 |
| ; GCN-NEXT: s_mov_b32 s6, 0x30000 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v26 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v25 |
| ; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v28 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v29 |
| ; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v30 |
| ; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v31 |
| ; GCN-NEXT: v_add_i32_e32 v7, vcc, 3, v32 |
| ; GCN-NEXT: v_add_i32_e32 v8, vcc, 3, v16 |
| ; GCN-NEXT: v_add_i32_e32 v9, vcc, 3, v18 |
| ; GCN-NEXT: v_add_i32_e32 v10, vcc, 3, v20 |
| ; GCN-NEXT: v_add_i32_e32 v11, vcc, 3, v22 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v1 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2 |
| ; GCN-NEXT: v_and_b32_e32 v3, 0xffff, v3 |
| ; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v4 |
| ; GCN-NEXT: v_and_b32_e32 v5, 0xffff, v5 |
| ; GCN-NEXT: v_and_b32_e32 v6, 0xffff, v6 |
| ; GCN-NEXT: v_and_b32_e32 v7, 0xffff, v7 |
| ; GCN-NEXT: v_and_b32_e32 v8, 0xffff, v8 |
| ; GCN-NEXT: v_and_b32_e32 v9, 0xffff, v9 |
| ; GCN-NEXT: v_and_b32_e32 v10, 0xffff, v10 |
| ; GCN-NEXT: v_and_b32_e32 v11, 0xffff, v11 |
| ; GCN-NEXT: v_or_b32_e32 v0, v38, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v39, v1 |
| ; GCN-NEXT: v_or_b32_e32 v2, v24, v2 |
| ; GCN-NEXT: v_or_b32_e32 v3, v33, v3 |
| ; GCN-NEXT: v_or_b32_e32 v4, v34, v4 |
| ; GCN-NEXT: v_or_b32_e32 v5, v35, v5 |
| ; GCN-NEXT: v_or_b32_e32 v6, v36, v6 |
| ; GCN-NEXT: v_or_b32_e32 v7, v37, v7 |
| ; GCN-NEXT: v_or_b32_e32 v8, v17, v8 |
| ; GCN-NEXT: v_or_b32_e32 v9, v19, v9 |
| ; GCN-NEXT: v_or_b32_e32 v10, v21, v10 |
| ; GCN-NEXT: v_or_b32_e32 v11, v23, v11 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, s6, v1 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, s6, v2 |
| ; GCN-NEXT: v_add_i32_e32 v3, vcc, s6, v3 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, s6, v4 |
| ; GCN-NEXT: v_add_i32_e32 v5, vcc, s6, v5 |
| ; GCN-NEXT: v_add_i32_e32 v6, vcc, s6, v6 |
| ; GCN-NEXT: v_add_i32_e32 v7, vcc, s6, v7 |
| ; GCN-NEXT: v_add_i32_e32 v8, vcc, s6, v8 |
| ; GCN-NEXT: v_add_i32_e32 v9, vcc, s6, v9 |
| ; GCN-NEXT: v_add_i32_e32 v10, vcc, s6, v10 |
| ; GCN-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v24i16_to_v6i64: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB25_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v13, 3 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v11 |
| ; VI-NEXT: v_add_u16_sdwa v11, v11, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v11, v12, v11 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v10 |
| ; VI-NEXT: v_add_u16_sdwa v10, v10, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v10, v12, v10 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v9 |
| ; VI-NEXT: v_add_u16_sdwa v9, v9, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v9, v12, v9 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v8 |
| ; VI-NEXT: v_add_u16_sdwa v8, v8, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v8, v12, v8 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v7 |
| ; VI-NEXT: v_add_u16_sdwa v7, v7, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v7, v12, v7 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v6 |
| ; VI-NEXT: v_add_u16_sdwa v6, v6, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v6, v12, v6 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v5 |
| ; VI-NEXT: v_add_u16_sdwa v5, v5, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v5, v12, v5 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v4 |
| ; VI-NEXT: v_add_u16_sdwa v4, v4, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v4, v12, v4 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v3 |
| ; VI-NEXT: v_add_u16_sdwa v3, v3, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v3, v12, v3 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v2 |
| ; VI-NEXT: v_add_u16_sdwa v2, v2, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v2, v12, v2 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v1 |
| ; VI-NEXT: v_add_u16_sdwa v1, v1, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v1, v12, v1 |
| ; VI-NEXT: v_add_u16_e32 v12, 3, v0 |
| ; VI-NEXT: v_add_u16_sdwa v0, v0, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v0, v12, v0 |
| ; VI-NEXT: .LBB25_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v24i16_to_v6i64: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB25_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: .LBB25_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v24i16_to_v6i64: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB25_2 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: .LBB25_2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <24 x i16> %a, splat (i16 3) |
| %a2 = bitcast <24 x i16> %a1 to <6 x i64> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <24 x i16> %a to <6 x i64> |
| br label %end |
| |
| end: |
| %phi = phi <6 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <6 x i64> %phi |
| } |
| |
| define <24 x half> @bitcast_v6i64_to_v24f16(<6 x i64> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v6i64_to_v24f16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v26, v11 |
| ; GCN-NEXT: v_mov_b32_e32 v25, v10 |
| ; GCN-NEXT: v_mov_b32_e32 v28, v9 |
| ; GCN-NEXT: v_mov_b32_e32 v27, v8 |
| ; GCN-NEXT: v_mov_b32_e32 v30, v7 |
| ; GCN-NEXT: v_mov_b32_e32 v29, v6 |
| ; GCN-NEXT: v_mov_b32_e32 v32, v5 |
| ; GCN-NEXT: v_mov_b32_e32 v31, v4 |
| ; GCN-NEXT: v_mov_b32_e32 v34, v3 |
| ; GCN-NEXT: v_mov_b32_e32 v33, v2 |
| ; GCN-NEXT: v_mov_b32_e32 v35, v1 |
| ; GCN-NEXT: v_mov_b32_e32 v24, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: ; implicit-def: $vgpr6 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr8 |
| ; GCN-NEXT: ; implicit-def: $vgpr9 |
| ; GCN-NEXT: ; implicit-def: $vgpr10 |
| ; GCN-NEXT: ; implicit-def: $vgpr11 |
| ; GCN-NEXT: ; implicit-def: $vgpr12 |
| ; GCN-NEXT: ; implicit-def: $vgpr13 |
| ; GCN-NEXT: ; implicit-def: $vgpr14 |
| ; GCN-NEXT: ; implicit-def: $vgpr15 |
| ; GCN-NEXT: ; implicit-def: $vgpr16 |
| ; GCN-NEXT: ; implicit-def: $vgpr17 |
| ; GCN-NEXT: ; implicit-def: $vgpr18 |
| ; GCN-NEXT: ; implicit-def: $vgpr19 |
| ; GCN-NEXT: ; implicit-def: $vgpr20 |
| ; GCN-NEXT: ; implicit-def: $vgpr21 |
| ; GCN-NEXT: ; implicit-def: $vgpr22 |
| ; GCN-NEXT: ; implicit-def: $vgpr23 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB26_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB26_4 |
| ; GCN-NEXT: .LBB26_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB26_3: ; %cmp.false |
| ; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v26 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v25 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v28 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v27 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v30 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v9, 16, v29 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v11, 16, v32 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v36, 16, v31 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v37, 16, v34 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v38, 16, v33 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v39, 16, v35 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v48, 16, v24 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v22, v26 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v20, v25 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v18, v28 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v16, v27 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v14, v30 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v12, v29 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v10, v32 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v8, v31 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v6, v34 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v4, v33 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v35 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v23, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v21, v1 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v19, v3 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v17, v5 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v15, v7 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v13, v9 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v11, v11 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v9, v36 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v7, v37 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v38 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v39 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v48 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v24 |
| ; GCN-NEXT: ; implicit-def: $vgpr24 |
| ; GCN-NEXT: ; implicit-def: $vgpr35 |
| ; GCN-NEXT: ; implicit-def: $vgpr33 |
| ; GCN-NEXT: ; implicit-def: $vgpr34 |
| ; GCN-NEXT: ; implicit-def: $vgpr31 |
| ; GCN-NEXT: ; implicit-def: $vgpr32 |
| ; GCN-NEXT: ; implicit-def: $vgpr29 |
| ; GCN-NEXT: ; implicit-def: $vgpr30 |
| ; GCN-NEXT: ; implicit-def: $vgpr27 |
| ; GCN-NEXT: ; implicit-def: $vgpr28 |
| ; GCN-NEXT: ; implicit-def: $vgpr25 |
| ; GCN-NEXT: ; implicit-def: $vgpr26 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB26_2 |
| ; GCN-NEXT: .LBB26_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v24 |
| ; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v35, vcc |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v33 |
| ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v34, vcc |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v31 |
| ; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v32, vcc |
| ; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v29 |
| ; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v30, vcc |
| ; GCN-NEXT: v_add_i32_e32 v8, vcc, 3, v27 |
| ; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v28, vcc |
| ; GCN-NEXT: v_add_i32_e32 v10, vcc, 3, v25 |
| ; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v26, vcc |
| ; GCN-NEXT: v_lshrrev_b32_e32 v24, 16, v0 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v25, 16, v1 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v26, 16, v2 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v27, 16, v3 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v28, 16, v4 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v29, 16, v5 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v13, 16, v6 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v15, 16, v7 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v17, 16, v8 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v19, 16, v9 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v21, 16, v10 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v23, 16, v11 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v22, v11 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v20, v10 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v18, v9 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v16, v8 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v14, v7 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v12, v6 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v10, v5 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v8, v4 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v6, v3 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v4, v2 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v1 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v23, v23 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v21, v21 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v19, v19 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v17, v17 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v15, v15 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v13, v13 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v11, v29 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v9, v28 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v7, v27 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v26 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v25 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v24 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v6i64_to_v24f16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB26_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10 |
| ; VI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc |
| ; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8 |
| ; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc |
| ; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6 |
| ; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4 |
| ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2 |
| ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0 |
| ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc |
| ; VI-NEXT: .LBB26_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v6i64_to_v24f16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB26_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, 3, v10 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc |
| ; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 3, v8 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc |
| ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 3, v6 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc |
| ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v4 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc |
| ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v2 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc |
| ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc |
| ; GFX9-NEXT: .LBB26_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v6i64_to_v24f16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB26_2 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_co_u32 v10, vcc_lo, v10, 3 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) |
| ; GFX11-NEXT: v_add_co_ci_u32_e64 v11, null, 0, v11, vcc_lo |
| ; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, v8, 3 |
| ; GFX11-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo |
| ; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v6, 3 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) |
| ; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo |
| ; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 3 |
| ; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo |
| ; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) |
| ; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo |
| ; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3 |
| ; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo |
| ; GFX11-NEXT: .LBB26_2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <6 x i64> %a, splat (i64 3) |
| %a2 = bitcast <6 x i64> %a1 to <24 x half> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <6 x i64> %a to <24 x half> |
| br label %end |
| |
| end: |
| %phi = phi <24 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <24 x half> %phi |
| } |
| |
| define <6 x i64> @bitcast_v24f16_to_v6i64(<24 x half> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v24f16_to_v6i64: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v50, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v49, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v48, v3 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v39, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v38, v5 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v34, v4 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v37, v7 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v32, v6 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v36, v9 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v30, v8 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v35, v11 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v28, v10 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v33, v13 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v27, v12 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v31, v15 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v25, v14 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v29, v17 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v24, v16 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v26, v19 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v18, v18 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v21, v21 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v17, v20 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v19, v23 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v16, v22 |
| ; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB27_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB27_4 |
| ; GCN-NEXT: .LBB27_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB27_3: ; %cmp.false |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v50 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v48 |
| ; GCN-NEXT: v_or_b32_e32 v0, v49, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v39, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v38 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v37 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v36 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v35 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v33 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v7, 16, v31 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v29 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v9, 16, v26 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v21 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v11, 16, v19 |
| ; GCN-NEXT: v_or_b32_e32 v2, v34, v2 |
| ; GCN-NEXT: v_or_b32_e32 v3, v32, v3 |
| ; GCN-NEXT: v_or_b32_e32 v4, v30, v4 |
| ; GCN-NEXT: v_or_b32_e32 v5, v28, v5 |
| ; GCN-NEXT: v_or_b32_e32 v6, v27, v6 |
| ; GCN-NEXT: v_or_b32_e32 v7, v25, v7 |
| ; GCN-NEXT: v_or_b32_e32 v8, v24, v8 |
| ; GCN-NEXT: v_or_b32_e32 v9, v18, v9 |
| ; GCN-NEXT: v_or_b32_e32 v10, v17, v10 |
| ; GCN-NEXT: v_or_b32_e32 v11, v16, v11 |
| ; GCN-NEXT: ; implicit-def: $vgpr50 |
| ; GCN-NEXT: ; implicit-def: $vgpr49 |
| ; GCN-NEXT: ; implicit-def: $vgpr48 |
| ; GCN-NEXT: ; implicit-def: $vgpr39 |
| ; GCN-NEXT: ; implicit-def: $vgpr38 |
| ; GCN-NEXT: ; implicit-def: $vgpr34 |
| ; GCN-NEXT: ; implicit-def: $vgpr37 |
| ; GCN-NEXT: ; implicit-def: $vgpr32 |
| ; GCN-NEXT: ; implicit-def: $vgpr36 |
| ; GCN-NEXT: ; implicit-def: $vgpr30 |
| ; GCN-NEXT: ; implicit-def: $vgpr35 |
| ; GCN-NEXT: ; implicit-def: $vgpr28 |
| ; GCN-NEXT: ; implicit-def: $vgpr33 |
| ; GCN-NEXT: ; implicit-def: $vgpr27 |
| ; GCN-NEXT: ; implicit-def: $vgpr31 |
| ; GCN-NEXT: ; implicit-def: $vgpr25 |
| ; GCN-NEXT: ; implicit-def: $vgpr29 |
| ; GCN-NEXT: ; implicit-def: $vgpr24 |
| ; GCN-NEXT: ; implicit-def: $vgpr26 |
| ; GCN-NEXT: ; implicit-def: $vgpr18 |
| ; GCN-NEXT: ; implicit-def: $vgpr21 |
| ; GCN-NEXT: ; implicit-def: $vgpr17 |
| ; GCN-NEXT: ; implicit-def: $vgpr19 |
| ; GCN-NEXT: ; implicit-def: $vgpr16 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB27_2 |
| ; GCN-NEXT: .LBB27_4: ; %cmp.true |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v50 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v49 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v48 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v39 |
| ; GCN-NEXT: v_add_f32_e32 v0, 0x38000000, v0 |
| ; GCN-NEXT: v_add_f32_e32 v1, 0x38000000, v1 |
| ; GCN-NEXT: v_add_f32_e32 v2, 0x38000000, v2 |
| ; GCN-NEXT: v_add_f32_e32 v3, 0x38000000, v3 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 |
| ; GCN-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v3, v2 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v38 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v34 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v4, v37 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v32 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v6, v36 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v7, v30 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v8, v35 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v9, v28 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v10, v33 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v11, v27 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v12, v31 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v13, v25 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v14, v29 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v15, v24 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v20, v26 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v18, v18 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v21, v21 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v17, v17 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v19, v19 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v16, v16 |
| ; GCN-NEXT: v_add_f32_e32 v2, 0x38000000, v2 |
| ; GCN-NEXT: v_add_f32_e32 v3, 0x38000000, v3 |
| ; GCN-NEXT: v_add_f32_e32 v4, 0x38000000, v4 |
| ; GCN-NEXT: v_add_f32_e32 v5, 0x38000000, v5 |
| ; GCN-NEXT: v_add_f32_e32 v6, 0x38000000, v6 |
| ; GCN-NEXT: v_add_f32_e32 v7, 0x38000000, v7 |
| ; GCN-NEXT: v_add_f32_e32 v8, 0x38000000, v8 |
| ; GCN-NEXT: v_add_f32_e32 v9, 0x38000000, v9 |
| ; GCN-NEXT: v_add_f32_e32 v10, 0x38000000, v10 |
| ; GCN-NEXT: v_add_f32_e32 v11, 0x38000000, v11 |
| ; GCN-NEXT: v_add_f32_e32 v12, 0x38000000, v12 |
| ; GCN-NEXT: v_add_f32_e32 v13, 0x38000000, v13 |
| ; GCN-NEXT: v_add_f32_e32 v14, 0x38000000, v14 |
| ; GCN-NEXT: v_add_f32_e32 v15, 0x38000000, v15 |
| ; GCN-NEXT: v_add_f32_e32 v20, 0x38000000, v20 |
| ; GCN-NEXT: v_add_f32_e32 v18, 0x38000000, v18 |
| ; GCN-NEXT: v_add_f32_e32 v21, 0x38000000, v21 |
| ; GCN-NEXT: v_add_f32_e32 v17, 0x38000000, v17 |
| ; GCN-NEXT: v_add_f32_e32 v19, 0x38000000, v19 |
| ; GCN-NEXT: v_add_f32_e32 v16, 0x38000000, v16 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v4, v4 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v5, v5 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v6, v6 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v7, v7 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v8, v8 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v9, v9 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v10, v10 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v11, v11 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v12, v12 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v13, v13 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v14, v14 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v15, v15 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v20, v20 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v18, v18 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v21, v21 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v17, v17 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v19, v19 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v16, v16 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v4 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v6, 16, v6 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v8, 16, v8 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v10, 16, v10 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v12, 16, v12 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v14, 16, v14 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v20, 16, v20 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v21, 16, v21 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v19, 16, v19 |
| ; GCN-NEXT: v_or_b32_e32 v2, v3, v2 |
| ; GCN-NEXT: v_or_b32_e32 v3, v5, v4 |
| ; GCN-NEXT: v_or_b32_e32 v4, v7, v6 |
| ; GCN-NEXT: v_or_b32_e32 v5, v9, v8 |
| ; GCN-NEXT: v_or_b32_e32 v6, v11, v10 |
| ; GCN-NEXT: v_or_b32_e32 v7, v13, v12 |
| ; GCN-NEXT: v_or_b32_e32 v8, v15, v14 |
| ; GCN-NEXT: v_or_b32_e32 v9, v18, v20 |
| ; GCN-NEXT: v_or_b32_e32 v10, v17, v21 |
| ; GCN-NEXT: v_or_b32_e32 v11, v16, v19 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v24f16_to_v6i64: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB27_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v12, 0x200 |
| ; VI-NEXT: v_add_f16_sdwa v13, v11, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v11, 0x200, v11 |
| ; VI-NEXT: v_or_b32_e32 v11, v11, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v10, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v10, 0x200, v10 |
| ; VI-NEXT: v_or_b32_e32 v10, v10, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v9, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v9, 0x200, v9 |
| ; VI-NEXT: v_or_b32_e32 v9, v9, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v8, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v8, 0x200, v8 |
| ; VI-NEXT: v_or_b32_e32 v8, v8, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v7, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v7, 0x200, v7 |
| ; VI-NEXT: v_or_b32_e32 v7, v7, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v6, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v6, 0x200, v6 |
| ; VI-NEXT: v_or_b32_e32 v6, v6, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v5, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v5, 0x200, v5 |
| ; VI-NEXT: v_or_b32_e32 v5, v5, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v4, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v4, 0x200, v4 |
| ; VI-NEXT: v_or_b32_e32 v4, v4, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v3, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v3, 0x200, v3 |
| ; VI-NEXT: v_or_b32_e32 v3, v3, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v2, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v2, 0x200, v2 |
| ; VI-NEXT: v_or_b32_e32 v2, v2, v13 |
| ; VI-NEXT: v_add_f16_sdwa v13, v1, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v1, 0x200, v1 |
| ; VI-NEXT: v_add_f16_sdwa v12, v0, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v0, 0x200, v0 |
| ; VI-NEXT: v_or_b32_e32 v1, v1, v13 |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v12 |
| ; VI-NEXT: .LBB27_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v24f16_to_v6i64: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB27_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: s_movk_i32 s6, 0x200 |
| ; GFX9-NEXT: v_pk_add_f16 v11, v11, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v10, v10, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v9, v9, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v8, v8, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: .LBB27_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v24f16_to_v6i64: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB27_2 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1] |
| ; GFX11-NEXT: .LBB27_2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <24 x half> %a, splat (half 0xH0200) |
| %a2 = bitcast <24 x half> %a1 to <6 x i64> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <24 x half> %a to <6 x i64> |
| br label %end |
| |
| end: |
| %phi = phi <6 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <6 x i64> %phi |
| } |
| |
| define <24 x half> @bitcast_v24i16_to_v24f16(<24 x i16> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v24i16_to_v24f16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill |
| ; GCN-NEXT: v_mov_b32_e32 v55, v23 |
| ; GCN-NEXT: v_mov_b32_e32 v54, v22 |
| ; GCN-NEXT: v_mov_b32_e32 v53, v21 |
| ; GCN-NEXT: v_mov_b32_e32 v52, v20 |
| ; GCN-NEXT: v_mov_b32_e32 v51, v19 |
| ; GCN-NEXT: v_mov_b32_e32 v50, v18 |
| ; GCN-NEXT: v_mov_b32_e32 v49, v17 |
| ; GCN-NEXT: v_mov_b32_e32 v48, v16 |
| ; GCN-NEXT: v_mov_b32_e32 v39, v15 |
| ; GCN-NEXT: v_mov_b32_e32 v38, v14 |
| ; GCN-NEXT: v_mov_b32_e32 v37, v13 |
| ; GCN-NEXT: v_mov_b32_e32 v36, v12 |
| ; GCN-NEXT: v_mov_b32_e32 v35, v11 |
| ; GCN-NEXT: v_mov_b32_e32 v34, v10 |
| ; GCN-NEXT: v_mov_b32_e32 v33, v9 |
| ; GCN-NEXT: v_mov_b32_e32 v32, v8 |
| ; GCN-NEXT: v_mov_b32_e32 v31, v7 |
| ; GCN-NEXT: v_mov_b32_e32 v30, v6 |
| ; GCN-NEXT: v_mov_b32_e32 v29, v5 |
| ; GCN-NEXT: v_mov_b32_e32 v28, v4 |
| ; GCN-NEXT: v_mov_b32_e32 v27, v3 |
| ; GCN-NEXT: v_mov_b32_e32 v26, v2 |
| ; GCN-NEXT: v_mov_b32_e32 v25, v1 |
| ; GCN-NEXT: s_waitcnt expcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v40, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: ; implicit-def: $vgpr6 |
| ; GCN-NEXT: ; implicit-def: $vgpr7 |
| ; GCN-NEXT: ; implicit-def: $vgpr8 |
| ; GCN-NEXT: ; implicit-def: $vgpr9 |
| ; GCN-NEXT: ; implicit-def: $vgpr10 |
| ; GCN-NEXT: ; implicit-def: $vgpr11 |
| ; GCN-NEXT: ; implicit-def: $vgpr12 |
| ; GCN-NEXT: ; implicit-def: $vgpr13 |
| ; GCN-NEXT: ; implicit-def: $vgpr14 |
| ; GCN-NEXT: ; implicit-def: $vgpr15 |
| ; GCN-NEXT: ; implicit-def: $vgpr16 |
| ; GCN-NEXT: ; implicit-def: $vgpr17 |
| ; GCN-NEXT: ; implicit-def: $vgpr18 |
| ; GCN-NEXT: ; implicit-def: $vgpr19 |
| ; GCN-NEXT: ; implicit-def: $vgpr20 |
| ; GCN-NEXT: ; implicit-def: $vgpr21 |
| ; GCN-NEXT: ; implicit-def: $vgpr22 |
| ; GCN-NEXT: ; implicit-def: $vgpr23 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB28_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.false |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v40 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v25 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v26 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v27 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v4, v28 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v29 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v6, v30 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v7, v31 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v8, v32 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v9, v33 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v10, v34 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v11, v35 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v12, v36 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v13, v37 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v14, v38 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v15, v39 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v16, v48 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v17, v49 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v18, v50 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v19, v51 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v20, v52 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v21, v53 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v22, v54 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v23, v55 |
| ; GCN-NEXT: ; implicit-def: $vgpr40 |
| ; GCN-NEXT: ; implicit-def: $vgpr25 |
| ; GCN-NEXT: ; implicit-def: $vgpr26 |
| ; GCN-NEXT: ; implicit-def: $vgpr27 |
| ; GCN-NEXT: ; implicit-def: $vgpr28 |
| ; GCN-NEXT: ; implicit-def: $vgpr29 |
| ; GCN-NEXT: ; implicit-def: $vgpr30 |
| ; GCN-NEXT: ; implicit-def: $vgpr31 |
| ; GCN-NEXT: ; implicit-def: $vgpr32 |
| ; GCN-NEXT: ; implicit-def: $vgpr33 |
| ; GCN-NEXT: ; implicit-def: $vgpr34 |
| ; GCN-NEXT: ; implicit-def: $vgpr35 |
| ; GCN-NEXT: ; implicit-def: $vgpr36 |
| ; GCN-NEXT: ; implicit-def: $vgpr37 |
| ; GCN-NEXT: ; implicit-def: $vgpr38 |
| ; GCN-NEXT: ; implicit-def: $vgpr39 |
| ; GCN-NEXT: ; implicit-def: $vgpr48 |
| ; GCN-NEXT: ; implicit-def: $vgpr49 |
| ; GCN-NEXT: ; implicit-def: $vgpr50 |
| ; GCN-NEXT: ; implicit-def: $vgpr51 |
| ; GCN-NEXT: ; implicit-def: $vgpr52 |
| ; GCN-NEXT: ; implicit-def: $vgpr53 |
| ; GCN-NEXT: ; implicit-def: $vgpr54 |
| ; GCN-NEXT: ; implicit-def: $vgpr55 |
| ; GCN-NEXT: .LBB28_2: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB28_4 |
| ; GCN-NEXT: ; %bb.3: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v23, vcc, 3, v55 |
| ; GCN-NEXT: v_add_i32_e32 v22, vcc, 3, v54 |
| ; GCN-NEXT: v_add_i32_e32 v21, vcc, 3, v53 |
| ; GCN-NEXT: v_add_i32_e32 v20, vcc, 3, v52 |
| ; GCN-NEXT: v_add_i32_e32 v19, vcc, 3, v51 |
| ; GCN-NEXT: v_add_i32_e32 v18, vcc, 3, v50 |
| ; GCN-NEXT: v_add_i32_e32 v17, vcc, 3, v49 |
| ; GCN-NEXT: v_add_i32_e32 v16, vcc, 3, v48 |
| ; GCN-NEXT: v_add_i32_e32 v15, vcc, 3, v39 |
| ; GCN-NEXT: v_add_i32_e32 v14, vcc, 3, v38 |
| ; GCN-NEXT: v_add_i32_e32 v13, vcc, 3, v37 |
| ; GCN-NEXT: v_add_i32_e32 v12, vcc, 3, v36 |
| ; GCN-NEXT: v_add_i32_e32 v11, vcc, 3, v35 |
| ; GCN-NEXT: v_add_i32_e32 v10, vcc, 3, v34 |
| ; GCN-NEXT: v_add_i32_e32 v9, vcc, 3, v33 |
| ; GCN-NEXT: v_add_i32_e32 v8, vcc, 3, v32 |
| ; GCN-NEXT: v_add_i32_e32 v7, vcc, 3, v31 |
| ; GCN-NEXT: v_add_i32_e32 v6, vcc, 3, v30 |
| ; GCN-NEXT: v_add_i32_e32 v5, vcc, 3, v29 |
| ; GCN-NEXT: v_add_i32_e32 v4, vcc, 3, v28 |
| ; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v27 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v26 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v25 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v40 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v2 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v3 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v4, v4 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v5 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v6, v6 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v7, v7 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v8, v8 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v9, v9 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v10, v10 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v11, v11 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v12, v12 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v13, v13 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v14, v14 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v15, v15 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v16, v16 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v17, v17 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v18, v18 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v19, v19 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v20, v20 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v21, v21 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v22, v22 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v23, v23 |
| ; GCN-NEXT: .LBB28_4: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload |
| ; GCN-NEXT: s_waitcnt vmcnt(0) |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v24i16_to_v24f16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB28_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v12, 3 |
| ; VI-NEXT: v_add_u16_sdwa v19, v11, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_u16_e32 v11, 3, v11 |
| ; VI-NEXT: v_or_b32_e32 v11, v11, v19 |
| ; VI-NEXT: v_add_u16_sdwa v19, v10, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_u16_e32 v10, 3, v10 |
| ; VI-NEXT: v_or_b32_e32 v10, v10, v19 |
| ; VI-NEXT: v_add_u16_sdwa v19, v9, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_u16_e32 v9, 3, v9 |
| ; VI-NEXT: v_or_b32_e32 v9, v9, v19 |
| ; VI-NEXT: v_add_u16_sdwa v19, v8, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_u16_e32 v8, 3, v8 |
| ; VI-NEXT: v_add_u16_sdwa v13, v0, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_u16_sdwa v14, v1, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_u16_sdwa v15, v2, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_u16_sdwa v16, v3, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_u16_sdwa v17, v4, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_u16_sdwa v18, v5, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v8, v8, v19 |
| ; VI-NEXT: v_add_u16_sdwa v19, v6, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_u16_sdwa v12, v7, v12 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_u16_e32 v7, 3, v7 |
| ; VI-NEXT: v_add_u16_e32 v6, 3, v6 |
| ; VI-NEXT: v_add_u16_e32 v5, 3, v5 |
| ; VI-NEXT: v_add_u16_e32 v4, 3, v4 |
| ; VI-NEXT: v_add_u16_e32 v3, 3, v3 |
| ; VI-NEXT: v_add_u16_e32 v2, 3, v2 |
| ; VI-NEXT: v_add_u16_e32 v1, 3, v1 |
| ; VI-NEXT: v_add_u16_e32 v0, 3, v0 |
| ; VI-NEXT: v_or_b32_e32 v7, v7, v12 |
| ; VI-NEXT: v_or_b32_e32 v6, v6, v19 |
| ; VI-NEXT: v_or_b32_e32 v5, v5, v18 |
| ; VI-NEXT: v_or_b32_e32 v4, v4, v17 |
| ; VI-NEXT: v_or_b32_e32 v3, v3, v16 |
| ; VI-NEXT: v_or_b32_e32 v2, v2, v15 |
| ; VI-NEXT: v_or_b32_e32 v1, v1, v14 |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v13 |
| ; VI-NEXT: .LBB28_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v24i16_to_v24f16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB28_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: .LBB28_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v24i16_to_v24f16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB28_2 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: .LBB28_2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <24 x i16> %a, splat (i16 3) |
| %a2 = bitcast <24 x i16> %a1 to <24 x half> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <24 x i16> %a to <24 x half> |
| br label %end |
| |
| end: |
| %phi = phi <24 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <24 x half> %phi |
| } |
| |
| define <24 x i16> @bitcast_v24f16_to_v24i16(<24 x half> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v24f16_to_v24i16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v4, v4 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v5, v5 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v6, v6 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v7, v7 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v8, v8 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v9, v9 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v10, v10 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v11, v11 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v12, v12 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v13, v13 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v14, v14 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v15, v15 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v16, v16 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v17, v17 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v18, v18 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v19, v19 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v20, v20 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v21, v21 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v22, v22 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v23, v23 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB29_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.true |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v23, v23 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v22, v22 |
| ; GCN-NEXT: v_add_f32_e32 v23, 0x38000000, v23 |
| ; GCN-NEXT: v_add_f32_e32 v22, 0x38000000, v22 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v23, v23 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v22, v22 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v24, 16, v23 |
| ; GCN-NEXT: v_or_b32_e32 v22, v22, v24 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v19, v19 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v18, v18 |
| ; GCN-NEXT: v_add_f32_e32 v19, 0x38000000, v19 |
| ; GCN-NEXT: v_add_f32_e32 v18, 0x38000000, v18 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v19, v19 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v18, v18 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v24, 16, v19 |
| ; GCN-NEXT: v_or_b32_e32 v18, v18, v24 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v15, v15 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v14, v14 |
| ; GCN-NEXT: v_add_f32_e32 v15, 0x38000000, v15 |
| ; GCN-NEXT: v_add_f32_e32 v14, 0x38000000, v14 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v15, v15 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v14, v14 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v24, 16, v15 |
| ; GCN-NEXT: v_or_b32_e32 v14, v14, v24 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v11, v11 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v10, v10 |
| ; GCN-NEXT: v_add_f32_e32 v11, 0x38000000, v11 |
| ; GCN-NEXT: v_add_f32_e32 v10, 0x38000000, v10 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v11, v11 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v10, v10 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v24, 16, v11 |
| ; GCN-NEXT: v_or_b32_e32 v10, v10, v24 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v7, v7 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v6, v6 |
| ; GCN-NEXT: v_add_f32_e32 v7, 0x38000000, v7 |
| ; GCN-NEXT: v_add_f32_e32 v6, 0x38000000, v6 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v7, v7 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v6, v6 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v24, 16, v7 |
| ; GCN-NEXT: v_or_b32_e32 v6, v6, v24 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v3, v3 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v2, v2 |
| ; GCN-NEXT: v_add_f32_e32 v3, 0x38000000, v3 |
| ; GCN-NEXT: v_add_f32_e32 v2, 0x38000000, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v3, v3 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v2, v2 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v24, 16, v3 |
| ; GCN-NEXT: v_or_b32_e32 v2, v2, v24 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v5, v5 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v4, v4 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v9, v9 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v8, v8 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v13, v13 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v12, v12 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v17, v17 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v16, v16 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v21, v21 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v20, v20 |
| ; GCN-NEXT: v_add_f32_e32 v1, 0x38000000, v1 |
| ; GCN-NEXT: v_add_f32_e32 v0, 0x38000000, v0 |
| ; GCN-NEXT: v_add_f32_e32 v5, 0x38000000, v5 |
| ; GCN-NEXT: v_add_f32_e32 v4, 0x38000000, v4 |
| ; GCN-NEXT: v_add_f32_e32 v9, 0x38000000, v9 |
| ; GCN-NEXT: v_add_f32_e32 v8, 0x38000000, v8 |
| ; GCN-NEXT: v_add_f32_e32 v13, 0x38000000, v13 |
| ; GCN-NEXT: v_add_f32_e32 v12, 0x38000000, v12 |
| ; GCN-NEXT: v_add_f32_e32 v17, 0x38000000, v17 |
| ; GCN-NEXT: v_add_f32_e32 v16, 0x38000000, v16 |
| ; GCN-NEXT: v_add_f32_e32 v21, 0x38000000, v21 |
| ; GCN-NEXT: v_add_f32_e32 v20, 0x38000000, v20 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v5, v5 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v4, v4 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v9, v9 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v8, v8 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v13, v13 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v12, v12 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v17, v17 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v16, v16 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v21, v21 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v20, v20 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v5 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v9, 16, v9 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v13, 16, v13 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v17, 16, v17 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v21, 16, v21 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GCN-NEXT: v_or_b32_e32 v4, v4, v5 |
| ; GCN-NEXT: v_or_b32_e32 v8, v8, v9 |
| ; GCN-NEXT: v_or_b32_e32 v12, v12, v13 |
| ; GCN-NEXT: v_or_b32_e32 v16, v16, v17 |
| ; GCN-NEXT: v_or_b32_e32 v20, v20, v21 |
| ; GCN-NEXT: v_alignbit_b32 v1, v2, v1, 16 |
| ; GCN-NEXT: v_alignbit_b32 v5, v6, v5, 16 |
| ; GCN-NEXT: v_alignbit_b32 v9, v10, v9, 16 |
| ; GCN-NEXT: v_alignbit_b32 v13, v14, v13, 16 |
| ; GCN-NEXT: v_alignbit_b32 v17, v18, v17, 16 |
| ; GCN-NEXT: v_alignbit_b32 v21, v22, v21, 16 |
| ; GCN-NEXT: .LBB29_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v24f16_to_v24i16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB29_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v13, 0x200 |
| ; VI-NEXT: v_add_f16_e32 v19, 0x200, v11 |
| ; VI-NEXT: v_add_f16_sdwa v11, v11, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v11, v19, v11 |
| ; VI-NEXT: v_add_f16_e32 v19, 0x200, v10 |
| ; VI-NEXT: v_add_f16_sdwa v10, v10, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v10, v19, v10 |
| ; VI-NEXT: v_add_f16_e32 v19, 0x200, v9 |
| ; VI-NEXT: v_add_f16_sdwa v9, v9, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v9, v19, v9 |
| ; VI-NEXT: v_add_f16_e32 v19, 0x200, v8 |
| ; VI-NEXT: v_add_f16_sdwa v8, v8, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v12, 0x200, v0 |
| ; VI-NEXT: v_add_f16_sdwa v0, v0, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v14, 0x200, v1 |
| ; VI-NEXT: v_add_f16_sdwa v1, v1, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v15, 0x200, v2 |
| ; VI-NEXT: v_add_f16_sdwa v2, v2, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v16, 0x200, v3 |
| ; VI-NEXT: v_add_f16_sdwa v3, v3, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v17, 0x200, v4 |
| ; VI-NEXT: v_add_f16_sdwa v4, v4, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v18, 0x200, v5 |
| ; VI-NEXT: v_add_f16_sdwa v5, v5, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v8, v19, v8 |
| ; VI-NEXT: v_add_f16_e32 v19, 0x200, v6 |
| ; VI-NEXT: v_add_f16_sdwa v6, v6, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_sdwa v13, v7, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v7, 0x200, v7 |
| ; VI-NEXT: v_or_b32_e32 v7, v7, v13 |
| ; VI-NEXT: v_or_b32_e32 v6, v19, v6 |
| ; VI-NEXT: v_or_b32_e32 v5, v18, v5 |
| ; VI-NEXT: v_or_b32_e32 v4, v17, v4 |
| ; VI-NEXT: v_or_b32_e32 v3, v16, v3 |
| ; VI-NEXT: v_or_b32_e32 v2, v15, v2 |
| ; VI-NEXT: v_or_b32_e32 v1, v14, v1 |
| ; VI-NEXT: v_or_b32_e32 v0, v12, v0 |
| ; VI-NEXT: .LBB29_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v24f16_to_v24i16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB29_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: s_movk_i32 s6, 0x200 |
| ; GFX9-NEXT: v_pk_add_f16 v11, v11, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v10, v10, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v9, v9, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v8, v8, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: .LBB29_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v24f16_to_v24i16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v12 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: s_cbranch_execz .LBB29_2 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1] |
| ; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1] |
| ; GFX11-NEXT: .LBB29_2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <24 x half> %a, splat (half 0xH0200) |
| %a2 = bitcast <24 x half> %a1 to <24 x i16> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <24 x half> %a to <24 x i16> |
| br label %end |
| |
| end: |
| %phi = phi <24 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <24 x i16> %phi |
| } |
