| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 |
| |
| ; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s |
| ; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=VI %s |
| ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s |
| ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s |
| ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s |
| |
| define float @bitcast_i32_to_f32(i32 %a, i32 %b) { |
| ; GCN-LABEL: bitcast_i32_to_f32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB0_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0 |
| ; GCN-NEXT: .LBB0_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_i32_to_f32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_i32_to_f32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_u32_e32 v0, 3, v0 |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_i32_to_f32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v1 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0 |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add i32 %a, 3 |
| %a2 = bitcast i32 %a1 to float |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast i32 %a to float |
| br label %end |
| |
| end: |
| %phi = phi float [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret float %phi |
| } |
| |
| define i32 @bitcast_f32_to_i32(float %a, i32 %b) { |
| ; GCN-LABEL: bitcast_f32_to_i32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB1_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.true |
| ; GCN-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GCN-NEXT: .LBB1_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_f32_to_i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_f32_to_i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_f32_to_i32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v1 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd float %a, 1.000000e+00 |
| %a2 = bitcast float %a1 to i32 |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast float %a to i32 |
| br label %end |
| |
| end: |
| %phi = phi i32 [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret i32 %phi |
| } |
| |
| define <2 x i16> @bitcast_i32_to_v2i16(i32 %a, i32 %b) { |
| ; GCN-LABEL: bitcast_i32_to_v2i16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB2_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB2_4 |
| ; GCN-NEXT: .LBB2_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB2_3: ; %cmp.false |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v0 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB2_2 |
| ; GCN-NEXT: .LBB2_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v0 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_i32_to_v2i16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_i32_to_v2i16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_u32_e32 v0, 3, v0 |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_i32_to_v2i16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v1 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0 |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add i32 %a, 3 |
| %a2 = bitcast i32 %a1 to <2 x i16> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast i32 %a to <2 x i16> |
| br label %end |
| |
| end: |
| %phi = phi <2 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <2 x i16> %phi |
| } |
| |
| define i32 @bitcast_v2i16_to_i32(<2 x i16> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v2i16_to_i32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v3, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB3_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB3_4 |
| ; GCN-NEXT: .LBB3_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB3_3: ; %cmp.false |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v3 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB3_2 |
| ; GCN-NEXT: .LBB3_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v3 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GCN-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v2i16_to_i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v2, 3 |
| ; VI-NEXT: v_add_u16_e32 v1, 3, v0 |
| ; VI-NEXT: v_add_u16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v2i16_to_i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v2i16_to_i32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v1 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <2 x i16> %a, splat (i16 3) |
| %a2 = bitcast <2 x i16> %a1 to i32 |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <2 x i16> %a to i32 |
| br label %end |
| |
| end: |
| %phi = phi i32 [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret i32 %phi |
| } |
| |
| define <2 x half> @bitcast_i32_to_v2f16(i32 %a, i32 %b) { |
| ; GCN-LABEL: bitcast_i32_to_v2f16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v2, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB4_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB4_4 |
| ; GCN-NEXT: .LBB4_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB4_3: ; %cmp.false |
| ; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v2 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v2 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB4_2 |
| ; GCN-NEXT: .LBB4_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v2 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_i32_to_v2f16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_i32_to_v2f16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_u32_e32 v0, 3, v0 |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_i32_to_v2f16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v1 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0 |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add i32 %a, 3 |
| %a2 = bitcast i32 %a1 to <2 x half> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast i32 %a to <2 x half> |
| br label %end |
| |
| end: |
| %phi = phi <2 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <2 x half> %phi |
| } |
| |
| define i32 @bitcast_v2f16_to_i32(<2 x half> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v2f16_to_i32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v2, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v1, v0 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB5_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB5_4 |
| ; GCN-NEXT: .LBB5_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB5_3: ; %cmp.false |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v2 |
| ; GCN-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB5_2 |
| ; GCN-NEXT: .LBB5_4: ; %cmp.true |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v2 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1 |
| ; GCN-NEXT: v_add_f32_e32 v0, 0x38000000, v0 |
| ; GCN-NEXT: v_add_f32_e32 v1, 0x38000000, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 |
| ; GCN-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v2f16_to_i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v1, 0x200 |
| ; VI-NEXT: v_add_f16_sdwa v1, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v0, 0x200, v0 |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v2f16_to_i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: s_movk_i32 s6, 0x200 |
| ; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v2f16_to_i32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v1 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1] |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <2 x half> %a, splat (half 0xH0200) |
| %a2 = bitcast <2 x half> %a1 to i32 |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <2 x half> %a to i32 |
| br label %end |
| |
| end: |
| %phi = phi i32 [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret i32 %phi |
| } |
| |
| define <2 x bfloat> @bitcast_i32_to_v2bf16(i32 %a, i32 %b) { |
| ; GCN-LABEL: bitcast_i32_to_v2bf16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v2, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB6_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB6_4 |
| ; GCN-NEXT: .LBB6_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB6_3: ; %cmp.false |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v2 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v2 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB6_2 |
| ; GCN-NEXT: .LBB6_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v2 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_i32_to_v2bf16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_i32_to_v2bf16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_u32_e32 v0, 3, v0 |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_i32_to_v2bf16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v1 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0 |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add i32 %a, 3 |
| %a2 = bitcast i32 %a1 to <2 x bfloat> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast i32 %a to <2 x bfloat> |
| br label %end |
| |
| end: |
| %phi = phi <2 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <2 x bfloat> %phi |
| } |
| |
| define i32 @bitcast_v2bf16_to_i32(<2 x bfloat> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v2bf16_to_i32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 |
| ; GCN-NEXT: v_mul_f32_e32 v1, 1.0, v1 |
| ; GCN-NEXT: v_mul_f32_e32 v2, 1.0, v0 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB7_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB7_4 |
| ; GCN-NEXT: .LBB7_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB7_3: ; %cmp.false |
| ; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v1 |
| ; GCN-NEXT: v_alignbit_b32 v0, v0, v2, 16 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB7_2 |
| ; GCN-NEXT: .LBB7_4: ; %cmp.true |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v2 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 |
| ; GCN-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; GCN-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v1 |
| ; GCN-NEXT: v_alignbit_b32 v0, v1, v0, 16 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v2bf16_to_i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB7_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v0 |
| ; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 |
| ; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 |
| ; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc |
| ; VI-NEXT: v_bfe_u32 v2, v0, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 |
| ; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc |
| ; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 |
| ; VI-NEXT: v_alignbit_b32 v0, v0, v1, 16 |
| ; VI-NEXT: .LBB7_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v2bf16_to_i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB7_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v0 |
| ; GFX9-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 |
| ; GFX9-NEXT: s_movk_i32 s6, 0x7fff |
| ; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; GFX9-NEXT: v_add3_u32 v2, v2, v1, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 |
| ; GFX9-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc |
| ; GFX9-NEXT: v_bfe_u32 v2, v0, 16, 1 |
| ; GFX9-NEXT: v_add3_u32 v2, v2, v0, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v0 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc |
| ; GFX9-NEXT: s_mov_b32 s6, 0x7060302 |
| ; GFX9-NEXT: v_perm_b32 v0, v0, v1, s6 |
| ; GFX9-NEXT: .LBB7_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-TRUE16-LABEL: bitcast_v2bf16_to_i32: |
| ; GFX11-TRUE16: ; %bb.0: |
| ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v1 |
| ; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB7_2 |
| ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0 |
| ; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0 |
| ; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1 |
| ; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1 |
| ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 |
| ; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0 |
| ; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff |
| ; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo |
| ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 |
| ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo |
| ; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v1, v0 |
| ; GFX11-TRUE16-NEXT: .LBB7_2: ; %end |
| ; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-FAKE16-LABEL: bitcast_v2bf16_to_i32: |
| ; GFX11-FAKE16: ; %bb.0: |
| ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v1 |
| ; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB7_2 |
| ; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0 |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-FAKE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0 |
| ; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v1, 16, 1 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1 |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v1 |
| ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v0 |
| ; GFX11-FAKE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff |
| ; GFX11-FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo |
| ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0x7060302 |
| ; GFX11-FAKE16-NEXT: .LBB7_2: ; %end |
| ; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <2 x bfloat> %a, splat (bfloat 0xR40C0) |
| %a2 = bitcast <2 x bfloat> %a1 to i32 |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <2 x bfloat> %a to i32 |
| br label %end |
| |
| end: |
| %phi = phi i32 [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret i32 %phi |
| } |
| |
| define <1 x i32> @bitcast_i32_to_v1i32(i32 %a, i32 %b) { |
| ; GCN-LABEL: bitcast_i32_to_v1i32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB8_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0 |
| ; GCN-NEXT: .LBB8_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_i32_to_v1i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_i32_to_v1i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_u32_e32 v0, 3, v0 |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_i32_to_v1i32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v1 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0 |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add i32 %a, 3 |
| %a2 = bitcast i32 %a1 to <1 x i32> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast i32 %a to <1 x i32> |
| br label %end |
| |
| end: |
| %phi = phi <1 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <1 x i32> %phi |
| } |
| |
| define i32 @bitcast_v1i32_to_i32(<1 x i32> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v1i32_to_i32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB9_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0 |
| ; GCN-NEXT: .LBB9_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v1i32_to_i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v1i32_to_i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_u32_e32 v0, 3, v0 |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v1i32_to_i32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v1 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0 |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <1 x i32> %a, splat (i32 3) |
| %a2 = bitcast <1 x i32> %a1 to i32 |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <1 x i32> %a to i32 |
| br label %end |
| |
| end: |
| %phi = phi i32 [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret i32 %phi |
| } |
| |
| define <4 x i8> @bitcast_i32_to_v4i8(i32 %a, i32 %b) { |
| ; GCN-LABEL: bitcast_i32_to_v4i8: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB10_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB10_4 |
| ; GCN-NEXT: .LBB10_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB10_3: ; %cmp.false |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB10_2 |
| ; GCN-NEXT: .LBB10_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_i32_to_v4i8: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: ; implicit-def: $vgpr1 |
| ; VI-NEXT: ; implicit-def: $vgpr2 |
| ; VI-NEXT: ; implicit-def: $vgpr3 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_cbranch_execnz .LBB10_3 |
| ; VI-NEXT: ; %bb.1: ; %Flow |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execnz .LBB10_4 |
| ; VI-NEXT: .LBB10_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; VI-NEXT: .LBB10_3: ; %cmp.false |
| ; VI-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB10_2 |
| ; VI-NEXT: .LBB10_4: ; %cmp.true |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0 |
| ; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; VI-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_i32_to_v4i8: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: ; implicit-def: $vgpr1 |
| ; GFX9-NEXT: ; implicit-def: $vgpr2 |
| ; GFX9-NEXT: ; implicit-def: $vgpr3 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_cbranch_execnz .LBB10_3 |
| ; GFX9-NEXT: ; %bb.1: ; %Flow |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execnz .LBB10_4 |
| ; GFX9-NEXT: .LBB10_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; GFX9-NEXT: .LBB10_3: ; %cmp.false |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB10_2 |
| ; GFX9-NEXT: .LBB10_4: ; %cmp.true |
| ; GFX9-NEXT: v_add_u32_e32 v0, 3, v0 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-TRUE16-LABEL: bitcast_i32_to_v4i8: |
| ; GFX11-TRUE16: ; %bb.0: |
| ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v0 |
| ; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16 |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16 |
| ; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v2 |
| ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2 |
| ; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow |
| ; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true |
| ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v2 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v2 |
| ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2 |
| ; GFX11-TRUE16-NEXT: ; %bb.4: ; %end |
| ; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l |
| ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h |
| ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-FAKE16-LABEL: bitcast_i32_to_v4i8: |
| ; GFX11-FAKE16: ; %bb.0: |
| ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr1 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr2 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr3 |
| ; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB10_3 |
| ; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow |
| ; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB10_4 |
| ; GFX11-FAKE16-NEXT: .LBB10_2: ; %end |
| ; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] |
| ; GFX11-FAKE16-NEXT: .LBB10_3: ; %cmp.false |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB10_2 |
| ; GFX11-FAKE16-NEXT: .LBB10_4: ; %cmp.true |
| ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 3, v0 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add i32 %a, 3 |
| %a2 = bitcast i32 %a1 to <4 x i8> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast i32 %a to <4 x i8> |
| br label %end |
| |
| end: |
| %phi = phi <4 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <4 x i8> %phi |
| } |
| |
| define i32 @bitcast_v4i8_to_i32(<4 x i8> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v4i8_to_i32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v5, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v4, 8, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 24, v3 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB11_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB11_4 |
| ; GCN-NEXT: .LBB11_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB11_3: ; %cmp.false |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xff, v5 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xff, v2 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v4 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v1, v2 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB11_2 |
| ; GCN-NEXT: .LBB11_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v5 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v2 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xff, v0 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xff, v2 |
| ; GCN-NEXT: v_or_b32_e32 v0, v4, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v1, v2 |
| ; GCN-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v4i8_to_i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v5, v0 |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 |
| ; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v1 |
| ; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v3 |
| ; VI-NEXT: ; implicit-def: $vgpr0 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_cbranch_execnz .LBB11_3 |
| ; VI-NEXT: ; %bb.1: ; %Flow |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execnz .LBB11_4 |
| ; VI-NEXT: .LBB11_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; VI-NEXT: .LBB11_3: ; %cmp.false |
| ; VI-NEXT: v_or_b32_sdwa v0, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; VI-NEXT: ; implicit-def: $vgpr5 |
| ; VI-NEXT: ; implicit-def: $vgpr4 |
| ; VI-NEXT: ; implicit-def: $vgpr2 |
| ; VI-NEXT: ; implicit-def: $vgpr1 |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB11_2 |
| ; VI-NEXT: .LBB11_4: ; %cmp.true |
| ; VI-NEXT: v_add_u16_e32 v0, 3, v5 |
| ; VI-NEXT: v_add_u16_e32 v2, 3, v2 |
| ; VI-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_mov_b32_e32 v2, 0x300 |
| ; VI-NEXT: v_add_u16_e32 v0, 0x300, v0 |
| ; VI-NEXT: v_add_u16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v4i8_to_i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v5, v0 |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v1 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v3 |
| ; GFX9-NEXT: ; implicit-def: $vgpr0 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_cbranch_execnz .LBB11_3 |
| ; GFX9-NEXT: ; %bb.1: ; %Flow |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execnz .LBB11_4 |
| ; GFX9-NEXT: .LBB11_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; GFX9-NEXT: .LBB11_3: ; %cmp.false |
| ; GFX9-NEXT: v_or_b32_sdwa v0, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; GFX9-NEXT: ; implicit-def: $vgpr5 |
| ; GFX9-NEXT: ; implicit-def: $vgpr4 |
| ; GFX9-NEXT: ; implicit-def: $vgpr2 |
| ; GFX9-NEXT: ; implicit-def: $vgpr1 |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB11_2 |
| ; GFX9-NEXT: .LBB11_4: ; %cmp.true |
| ; GFX9-NEXT: v_add_u16_e32 v0, 3, v5 |
| ; GFX9-NEXT: v_add_u16_e32 v2, 3, v2 |
| ; GFX9-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: s_movk_i32 s6, 0x300 |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0 |
| ; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-TRUE16-LABEL: bitcast_v4i8_to_i32: |
| ; GFX11-TRUE16: ; %bb.0: |
| ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.l |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v3.l |
| ; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0 |
| ; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v4 |
| ; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB11_3 |
| ; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow |
| ; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB11_4 |
| ; GFX11-TRUE16-NEXT: .LBB11_2: ; %end |
| ; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] |
| ; GFX11-TRUE16-NEXT: .LBB11_3: ; %cmp.false |
| ; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v2.h |
| ; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.l |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16 |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.l |
| ; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v0.h, v1.h |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16 |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16 |
| ; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB11_2 |
| ; GFX11-TRUE16-NEXT: .LBB11_4: ; %cmp.true |
| ; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v2.h, 3 |
| ; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v2.l, 3 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l |
| ; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l |
| ; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v0.h |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, 0x300, v0.l |
| ; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, 0x300, v0.h |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-FAKE16-LABEL: bitcast_v4i8_to_i32: |
| ; GFX11-FAKE16: ; %bb.0: |
| ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v5, v0 |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v1 |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3 |
| ; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0 |
| ; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v4 |
| ; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB11_3 |
| ; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow |
| ; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB11_4 |
| ; GFX11-FAKE16-NEXT: .LBB11_2: ; %end |
| ; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] |
| ; GFX11-FAKE16-NEXT: .LBB11_3: ; %cmp.false |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v5 |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr5 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr2 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr3 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr1 |
| ; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB11_2 |
| ; GFX11-FAKE16-NEXT: .LBB11_4: ; %cmp.true |
| ; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v5, 3 |
| ; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v2, 3 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0 |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0 |
| ; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <4 x i8> %a, splat (i8 3) |
| %a2 = bitcast <4 x i8> %a1 to i32 |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <4 x i8> %a to i32 |
| br label %end |
| |
| end: |
| %phi = phi i32 [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret i32 %phi |
| } |
| |
| define <2 x i16> @bitcast_f32_to_v2i16(float %a, i32 %b) { |
| ; GCN-LABEL: bitcast_f32_to_v2i16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB12_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB12_4 |
| ; GCN-NEXT: .LBB12_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB12_3: ; %cmp.false |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v0 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB12_2 |
| ; GCN-NEXT: .LBB12_4: ; %cmp.true |
| ; GCN-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v0 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_f32_to_v2i16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_f32_to_v2i16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_f32_to_v2i16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v1 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd float %a, 1.000000e+00 |
| %a2 = bitcast float %a1 to <2 x i16> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast float %a to <2 x i16> |
| br label %end |
| |
| end: |
| %phi = phi <2 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <2 x i16> %phi |
| } |
| |
| define float @bitcast_v2i16_to_f32(<2 x i16> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v2i16_to_f32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v3, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB13_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB13_4 |
| ; GCN-NEXT: .LBB13_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB13_3: ; %cmp.false |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v3 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB13_2 |
| ; GCN-NEXT: .LBB13_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v3 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GCN-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v2i16_to_f32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v2, 3 |
| ; VI-NEXT: v_add_u16_e32 v1, 3, v0 |
| ; VI-NEXT: v_add_u16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v2i16_to_f32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v2i16_to_f32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v1 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <2 x i16> %a, splat (i16 3) |
| %a2 = bitcast <2 x i16> %a1 to float |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <2 x i16> %a to float |
| br label %end |
| |
| end: |
| %phi = phi float [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret float %phi |
| } |
| |
| define <2 x half> @bitcast_f32_to_v2f16(float %a, i32 %b) { |
| ; GCN-LABEL: bitcast_f32_to_v2f16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v2, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB14_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB14_4 |
| ; GCN-NEXT: .LBB14_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB14_3: ; %cmp.false |
| ; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v2 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v2 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB14_2 |
| ; GCN-NEXT: .LBB14_4: ; %cmp.true |
| ; GCN-NEXT: v_add_f32_e32 v0, 1.0, v2 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_f32_to_v2f16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_f32_to_v2f16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_f32_to_v2f16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v1 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd float %a, 1.000000e+00 |
| %a2 = bitcast float %a1 to <2 x half> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast float %a to <2 x half> |
| br label %end |
| |
| end: |
| %phi = phi <2 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <2 x half> %phi |
| } |
| |
| define float @bitcast_v2f16_to_f32(<2 x half> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v2f16_to_f32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v2, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v1, v0 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB15_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB15_4 |
| ; GCN-NEXT: .LBB15_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB15_3: ; %cmp.false |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v2 |
| ; GCN-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB15_2 |
| ; GCN-NEXT: .LBB15_4: ; %cmp.true |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v2 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1 |
| ; GCN-NEXT: v_add_f32_e32 v0, 0x38000000, v0 |
| ; GCN-NEXT: v_add_f32_e32 v1, 0x38000000, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 |
| ; GCN-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v2f16_to_f32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v1, 0x200 |
| ; VI-NEXT: v_add_f16_sdwa v1, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v0, 0x200, v0 |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v2f16_to_f32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: s_movk_i32 s6, 0x200 |
| ; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v2f16_to_f32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v1 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1] |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <2 x half> %a, splat (half 0xH0200) |
| %a2 = bitcast <2 x half> %a1 to float |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <2 x half> %a to float |
| br label %end |
| |
| end: |
| %phi = phi float [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret float %phi |
| } |
| |
| define <2 x bfloat> @bitcast_f32_to_v2bf16(float %a, i32 %b) { |
| ; GCN-LABEL: bitcast_f32_to_v2bf16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v2, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB16_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB16_4 |
| ; GCN-NEXT: .LBB16_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB16_3: ; %cmp.false |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v2 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v2 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB16_2 |
| ; GCN-NEXT: .LBB16_4: ; %cmp.true |
| ; GCN-NEXT: v_add_f32_e32 v0, 1.0, v2 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_f32_to_v2bf16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_f32_to_v2bf16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_f32_to_v2bf16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v1 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd float %a, 1.000000e+00 |
| %a2 = bitcast float %a1 to <2 x bfloat> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast float %a to <2 x bfloat> |
| br label %end |
| |
| end: |
| %phi = phi <2 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <2 x bfloat> %phi |
| } |
| |
| define float @bitcast_v2bf16_to_f32(<2 x bfloat> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v2bf16_to_f32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 |
| ; GCN-NEXT: v_mul_f32_e32 v1, 1.0, v1 |
| ; GCN-NEXT: v_mul_f32_e32 v2, 1.0, v0 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB17_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB17_4 |
| ; GCN-NEXT: .LBB17_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB17_3: ; %cmp.false |
| ; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v1 |
| ; GCN-NEXT: v_alignbit_b32 v0, v0, v2, 16 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB17_2 |
| ; GCN-NEXT: .LBB17_4: ; %cmp.true |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v2 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 |
| ; GCN-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; GCN-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v1 |
| ; GCN-NEXT: v_alignbit_b32 v0, v1, v0, 16 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v2bf16_to_f32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB17_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v0 |
| ; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 |
| ; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 |
| ; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc |
| ; VI-NEXT: v_bfe_u32 v2, v0, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 |
| ; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc |
| ; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 |
| ; VI-NEXT: v_alignbit_b32 v0, v0, v1, 16 |
| ; VI-NEXT: .LBB17_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v2bf16_to_f32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB17_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v0 |
| ; GFX9-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 |
| ; GFX9-NEXT: s_movk_i32 s6, 0x7fff |
| ; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; GFX9-NEXT: v_add3_u32 v2, v2, v1, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 |
| ; GFX9-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc |
| ; GFX9-NEXT: v_bfe_u32 v2, v0, 16, 1 |
| ; GFX9-NEXT: v_add3_u32 v2, v2, v0, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v0 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc |
| ; GFX9-NEXT: s_mov_b32 s6, 0x7060302 |
| ; GFX9-NEXT: v_perm_b32 v0, v0, v1, s6 |
| ; GFX9-NEXT: .LBB17_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-TRUE16-LABEL: bitcast_v2bf16_to_f32: |
| ; GFX11-TRUE16: ; %bb.0: |
| ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v1 |
| ; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB17_2 |
| ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0 |
| ; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0 |
| ; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1 |
| ; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1 |
| ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 |
| ; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0 |
| ; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff |
| ; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo |
| ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 |
| ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo |
| ; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v1, v0 |
| ; GFX11-TRUE16-NEXT: .LBB17_2: ; %end |
| ; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-FAKE16-LABEL: bitcast_v2bf16_to_f32: |
| ; GFX11-FAKE16: ; %bb.0: |
| ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v1 |
| ; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB17_2 |
| ; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0 |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-FAKE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0 |
| ; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v1, 16, 1 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1 |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v1 |
| ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v0 |
| ; GFX11-FAKE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff |
| ; GFX11-FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo |
| ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0x7060302 |
| ; GFX11-FAKE16-NEXT: .LBB17_2: ; %end |
| ; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <2 x bfloat> %a, splat (bfloat 0xR40C0) |
| %a2 = bitcast <2 x bfloat> %a1 to float |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <2 x bfloat> %a to float |
| br label %end |
| |
| end: |
| %phi = phi float [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret float %phi |
| } |
| |
| define <1 x i32> @bitcast_f32_to_v1i32(float %a, i32 %b) { |
| ; GCN-LABEL: bitcast_f32_to_v1i32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB18_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.true |
| ; GCN-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GCN-NEXT: .LBB18_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_f32_to_v1i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_f32_to_v1i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_f32_to_v1i32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v1 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd float %a, 1.000000e+00 |
| %a2 = bitcast float %a1 to <1 x i32> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast float %a to <1 x i32> |
| br label %end |
| |
| end: |
| %phi = phi <1 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <1 x i32> %phi |
| } |
| |
| define float @bitcast_v1i32_to_f32(<1 x i32> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v1i32_to_f32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB19_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0 |
| ; GCN-NEXT: .LBB19_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v1i32_to_f32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v1i32_to_f32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_u32_e32 v0, 3, v0 |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v1i32_to_f32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v1 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0 |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <1 x i32> %a, splat (i32 3) |
| %a2 = bitcast <1 x i32> %a1 to float |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <1 x i32> %a to float |
| br label %end |
| |
| end: |
| %phi = phi float [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret float %phi |
| } |
| |
| define <4 x i8> @bitcast_f32_to_v4i8(float %a, i32 %b) { |
| ; GCN-LABEL: bitcast_f32_to_v4i8: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB20_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB20_4 |
| ; GCN-NEXT: .LBB20_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB20_3: ; %cmp.false |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB20_2 |
| ; GCN-NEXT: .LBB20_4: ; %cmp.true |
| ; GCN-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_f32_to_v4i8: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: ; implicit-def: $vgpr1 |
| ; VI-NEXT: ; implicit-def: $vgpr2 |
| ; VI-NEXT: ; implicit-def: $vgpr3 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_cbranch_execnz .LBB20_3 |
| ; VI-NEXT: ; %bb.1: ; %Flow |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execnz .LBB20_4 |
| ; VI-NEXT: .LBB20_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; VI-NEXT: .LBB20_3: ; %cmp.false |
| ; VI-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB20_2 |
| ; VI-NEXT: .LBB20_4: ; %cmp.true |
| ; VI-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; VI-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_f32_to_v4i8: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: ; implicit-def: $vgpr1 |
| ; GFX9-NEXT: ; implicit-def: $vgpr2 |
| ; GFX9-NEXT: ; implicit-def: $vgpr3 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_cbranch_execnz .LBB20_3 |
| ; GFX9-NEXT: ; %bb.1: ; %Flow |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execnz .LBB20_4 |
| ; GFX9-NEXT: .LBB20_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; GFX9-NEXT: .LBB20_3: ; %cmp.false |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB20_2 |
| ; GFX9-NEXT: .LBB20_4: ; %cmp.true |
| ; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-TRUE16-LABEL: bitcast_f32_to_v4i8: |
| ; GFX11-TRUE16: ; %bb.0: |
| ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v0 |
| ; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16 |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16 |
| ; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v2 |
| ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2 |
| ; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow |
| ; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true |
| ; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 1.0, v2 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v2 |
| ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2 |
| ; GFX11-TRUE16-NEXT: ; %bb.4: ; %end |
| ; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l |
| ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h |
| ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-FAKE16-LABEL: bitcast_f32_to_v4i8: |
| ; GFX11-FAKE16: ; %bb.0: |
| ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr1 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr2 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr3 |
| ; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB20_3 |
| ; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow |
| ; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB20_4 |
| ; GFX11-FAKE16-NEXT: .LBB20_2: ; %end |
| ; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] |
| ; GFX11-FAKE16-NEXT: .LBB20_3: ; %cmp.false |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB20_2 |
| ; GFX11-FAKE16-NEXT: .LBB20_4: ; %cmp.true |
| ; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 1.0, v0 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd float %a, 1.000000e+00 |
| %a2 = bitcast float %a1 to <4 x i8> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast float %a to <4 x i8> |
| br label %end |
| |
| end: |
| %phi = phi <4 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <4 x i8> %phi |
| } |
| |
| define float @bitcast_v4i8_to_f32(<4 x i8> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v4i8_to_f32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v5, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v4, 8, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 24, v3 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB21_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB21_4 |
| ; GCN-NEXT: .LBB21_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB21_3: ; %cmp.false |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xff, v5 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xff, v2 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v4 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v1, v2 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB21_2 |
| ; GCN-NEXT: .LBB21_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v5 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v2 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xff, v0 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xff, v2 |
| ; GCN-NEXT: v_or_b32_e32 v0, v4, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v1, v2 |
| ; GCN-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v4i8_to_f32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v5, v0 |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 |
| ; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v1 |
| ; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v3 |
| ; VI-NEXT: ; implicit-def: $vgpr0 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_cbranch_execnz .LBB21_3 |
| ; VI-NEXT: ; %bb.1: ; %Flow |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execnz .LBB21_4 |
| ; VI-NEXT: .LBB21_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; VI-NEXT: .LBB21_3: ; %cmp.false |
| ; VI-NEXT: v_or_b32_sdwa v0, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; VI-NEXT: ; implicit-def: $vgpr5 |
| ; VI-NEXT: ; implicit-def: $vgpr4 |
| ; VI-NEXT: ; implicit-def: $vgpr2 |
| ; VI-NEXT: ; implicit-def: $vgpr1 |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB21_2 |
| ; VI-NEXT: .LBB21_4: ; %cmp.true |
| ; VI-NEXT: v_add_u16_e32 v0, 3, v5 |
| ; VI-NEXT: v_add_u16_e32 v2, 3, v2 |
| ; VI-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_mov_b32_e32 v2, 0x300 |
| ; VI-NEXT: v_add_u16_e32 v0, 0x300, v0 |
| ; VI-NEXT: v_add_u16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v4i8_to_f32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v5, v0 |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v1 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v3 |
| ; GFX9-NEXT: ; implicit-def: $vgpr0 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_cbranch_execnz .LBB21_3 |
| ; GFX9-NEXT: ; %bb.1: ; %Flow |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execnz .LBB21_4 |
| ; GFX9-NEXT: .LBB21_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; GFX9-NEXT: .LBB21_3: ; %cmp.false |
| ; GFX9-NEXT: v_or_b32_sdwa v0, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; GFX9-NEXT: ; implicit-def: $vgpr5 |
| ; GFX9-NEXT: ; implicit-def: $vgpr4 |
| ; GFX9-NEXT: ; implicit-def: $vgpr2 |
| ; GFX9-NEXT: ; implicit-def: $vgpr1 |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB21_2 |
| ; GFX9-NEXT: .LBB21_4: ; %cmp.true |
| ; GFX9-NEXT: v_add_u16_e32 v0, 3, v5 |
| ; GFX9-NEXT: v_add_u16_e32 v2, 3, v2 |
| ; GFX9-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: s_movk_i32 s6, 0x300 |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0 |
| ; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-TRUE16-LABEL: bitcast_v4i8_to_f32: |
| ; GFX11-TRUE16: ; %bb.0: |
| ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.l |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v3.l |
| ; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0 |
| ; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v4 |
| ; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB21_3 |
| ; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow |
| ; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB21_4 |
| ; GFX11-TRUE16-NEXT: .LBB21_2: ; %end |
| ; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] |
| ; GFX11-TRUE16-NEXT: .LBB21_3: ; %cmp.false |
| ; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v2.h |
| ; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.l |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16 |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.l |
| ; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v0.h, v1.h |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16 |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16 |
| ; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB21_2 |
| ; GFX11-TRUE16-NEXT: .LBB21_4: ; %cmp.true |
| ; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v2.h, 3 |
| ; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v2.l, 3 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l |
| ; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l |
| ; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v0.h |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, 0x300, v0.l |
| ; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, 0x300, v0.h |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-FAKE16-LABEL: bitcast_v4i8_to_f32: |
| ; GFX11-FAKE16: ; %bb.0: |
| ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v5, v0 |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v1 |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3 |
| ; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0 |
| ; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v4 |
| ; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB21_3 |
| ; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow |
| ; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB21_4 |
| ; GFX11-FAKE16-NEXT: .LBB21_2: ; %end |
| ; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] |
| ; GFX11-FAKE16-NEXT: .LBB21_3: ; %cmp.false |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v5 |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr5 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr2 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr3 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr1 |
| ; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB21_2 |
| ; GFX11-FAKE16-NEXT: .LBB21_4: ; %cmp.true |
| ; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v5, 3 |
| ; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v2, 3 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0 |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0 |
| ; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <4 x i8> %a, splat (i8 3) |
| %a2 = bitcast <4 x i8> %a1 to float |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <4 x i8> %a to float |
| br label %end |
| |
| end: |
| %phi = phi float [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret float %phi |
| } |
| |
| define <2 x half> @bitcast_v2i16_to_v2f16(<2 x i16> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v2i16_to_v2f16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v4, v1 |
| ; GCN-NEXT: v_mov_b32_e32 v3, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB22_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB22_4 |
| ; GCN-NEXT: .LBB22_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB22_3: ; %cmp.false |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v3 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v4 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB22_2 |
| ; GCN-NEXT: .LBB22_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v4 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v3 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v2i16_to_v2f16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v1, 3 |
| ; VI-NEXT: v_add_u16_sdwa v1, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_u16_e32 v0, 3, v0 |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v2i16_to_v2f16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v2i16_to_v2f16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v1 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <2 x i16> %a, splat (i16 3) |
| %a2 = bitcast <2 x i16> %a1 to <2 x half> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <2 x i16> %a to <2 x half> |
| br label %end |
| |
| end: |
| %phi = phi <2 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <2 x half> %phi |
| } |
| |
| define <2 x i16> @bitcast_v2f16_to_v2i16(<2 x half> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v2f16_to_v2i16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB23_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.true |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 |
| ; GCN-NEXT: v_add_f32_e32 v1, 0x38000000, v1 |
| ; GCN-NEXT: v_add_f32_e32 v0, 0x38000000, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v2 |
| ; GCN-NEXT: .LBB23_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v2f16_to_v2i16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v2, 0x200 |
| ; VI-NEXT: v_add_f16_e32 v1, 0x200, v0 |
| ; VI-NEXT: v_add_f16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v2f16_to_v2i16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: s_movk_i32 s6, 0x200 |
| ; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v2f16_to_v2i16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v1 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1] |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <2 x half> %a, splat (half 0xH0200) |
| %a2 = bitcast <2 x half> %a1 to <2 x i16> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <2 x half> %a to <2 x i16> |
| br label %end |
| |
| end: |
| %phi = phi <2 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <2 x i16> %phi |
| } |
| |
| define <2 x bfloat> @bitcast_v2i16_to_v2bf16(<2 x i16> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v2i16_to_v2bf16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB24_2 |
| ; GCN-NEXT: ; %bb.1: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1 |
| ; GCN-NEXT: .LBB24_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v2i16_to_v2bf16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v1, 3 |
| ; VI-NEXT: v_add_u16_sdwa v1, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_u16_e32 v0, 3, v0 |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v2i16_to_v2bf16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v2i16_to_v2bf16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v1 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <2 x i16> %a, splat (i16 3) |
| %a2 = bitcast <2 x i16> %a1 to <2 x bfloat> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <2 x i16> %a to <2 x bfloat> |
| br label %end |
| |
| end: |
| %phi = phi <2 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <2 x bfloat> %phi |
| } |
| |
| define <2 x i16> @bitcast_v2bf16_to_v2i16(<2 x bfloat> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v2bf16_to_v2i16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 |
| ; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v0 |
| ; GCN-NEXT: v_mul_f32_e32 v2, 1.0, v1 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB25_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB25_4 |
| ; GCN-NEXT: .LBB25_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB25_3: ; %cmp.false |
| ; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v3 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v2 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB25_2 |
| ; GCN-NEXT: .LBB25_4: ; %cmp.true |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v3 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v2 |
| ; GCN-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; GCN-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v1 |
| ; GCN-NEXT: v_alignbit_b32 v0, v1, v0, 16 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v2bf16_to_v2i16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB25_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v0 |
| ; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 |
| ; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 |
| ; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc |
| ; VI-NEXT: v_bfe_u32 v2, v0, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 |
| ; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc |
| ; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 |
| ; VI-NEXT: v_alignbit_b32 v0, v0, v1, 16 |
| ; VI-NEXT: .LBB25_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v2bf16_to_v2i16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB25_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v0 |
| ; GFX9-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 |
| ; GFX9-NEXT: s_movk_i32 s6, 0x7fff |
| ; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; GFX9-NEXT: v_add3_u32 v2, v2, v1, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 |
| ; GFX9-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc |
| ; GFX9-NEXT: v_bfe_u32 v2, v0, 16, 1 |
| ; GFX9-NEXT: v_add3_u32 v2, v2, v0, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v0 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc |
| ; GFX9-NEXT: s_mov_b32 s6, 0x7060302 |
| ; GFX9-NEXT: v_perm_b32 v0, v0, v1, s6 |
| ; GFX9-NEXT: .LBB25_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-TRUE16-LABEL: bitcast_v2bf16_to_v2i16: |
| ; GFX11-TRUE16: ; %bb.0: |
| ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v1 |
| ; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB25_2 |
| ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v0 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v0, 16, v0 |
| ; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 |
| ; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1 |
| ; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1 |
| ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 |
| ; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0 |
| ; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff |
| ; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo |
| ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 |
| ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo |
| ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0 |
| ; GFX11-TRUE16-NEXT: .LBB25_2: ; %end |
| ; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-FAKE16-LABEL: bitcast_v2bf16_to_v2i16: |
| ; GFX11-FAKE16: ; %bb.0: |
| ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v1 |
| ; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB25_2 |
| ; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0 |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-FAKE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0 |
| ; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v1, 16, 1 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1 |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v1 |
| ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v0 |
| ; GFX11-FAKE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff |
| ; GFX11-FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo |
| ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0x7060302 |
| ; GFX11-FAKE16-NEXT: .LBB25_2: ; %end |
| ; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <2 x bfloat> %a, splat (bfloat 0xR40C0) |
| %a2 = bitcast <2 x bfloat> %a1 to <2 x i16> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <2 x bfloat> %a to <2 x i16> |
| br label %end |
| |
| end: |
| %phi = phi <2 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <2 x i16> %phi |
| } |
| |
| define <1 x i32> @bitcast_v2i16_to_v1i32(<2 x i16> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v2i16_to_v1i32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v3, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB26_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB26_4 |
| ; GCN-NEXT: .LBB26_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB26_3: ; %cmp.false |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v3 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB26_2 |
| ; GCN-NEXT: .LBB26_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v3 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GCN-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v2i16_to_v1i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v2, 3 |
| ; VI-NEXT: v_add_u16_e32 v1, 3, v0 |
| ; VI-NEXT: v_add_u16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v2i16_to_v1i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v2i16_to_v1i32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v1 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <2 x i16> %a, splat (i16 3) |
| %a2 = bitcast <2 x i16> %a1 to <1 x i32> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <2 x i16> %a to <1 x i32> |
| br label %end |
| |
| end: |
| %phi = phi <1 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <1 x i32> %phi |
| } |
| |
| define <2 x i16> @bitcast_v1i32_to_v2i16(<1 x i32> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v1i32_to_v2i16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB27_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB27_4 |
| ; GCN-NEXT: .LBB27_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB27_3: ; %cmp.false |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v0 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB27_2 |
| ; GCN-NEXT: .LBB27_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v0 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v1i32_to_v2i16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v1i32_to_v2i16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_u32_e32 v0, 3, v0 |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v1i32_to_v2i16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v1 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0 |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <1 x i32> %a, splat (i32 3) |
| %a2 = bitcast <1 x i32> %a1 to <2 x i16> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <1 x i32> %a to <2 x i16> |
| br label %end |
| |
| end: |
| %phi = phi <2 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <2 x i16> %phi |
| } |
| |
| define <4 x i8> @bitcast_v2i16_to_v4i8(<2 x i16> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v2i16_to_v4i8: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v4, v1 |
| ; GCN-NEXT: v_mov_b32_e32 v5, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB28_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB28_4 |
| ; GCN-NEXT: .LBB28_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB28_3: ; %cmp.false |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v5 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v4 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v4 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GCN-NEXT: v_bfe_u32 v3, v4, 8, 8 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB28_2 |
| ; GCN-NEXT: .LBB28_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v5 |
| ; GCN-NEXT: v_add_i32_e32 v3, vcc, 3, v4 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v3 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v3 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GCN-NEXT: v_bfe_u32 v3, v3, 8, 8 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v2i16_to_v4i8: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v4, v0 |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v4 |
| ; VI-NEXT: ; implicit-def: $vgpr0 |
| ; VI-NEXT: ; implicit-def: $vgpr1 |
| ; VI-NEXT: ; implicit-def: $vgpr3 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_cbranch_execnz .LBB28_3 |
| ; VI-NEXT: ; %bb.1: ; %Flow |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execnz .LBB28_4 |
| ; VI-NEXT: .LBB28_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; VI-NEXT: .LBB28_3: ; %cmp.false |
| ; VI-NEXT: v_lshrrev_b32_e32 v3, 24, v4 |
| ; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v4 |
| ; VI-NEXT: v_mov_b32_e32 v0, v4 |
| ; VI-NEXT: ; implicit-def: $vgpr4 |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB28_2 |
| ; VI-NEXT: .LBB28_4: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v1, 3 |
| ; VI-NEXT: v_add_u16_sdwa v2, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_u16_e32 v0, 3, v4 |
| ; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v2 |
| ; VI-NEXT: v_or_b32_e32 v1, v0, v1 |
| ; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v1 |
| ; VI-NEXT: v_bfe_u32 v3, v2, 8, 8 |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v2i16_to_v4i8: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: ; implicit-def: $vgpr1 |
| ; GFX9-NEXT: ; implicit-def: $vgpr2 |
| ; GFX9-NEXT: ; implicit-def: $vgpr3 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_cbranch_execnz .LBB28_3 |
| ; GFX9-NEXT: ; %bb.1: ; %Flow |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execnz .LBB28_4 |
| ; GFX9-NEXT: .LBB28_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; GFX9-NEXT: .LBB28_3: ; %cmp.false |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB28_2 |
| ; GFX9-NEXT: .LBB28_4: ; %cmp.true |
| ; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-TRUE16-LABEL: bitcast_v2i16_to_v4i8: |
| ; GFX11-TRUE16: ; %bb.0: |
| ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v0 |
| ; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16 |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16 |
| ; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v2 |
| ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2 |
| ; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow |
| ; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true |
| ; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0] |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v2 |
| ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2 |
| ; GFX11-TRUE16-NEXT: ; %bb.4: ; %end |
| ; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l |
| ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h |
| ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-FAKE16-LABEL: bitcast_v2i16_to_v4i8: |
| ; GFX11-FAKE16: ; %bb.0: |
| ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr1 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr2 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr3 |
| ; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB28_3 |
| ; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow |
| ; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB28_4 |
| ; GFX11-FAKE16-NEXT: .LBB28_2: ; %end |
| ; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] |
| ; GFX11-FAKE16-NEXT: .LBB28_3: ; %cmp.false |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB28_2 |
| ; GFX11-FAKE16-NEXT: .LBB28_4: ; %cmp.true |
| ; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0] |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <2 x i16> %a, splat (i16 3) |
| %a2 = bitcast <2 x i16> %a1 to <4 x i8> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <2 x i16> %a to <4 x i8> |
| br label %end |
| |
| end: |
| %phi = phi <4 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <4 x i8> %phi |
| } |
| |
| define <2 x i16> @bitcast_v4i8_to_v2i16(<4 x i8> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v4i8_to_v2i16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v5, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v4, 8, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v3, 8, v3 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB29_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB29_4 |
| ; GCN-NEXT: .LBB29_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB29_3: ; %cmp.false |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xff, v5 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xff, v2 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v4 |
| ; GCN-NEXT: v_or_b32_e32 v1, v1, v3 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v1 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v2 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v1 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB29_2 |
| ; GCN-NEXT: .LBB29_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v5 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v2 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xff, v0 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xff, v1 |
| ; GCN-NEXT: v_or_b32_e32 v0, v4, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v3, v1 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 0x300, v1 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v1 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v2 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v1 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v4i8_to_v2i16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v5, v0 |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 |
| ; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v1 |
| ; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v3 |
| ; VI-NEXT: ; implicit-def: $vgpr0 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_cbranch_execnz .LBB29_3 |
| ; VI-NEXT: ; %bb.1: ; %Flow |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execnz .LBB29_4 |
| ; VI-NEXT: .LBB29_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; VI-NEXT: .LBB29_3: ; %cmp.false |
| ; VI-NEXT: v_or_b32_sdwa v0, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; VI-NEXT: ; implicit-def: $vgpr5 |
| ; VI-NEXT: ; implicit-def: $vgpr4 |
| ; VI-NEXT: ; implicit-def: $vgpr2 |
| ; VI-NEXT: ; implicit-def: $vgpr1 |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB29_2 |
| ; VI-NEXT: .LBB29_4: ; %cmp.true |
| ; VI-NEXT: v_add_u16_e32 v0, 3, v5 |
| ; VI-NEXT: v_add_u16_e32 v2, 3, v2 |
| ; VI-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_mov_b32_e32 v2, 0x300 |
| ; VI-NEXT: v_add_u16_e32 v0, 0x300, v0 |
| ; VI-NEXT: v_add_u16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v4i8_to_v2i16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v5, v0 |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v1 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v3 |
| ; GFX9-NEXT: ; implicit-def: $vgpr0 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_cbranch_execnz .LBB29_3 |
| ; GFX9-NEXT: ; %bb.1: ; %Flow |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execnz .LBB29_4 |
| ; GFX9-NEXT: .LBB29_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; GFX9-NEXT: .LBB29_3: ; %cmp.false |
| ; GFX9-NEXT: v_or_b32_sdwa v0, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; GFX9-NEXT: ; implicit-def: $vgpr5 |
| ; GFX9-NEXT: ; implicit-def: $vgpr4 |
| ; GFX9-NEXT: ; implicit-def: $vgpr2 |
| ; GFX9-NEXT: ; implicit-def: $vgpr1 |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB29_2 |
| ; GFX9-NEXT: .LBB29_4: ; %cmp.true |
| ; GFX9-NEXT: v_add_u16_e32 v0, 3, v5 |
| ; GFX9-NEXT: v_add_u16_e32 v2, 3, v2 |
| ; GFX9-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: s_movk_i32 s6, 0x300 |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0 |
| ; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-TRUE16-LABEL: bitcast_v4i8_to_v2i16: |
| ; GFX11-TRUE16: ; %bb.0: |
| ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.l |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v3.l |
| ; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0 |
| ; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v4 |
| ; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB29_3 |
| ; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow |
| ; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB29_4 |
| ; GFX11-TRUE16-NEXT: .LBB29_2: ; %end |
| ; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] |
| ; GFX11-TRUE16-NEXT: .LBB29_3: ; %cmp.false |
| ; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v2.h |
| ; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.l |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16 |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.l |
| ; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v0.h, v1.h |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16 |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16 |
| ; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB29_2 |
| ; GFX11-TRUE16-NEXT: .LBB29_4: ; %cmp.true |
| ; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v2.h, 3 |
| ; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v2.l, 3 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l |
| ; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l |
| ; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v0.h |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, 0x300, v0.l |
| ; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, 0x300, v0.h |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-FAKE16-LABEL: bitcast_v4i8_to_v2i16: |
| ; GFX11-FAKE16: ; %bb.0: |
| ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v5, v0 |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v1 |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3 |
| ; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0 |
| ; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v4 |
| ; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB29_3 |
| ; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow |
| ; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB29_4 |
| ; GFX11-FAKE16-NEXT: .LBB29_2: ; %end |
| ; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] |
| ; GFX11-FAKE16-NEXT: .LBB29_3: ; %cmp.false |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v5 |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr5 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr2 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr3 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr1 |
| ; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB29_2 |
| ; GFX11-FAKE16-NEXT: .LBB29_4: ; %cmp.true |
| ; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v5, 3 |
| ; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v2, 3 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0 |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0 |
| ; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <4 x i8> %a, splat (i8 3) |
| %a2 = bitcast <4 x i8> %a1 to <2 x i16> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <4 x i8> %a to <2 x i16> |
| br label %end |
| |
| end: |
| %phi = phi <2 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <2 x i16> %phi |
| } |
| |
| define <2 x bfloat> @bitcast_v2f16_to_v2bf16(<2 x half> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v2f16_to_v2bf16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v2, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v3, v1 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB30_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB30_4 |
| ; GCN-NEXT: .LBB30_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB30_3: ; %cmp.false |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v2 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v3 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB30_2 |
| ; GCN-NEXT: .LBB30_4: ; %cmp.true |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v3 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v2 |
| ; GCN-NEXT: v_add_f32_e32 v0, 0x38000000, v0 |
| ; GCN-NEXT: v_add_f32_e32 v1, 0x38000000, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v2, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v2 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v2f16_to_v2bf16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v2, 0x200 |
| ; VI-NEXT: v_add_f16_e32 v1, 0x200, v0 |
| ; VI-NEXT: v_add_f16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v2f16_to_v2bf16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: s_movk_i32 s6, 0x200 |
| ; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v2f16_to_v2bf16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v1 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1] |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <2 x half> %a, splat (half 0xH0200) |
| %a2 = bitcast <2 x half> %a1 to <2 x bfloat> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <2 x half> %a to <2 x bfloat> |
| br label %end |
| |
| end: |
| %phi = phi <2 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <2 x bfloat> %phi |
| } |
| |
| define <2 x half> @bitcast_v2bf16_to_v2f16(<2 x bfloat> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v2bf16_to_v2f16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 |
| ; GCN-NEXT: v_mul_f32_e32 v2, 1.0, v0 |
| ; GCN-NEXT: v_mul_f32_e32 v3, 1.0, v1 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB31_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB31_4 |
| ; GCN-NEXT: .LBB31_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB31_3: ; %cmp.false |
| ; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v2 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v3 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB31_2 |
| ; GCN-NEXT: .LBB31_4: ; %cmp.true |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v3 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v2 |
| ; GCN-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; GCN-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v1 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v2 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v2bf16_to_v2f16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB31_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v0 |
| ; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 |
| ; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 |
| ; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc |
| ; VI-NEXT: v_bfe_u32 v2, v0, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 |
| ; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc |
| ; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 |
| ; VI-NEXT: v_alignbit_b32 v0, v0, v1, 16 |
| ; VI-NEXT: .LBB31_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v2bf16_to_v2f16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB31_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v0 |
| ; GFX9-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 |
| ; GFX9-NEXT: s_movk_i32 s6, 0x7fff |
| ; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; GFX9-NEXT: v_add3_u32 v2, v2, v1, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 |
| ; GFX9-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc |
| ; GFX9-NEXT: v_bfe_u32 v2, v0, 16, 1 |
| ; GFX9-NEXT: v_add3_u32 v2, v2, v0, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v0 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc |
| ; GFX9-NEXT: s_mov_b32 s6, 0x7060302 |
| ; GFX9-NEXT: v_perm_b32 v0, v0, v1, s6 |
| ; GFX9-NEXT: .LBB31_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-TRUE16-LABEL: bitcast_v2bf16_to_v2f16: |
| ; GFX11-TRUE16: ; %bb.0: |
| ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v1 |
| ; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB31_2 |
| ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0 |
| ; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0 |
| ; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1 |
| ; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1 |
| ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 |
| ; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0 |
| ; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff |
| ; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo |
| ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 |
| ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo |
| ; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v1, v0 |
| ; GFX11-TRUE16-NEXT: .LBB31_2: ; %end |
| ; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-FAKE16-LABEL: bitcast_v2bf16_to_v2f16: |
| ; GFX11-FAKE16: ; %bb.0: |
| ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v1 |
| ; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB31_2 |
| ; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0 |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-FAKE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0 |
| ; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v1, 16, 1 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1 |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v1 |
| ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v0 |
| ; GFX11-FAKE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff |
| ; GFX11-FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo |
| ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0x7060302 |
| ; GFX11-FAKE16-NEXT: .LBB31_2: ; %end |
| ; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <2 x bfloat> %a, splat (bfloat 0xR40C0) |
| %a2 = bitcast <2 x bfloat> %a1 to <2 x half> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <2 x bfloat> %a to <2 x half> |
| br label %end |
| |
| end: |
| %phi = phi <2 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <2 x half> %phi |
| } |
| |
| define <1 x i32> @bitcast_v2f16_to_v1i32(<2 x half> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v2f16_to_v1i32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v2, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v1, v0 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB32_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB32_4 |
| ; GCN-NEXT: .LBB32_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB32_3: ; %cmp.false |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v2 |
| ; GCN-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB32_2 |
| ; GCN-NEXT: .LBB32_4: ; %cmp.true |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v2 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1 |
| ; GCN-NEXT: v_add_f32_e32 v0, 0x38000000, v0 |
| ; GCN-NEXT: v_add_f32_e32 v1, 0x38000000, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1 |
| ; GCN-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v2f16_to_v1i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v1, 0x200 |
| ; VI-NEXT: v_add_f16_sdwa v1, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_add_f16_e32 v0, 0x200, v0 |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v2f16_to_v1i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: s_movk_i32 s6, 0x200 |
| ; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v2f16_to_v1i32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v1 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1] |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <2 x half> %a, splat (half 0xH0200) |
| %a2 = bitcast <2 x half> %a1 to <1 x i32> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <2 x half> %a to <1 x i32> |
| br label %end |
| |
| end: |
| %phi = phi <1 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <1 x i32> %phi |
| } |
| |
| define <2 x half> @bitcast_v1i32_to_v2f16(<1 x i32> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v1i32_to_v2f16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v2, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB33_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB33_4 |
| ; GCN-NEXT: .LBB33_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB33_3: ; %cmp.false |
| ; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v2 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v2 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB33_2 |
| ; GCN-NEXT: .LBB33_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v2 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v1i32_to_v2f16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v1i32_to_v2f16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_u32_e32 v0, 3, v0 |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v1i32_to_v2f16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v1 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0 |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <1 x i32> %a, splat (i32 3) |
| %a2 = bitcast <1 x i32> %a1 to <2 x half> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <1 x i32> %a to <2 x half> |
| br label %end |
| |
| end: |
| %phi = phi <2 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <2 x half> %phi |
| } |
| |
| define <4 x i8> @bitcast_v2f16_to_v4i8(<2 x half> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v2f16_to_v4i8: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v2, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v4, v0 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB34_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB34_4 |
| ; GCN-NEXT: .LBB34_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB34_3: ; %cmp.false |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v2 |
| ; GCN-NEXT: v_or_b32_e32 v0, v4, v0 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GCN-NEXT: v_bfe_u32 v3, v2, 8, 8 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB34_2 |
| ; GCN-NEXT: .LBB34_4: ; %cmp.true |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v2 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v4 |
| ; GCN-NEXT: v_add_f32_e32 v0, 0x38000000, v0 |
| ; GCN-NEXT: v_add_f32_e32 v1, 0x38000000, v1 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v2, v0 |
| ; GCN-NEXT: v_cvt_f16_f32_e32 v0, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v2 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GCN-NEXT: v_bfe_u32 v3, v2, 8, 8 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v2f16_to_v4i8: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; VI-NEXT: ; implicit-def: $vgpr1 |
| ; VI-NEXT: ; implicit-def: $vgpr3 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_cbranch_execnz .LBB34_3 |
| ; VI-NEXT: ; %bb.1: ; %Flow |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execnz .LBB34_4 |
| ; VI-NEXT: .LBB34_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; VI-NEXT: .LBB34_3: ; %cmp.false |
| ; VI-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB34_2 |
| ; VI-NEXT: .LBB34_4: ; %cmp.true |
| ; VI-NEXT: v_mov_b32_e32 v1, 0x200 |
| ; VI-NEXT: v_add_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD |
| ; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v2 |
| ; VI-NEXT: v_add_f16_e32 v0, 0x200, v0 |
| ; VI-NEXT: v_or_b32_e32 v1, v0, v1 |
| ; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v1 |
| ; VI-NEXT: v_bfe_u32 v3, v2, 8, 8 |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v2f16_to_v4i8: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: ; implicit-def: $vgpr1 |
| ; GFX9-NEXT: ; implicit-def: $vgpr2 |
| ; GFX9-NEXT: ; implicit-def: $vgpr3 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_cbranch_execnz .LBB34_3 |
| ; GFX9-NEXT: ; %bb.1: ; %Flow |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execnz .LBB34_4 |
| ; GFX9-NEXT: .LBB34_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; GFX9-NEXT: .LBB34_3: ; %cmp.false |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB34_2 |
| ; GFX9-NEXT: .LBB34_4: ; %cmp.true |
| ; GFX9-NEXT: s_movk_i32 s6, 0x200 |
| ; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0] |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-TRUE16-LABEL: bitcast_v2f16_to_v4i8: |
| ; GFX11-TRUE16: ; %bb.0: |
| ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v0 |
| ; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16 |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16 |
| ; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v2 |
| ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2 |
| ; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow |
| ; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true |
| ; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1] |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v2 |
| ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2 |
| ; GFX11-TRUE16-NEXT: ; %bb.4: ; %end |
| ; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l |
| ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h |
| ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-FAKE16-LABEL: bitcast_v2f16_to_v4i8: |
| ; GFX11-FAKE16: ; %bb.0: |
| ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr1 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr2 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr3 |
| ; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB34_3 |
| ; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow |
| ; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB34_4 |
| ; GFX11-FAKE16-NEXT: .LBB34_2: ; %end |
| ; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] |
| ; GFX11-FAKE16-NEXT: .LBB34_3: ; %cmp.false |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB34_2 |
| ; GFX11-FAKE16-NEXT: .LBB34_4: ; %cmp.true |
| ; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1] |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <2 x half> %a, splat (half 0xH0200) |
| %a2 = bitcast <2 x half> %a1 to <4 x i8> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <2 x half> %a to <4 x i8> |
| br label %end |
| |
| end: |
| %phi = phi <4 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <4 x i8> %phi |
| } |
| |
| define <2 x half> @bitcast_v4i8_to_v2f16(<4 x i8> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v4i8_to_v2f16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v5, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v4, 8, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v3, 8, v3 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB35_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB35_4 |
| ; GCN-NEXT: .LBB35_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB35_3: ; %cmp.false |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xff, v5 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xff, v2 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v4 |
| ; GCN-NEXT: v_or_b32_e32 v1, v1, v3 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v1 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB35_2 |
| ; GCN-NEXT: .LBB35_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v2 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v5 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xff, v0 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xff, v1 |
| ; GCN-NEXT: v_or_b32_e32 v0, v3, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v4, v1 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 0x300, v0 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x300, v1 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 |
| ; GCN-NEXT: v_cvt_f32_f16_e32 v1, v2 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v4i8_to_v2f16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v5, v0 |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 |
| ; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v1 |
| ; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v3 |
| ; VI-NEXT: ; implicit-def: $vgpr0 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_cbranch_execnz .LBB35_3 |
| ; VI-NEXT: ; %bb.1: ; %Flow |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execnz .LBB35_4 |
| ; VI-NEXT: .LBB35_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; VI-NEXT: .LBB35_3: ; %cmp.false |
| ; VI-NEXT: v_or_b32_sdwa v0, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; VI-NEXT: ; implicit-def: $vgpr5 |
| ; VI-NEXT: ; implicit-def: $vgpr4 |
| ; VI-NEXT: ; implicit-def: $vgpr2 |
| ; VI-NEXT: ; implicit-def: $vgpr1 |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB35_2 |
| ; VI-NEXT: .LBB35_4: ; %cmp.true |
| ; VI-NEXT: v_add_u16_e32 v0, 3, v5 |
| ; VI-NEXT: v_add_u16_e32 v2, 3, v2 |
| ; VI-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_mov_b32_e32 v2, 0x300 |
| ; VI-NEXT: v_add_u16_e32 v0, 0x300, v0 |
| ; VI-NEXT: v_add_u16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v4i8_to_v2f16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v5, v0 |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v1 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v3 |
| ; GFX9-NEXT: ; implicit-def: $vgpr0 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_cbranch_execnz .LBB35_3 |
| ; GFX9-NEXT: ; %bb.1: ; %Flow |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execnz .LBB35_4 |
| ; GFX9-NEXT: .LBB35_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; GFX9-NEXT: .LBB35_3: ; %cmp.false |
| ; GFX9-NEXT: v_or_b32_sdwa v0, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; GFX9-NEXT: ; implicit-def: $vgpr5 |
| ; GFX9-NEXT: ; implicit-def: $vgpr4 |
| ; GFX9-NEXT: ; implicit-def: $vgpr2 |
| ; GFX9-NEXT: ; implicit-def: $vgpr1 |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB35_2 |
| ; GFX9-NEXT: .LBB35_4: ; %cmp.true |
| ; GFX9-NEXT: v_add_u16_e32 v0, 3, v5 |
| ; GFX9-NEXT: v_add_u16_e32 v2, 3, v2 |
| ; GFX9-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: s_movk_i32 s6, 0x300 |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0 |
| ; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-TRUE16-LABEL: bitcast_v4i8_to_v2f16: |
| ; GFX11-TRUE16: ; %bb.0: |
| ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.l |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v3.l |
| ; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0 |
| ; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v4 |
| ; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB35_3 |
| ; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow |
| ; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB35_4 |
| ; GFX11-TRUE16-NEXT: .LBB35_2: ; %end |
| ; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] |
| ; GFX11-TRUE16-NEXT: .LBB35_3: ; %cmp.false |
| ; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v2.h |
| ; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.l |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16 |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.l |
| ; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v0.h, v1.h |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16 |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16 |
| ; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB35_2 |
| ; GFX11-TRUE16-NEXT: .LBB35_4: ; %cmp.true |
| ; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v2.h, 3 |
| ; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v2.l, 3 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l |
| ; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l |
| ; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v0.h |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, 0x300, v0.l |
| ; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, 0x300, v0.h |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-FAKE16-LABEL: bitcast_v4i8_to_v2f16: |
| ; GFX11-FAKE16: ; %bb.0: |
| ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v5, v0 |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v1 |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3 |
| ; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0 |
| ; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v4 |
| ; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB35_3 |
| ; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow |
| ; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB35_4 |
| ; GFX11-FAKE16-NEXT: .LBB35_2: ; %end |
| ; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] |
| ; GFX11-FAKE16-NEXT: .LBB35_3: ; %cmp.false |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v5 |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr5 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr2 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr3 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr1 |
| ; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB35_2 |
| ; GFX11-FAKE16-NEXT: .LBB35_4: ; %cmp.true |
| ; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v5, 3 |
| ; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v2, 3 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0 |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0 |
| ; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <4 x i8> %a, splat (i8 3) |
| %a2 = bitcast <4 x i8> %a1 to <2 x half> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <4 x i8> %a to <2 x half> |
| br label %end |
| |
| end: |
| %phi = phi <2 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <2 x half> %phi |
| } |
| |
| define <1 x i32> @bitcast_v2bf16_to_v1i32(<2 x bfloat> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v2bf16_to_v1i32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 |
| ; GCN-NEXT: v_mul_f32_e32 v1, 1.0, v1 |
| ; GCN-NEXT: v_mul_f32_e32 v2, 1.0, v0 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB36_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB36_4 |
| ; GCN-NEXT: .LBB36_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB36_3: ; %cmp.false |
| ; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v1 |
| ; GCN-NEXT: v_alignbit_b32 v0, v0, v2, 16 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB36_2 |
| ; GCN-NEXT: .LBB36_4: ; %cmp.true |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v2 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 |
| ; GCN-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; GCN-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v1 |
| ; GCN-NEXT: v_alignbit_b32 v0, v1, v0, 16 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v2bf16_to_v1i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB36_2 |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v0 |
| ; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 |
| ; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 |
| ; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc |
| ; VI-NEXT: v_bfe_u32 v2, v0, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 |
| ; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc |
| ; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 |
| ; VI-NEXT: v_alignbit_b32 v0, v0, v1, 16 |
| ; VI-NEXT: .LBB36_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v2bf16_to_v1i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB36_2 |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v0 |
| ; GFX9-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 |
| ; GFX9-NEXT: s_movk_i32 s6, 0x7fff |
| ; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; GFX9-NEXT: v_add3_u32 v2, v2, v1, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 |
| ; GFX9-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc |
| ; GFX9-NEXT: v_bfe_u32 v2, v0, 16, 1 |
| ; GFX9-NEXT: v_add3_u32 v2, v2, v0, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v0 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc |
| ; GFX9-NEXT: s_mov_b32 s6, 0x7060302 |
| ; GFX9-NEXT: v_perm_b32 v0, v0, v1, s6 |
| ; GFX9-NEXT: .LBB36_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-TRUE16-LABEL: bitcast_v2bf16_to_v1i32: |
| ; GFX11-TRUE16: ; %bb.0: |
| ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v1 |
| ; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB36_2 |
| ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0 |
| ; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0 |
| ; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1 |
| ; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1 |
| ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 |
| ; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0 |
| ; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff |
| ; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo |
| ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 |
| ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo |
| ; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v1, v0 |
| ; GFX11-TRUE16-NEXT: .LBB36_2: ; %end |
| ; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-FAKE16-LABEL: bitcast_v2bf16_to_v1i32: |
| ; GFX11-FAKE16: ; %bb.0: |
| ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v1 |
| ; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB36_2 |
| ; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0 |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-FAKE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0 |
| ; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v1, 16, 1 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1 |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v1 |
| ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v0 |
| ; GFX11-FAKE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff |
| ; GFX11-FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo |
| ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0x7060302 |
| ; GFX11-FAKE16-NEXT: .LBB36_2: ; %end |
| ; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <2 x bfloat> %a, splat (bfloat 0xR40C0) |
| %a2 = bitcast <2 x bfloat> %a1 to <1 x i32> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <2 x bfloat> %a to <1 x i32> |
| br label %end |
| |
| end: |
| %phi = phi <1 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <1 x i32> %phi |
| } |
| |
| define <2 x bfloat> @bitcast_v1i32_to_v2bf16(<1 x i32> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v1i32_to_v2bf16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v2, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB37_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB37_4 |
| ; GCN-NEXT: .LBB37_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB37_3: ; %cmp.false |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v2 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v2 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB37_2 |
| ; GCN-NEXT: .LBB37_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v2 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v1i32_to_v2bf16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: ; %bb.1: ; %cmp.true |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0 |
| ; VI-NEXT: ; %bb.2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v1i32_to_v2bf16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX9-NEXT: v_add_u32_e32 v0, 3, v0 |
| ; GFX9-NEXT: ; %bb.2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: bitcast_v1i32_to_v2bf16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v1 |
| ; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-NEXT: ; %bb.1: ; %cmp.true |
| ; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0 |
| ; GFX11-NEXT: ; %bb.2: ; %end |
| ; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <1 x i32> %a, splat (i32 3) |
| %a2 = bitcast <1 x i32> %a1 to <2 x bfloat> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <1 x i32> %a to <2 x bfloat> |
| br label %end |
| |
| end: |
| %phi = phi <2 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <2 x bfloat> %phi |
| } |
| |
| define <4 x i8> @bitcast_v2bf16_to_v4i8(<2 x bfloat> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v2bf16_to_v4i8: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 |
| ; GCN-NEXT: v_mul_f32_e32 v4, 1.0, v1 |
| ; GCN-NEXT: v_mul_f32_e32 v5, 1.0, v0 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB38_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB38_4 |
| ; GCN-NEXT: .LBB38_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB38_3: ; %cmp.false |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 24, v4 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v4 |
| ; GCN-NEXT: v_alignbit_b32 v0, v2, v5, 16 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB38_2 |
| ; GCN-NEXT: .LBB38_4: ; %cmp.true |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v5 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v4 |
| ; GCN-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; GCN-NEXT: v_add_f32_e32 v3, 0x40c00000, v1 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v3 |
| ; GCN-NEXT: v_alignbit_b32 v0, v2, v0, 16 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 24, v3 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v2bf16_to_v4i8: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: ; implicit-def: $vgpr1 |
| ; VI-NEXT: ; implicit-def: $vgpr2 |
| ; VI-NEXT: ; implicit-def: $vgpr3 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_cbranch_execnz .LBB38_3 |
| ; VI-NEXT: ; %bb.1: ; %Flow |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execnz .LBB38_4 |
| ; VI-NEXT: .LBB38_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; VI-NEXT: .LBB38_3: ; %cmp.false |
| ; VI-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB38_2 |
| ; VI-NEXT: .LBB38_4: ; %cmp.true |
| ; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v0 |
| ; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 |
| ; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 |
| ; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc |
| ; VI-NEXT: v_bfe_u32 v2, v0, 16, 1 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 |
| ; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0 |
| ; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc |
| ; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; VI-NEXT: v_alignbit_b32 v4, v2, v1, 16 |
| ; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v1 |
| ; VI-NEXT: v_lshrrev_b32_e32 v3, 24, v4 |
| ; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v4 |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v2bf16_to_v4i8: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: ; implicit-def: $vgpr1 |
| ; GFX9-NEXT: ; implicit-def: $vgpr2 |
| ; GFX9-NEXT: ; implicit-def: $vgpr3 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_cbranch_execnz .LBB38_3 |
| ; GFX9-NEXT: ; %bb.1: ; %Flow |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execnz .LBB38_4 |
| ; GFX9-NEXT: .LBB38_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; GFX9-NEXT: .LBB38_3: ; %cmp.false |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB38_2 |
| ; GFX9-NEXT: .LBB38_4: ; %cmp.true |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v0 |
| ; GFX9-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 |
| ; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 |
| ; GFX9-NEXT: s_movk_i32 s6, 0x7fff |
| ; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; GFX9-NEXT: v_add3_u32 v2, v2, v1, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 |
| ; GFX9-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc |
| ; GFX9-NEXT: v_bfe_u32 v2, v0, 16, 1 |
| ; GFX9-NEXT: v_add3_u32 v2, v2, v0, s6 |
| ; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v0 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc |
| ; GFX9-NEXT: s_mov_b32 s6, 0x7060302 |
| ; GFX9-NEXT: v_perm_b32 v4, v0, v1, s6 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v1 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v3, 24, v4 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v4 |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-TRUE16-LABEL: bitcast_v2bf16_to_v4i8: |
| ; GFX11-TRUE16: ; %bb.0: |
| ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, v0 |
| ; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16 |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16 |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16 |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16 |
| ; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v4 |
| ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v4 |
| ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v4.l |
| ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v4.h |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4 |
| ; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow |
| ; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB38_4 |
| ; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true |
| ; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v4 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v0, 16, v4 |
| ; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1 |
| ; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1 |
| ; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v0 |
| ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 |
| ; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1 |
| ; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff |
| ; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo |
| ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 |
| ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h |
| ; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc_lo |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0xffff, v1, v2 |
| ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v1 |
| ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1 |
| ; GFX11-TRUE16-NEXT: .LBB38_4: ; %end |
| ; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h |
| ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h |
| ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-FAKE16-LABEL: bitcast_v2bf16_to_v4i8: |
| ; GFX11-FAKE16: ; %bb.0: |
| ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr1 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr2 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr3 |
| ; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB38_3 |
| ; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow |
| ; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB38_4 |
| ; GFX11-FAKE16-NEXT: .LBB38_2: ; %end |
| ; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] |
| ; GFX11-FAKE16-NEXT: .LBB38_3: ; %cmp.false |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB38_2 |
| ; GFX11-FAKE16-NEXT: .LBB38_4: ; %cmp.true |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0 |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) |
| ; GFX11-FAKE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0 |
| ; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v1, 16, 1 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1 |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v1 |
| ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v0 |
| ; GFX11-FAKE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff |
| ; GFX11-FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo |
| ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 |
| ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) |
| ; GFX11-FAKE16-NEXT: v_perm_b32 v4, v0, v1, 0x7060302 |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1 |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 24, v4 |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v4 |
| ; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = fadd <2 x bfloat> %a, splat (bfloat 0xR40C0) |
| %a2 = bitcast <2 x bfloat> %a1 to <4 x i8> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <2 x bfloat> %a to <4 x i8> |
| br label %end |
| |
| end: |
| %phi = phi <4 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <4 x i8> %phi |
| } |
| |
| define <2 x bfloat> @bitcast_v4i8_to_v2bf16(<4 x i8> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v4i8_to_v2bf16: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v5, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v4, 24, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v3, 24, v3 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB39_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB39_4 |
| ; GCN-NEXT: .LBB39_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB39_3: ; %cmp.false |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xff, v5 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xff, v2 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GCN-NEXT: v_or_b32_e32 v0, v4, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v3, v1 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB39_2 |
| ; GCN-NEXT: .LBB39_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v2 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 3, v5 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xff, v0 |
| ; GCN-NEXT: v_and_b32_e32 v1, 0xff, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GCN-NEXT: v_or_b32_e32 v2, v3, v0 |
| ; GCN-NEXT: v_or_b32_e32 v0, v4, v1 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0 |
| ; GCN-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v2 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v4i8_to_v2bf16: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v5, v0 |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 |
| ; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v1 |
| ; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v3 |
| ; VI-NEXT: ; implicit-def: $vgpr0 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_cbranch_execnz .LBB39_3 |
| ; VI-NEXT: ; %bb.1: ; %Flow |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execnz .LBB39_4 |
| ; VI-NEXT: .LBB39_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; VI-NEXT: .LBB39_3: ; %cmp.false |
| ; VI-NEXT: v_or_b32_sdwa v0, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; VI-NEXT: ; implicit-def: $vgpr5 |
| ; VI-NEXT: ; implicit-def: $vgpr4 |
| ; VI-NEXT: ; implicit-def: $vgpr2 |
| ; VI-NEXT: ; implicit-def: $vgpr1 |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB39_2 |
| ; VI-NEXT: .LBB39_4: ; %cmp.true |
| ; VI-NEXT: v_add_u16_e32 v0, 3, v5 |
| ; VI-NEXT: v_add_u16_e32 v2, 3, v2 |
| ; VI-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_mov_b32_e32 v2, 0x300 |
| ; VI-NEXT: v_add_u16_e32 v0, 0x300, v0 |
| ; VI-NEXT: v_add_u16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v4i8_to_v2bf16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v5, v0 |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v1 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v3 |
| ; GFX9-NEXT: ; implicit-def: $vgpr0 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_cbranch_execnz .LBB39_3 |
| ; GFX9-NEXT: ; %bb.1: ; %Flow |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execnz .LBB39_4 |
| ; GFX9-NEXT: .LBB39_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; GFX9-NEXT: .LBB39_3: ; %cmp.false |
| ; GFX9-NEXT: v_or_b32_sdwa v0, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; GFX9-NEXT: ; implicit-def: $vgpr5 |
| ; GFX9-NEXT: ; implicit-def: $vgpr4 |
| ; GFX9-NEXT: ; implicit-def: $vgpr2 |
| ; GFX9-NEXT: ; implicit-def: $vgpr1 |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB39_2 |
| ; GFX9-NEXT: .LBB39_4: ; %cmp.true |
| ; GFX9-NEXT: v_add_u16_e32 v0, 3, v5 |
| ; GFX9-NEXT: v_add_u16_e32 v2, 3, v2 |
| ; GFX9-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: s_movk_i32 s6, 0x300 |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0 |
| ; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-TRUE16-LABEL: bitcast_v4i8_to_v2bf16: |
| ; GFX11-TRUE16: ; %bb.0: |
| ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.l |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v3.l |
| ; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0 |
| ; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v4 |
| ; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB39_3 |
| ; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow |
| ; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB39_4 |
| ; GFX11-TRUE16-NEXT: .LBB39_2: ; %end |
| ; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] |
| ; GFX11-TRUE16-NEXT: .LBB39_3: ; %cmp.false |
| ; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v2.h |
| ; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.l |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16 |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.l |
| ; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v0.h, v1.h |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16 |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16 |
| ; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB39_2 |
| ; GFX11-TRUE16-NEXT: .LBB39_4: ; %cmp.true |
| ; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v2.h, 3 |
| ; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v2.l, 3 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l |
| ; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l |
| ; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v0.h |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, 0x300, v0.l |
| ; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, 0x300, v0.h |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-FAKE16-LABEL: bitcast_v4i8_to_v2bf16: |
| ; GFX11-FAKE16: ; %bb.0: |
| ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v5, v0 |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v1 |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3 |
| ; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0 |
| ; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v4 |
| ; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB39_3 |
| ; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow |
| ; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB39_4 |
| ; GFX11-FAKE16-NEXT: .LBB39_2: ; %end |
| ; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] |
| ; GFX11-FAKE16-NEXT: .LBB39_3: ; %cmp.false |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v5 |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr5 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr2 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr3 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr1 |
| ; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB39_2 |
| ; GFX11-FAKE16-NEXT: .LBB39_4: ; %cmp.true |
| ; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v5, 3 |
| ; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v2, 3 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0 |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0 |
| ; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <4 x i8> %a, splat (i8 3) |
| %a2 = bitcast <4 x i8> %a1 to <2 x bfloat> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <4 x i8> %a to <2 x bfloat> |
| br label %end |
| |
| end: |
| %phi = phi <2 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <2 x bfloat> %phi |
| } |
| |
| define <4 x i8> @bitcast_v1i32_to_v4i8(<1 x i32> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v1i32_to_v4i8: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr3 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB40_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB40_4 |
| ; GCN-NEXT: .LBB40_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB40_3: ; %cmp.false |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB40_2 |
| ; GCN-NEXT: .LBB40_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; GCN-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v1i32_to_v4i8: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: ; implicit-def: $vgpr1 |
| ; VI-NEXT: ; implicit-def: $vgpr2 |
| ; VI-NEXT: ; implicit-def: $vgpr3 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_cbranch_execnz .LBB40_3 |
| ; VI-NEXT: ; %bb.1: ; %Flow |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execnz .LBB40_4 |
| ; VI-NEXT: .LBB40_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; VI-NEXT: .LBB40_3: ; %cmp.false |
| ; VI-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB40_2 |
| ; VI-NEXT: .LBB40_4: ; %cmp.true |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0 |
| ; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; VI-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v1i32_to_v4i8: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; GFX9-NEXT: ; implicit-def: $vgpr1 |
| ; GFX9-NEXT: ; implicit-def: $vgpr2 |
| ; GFX9-NEXT: ; implicit-def: $vgpr3 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_cbranch_execnz .LBB40_3 |
| ; GFX9-NEXT: ; %bb.1: ; %Flow |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execnz .LBB40_4 |
| ; GFX9-NEXT: .LBB40_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; GFX9-NEXT: .LBB40_3: ; %cmp.false |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB40_2 |
| ; GFX9-NEXT: .LBB40_4: ; %cmp.true |
| ; GFX9-NEXT: v_add_u32_e32 v0, 3, v0 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-TRUE16-LABEL: bitcast_v1i32_to_v4i8: |
| ; GFX11-TRUE16: ; %bb.0: |
| ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v0 |
| ; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16 |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16 |
| ; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v2 |
| ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2 |
| ; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow |
| ; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true |
| ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v2 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v2 |
| ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2 |
| ; GFX11-TRUE16-NEXT: ; %bb.4: ; %end |
| ; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l |
| ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h |
| ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-FAKE16-LABEL: bitcast_v1i32_to_v4i8: |
| ; GFX11-FAKE16: ; %bb.0: |
| ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr1 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr2 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr3 |
| ; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB40_3 |
| ; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow |
| ; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB40_4 |
| ; GFX11-FAKE16-NEXT: .LBB40_2: ; %end |
| ; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] |
| ; GFX11-FAKE16-NEXT: .LBB40_3: ; %cmp.false |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB40_2 |
| ; GFX11-FAKE16-NEXT: .LBB40_4: ; %cmp.true |
| ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 3, v0 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 24, v0 |
| ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0 |
| ; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <1 x i32> %a, splat (i32 3) |
| %a2 = bitcast <1 x i32> %a1 to <4 x i8> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <1 x i32> %a to <4 x i8> |
| br label %end |
| |
| end: |
| %phi = phi <4 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <4 x i8> %phi |
| } |
| |
| define <1 x i32> @bitcast_v4i8_to_v1i32(<4 x i8> %a, i32 %b) { |
| ; GCN-LABEL: bitcast_v4i8_to_v1i32: |
| ; GCN: ; %bb.0: |
| ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GCN-NEXT: v_mov_b32_e32 v5, v0 |
| ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v4, 8, v1 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v1, 24, v3 |
| ; GCN-NEXT: ; implicit-def: $vgpr0 |
| ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB41_3 |
| ; GCN-NEXT: ; %bb.1: ; %Flow |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execnz .LBB41_4 |
| ; GCN-NEXT: .LBB41_2: ; %end |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; GCN-NEXT: .LBB41_3: ; %cmp.false |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xff, v5 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xff, v2 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v4 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v1, v2 |
| ; GCN-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GCN-NEXT: ; implicit-def: $vgpr5 |
| ; GCN-NEXT: ; implicit-def: $vgpr4 |
| ; GCN-NEXT: ; implicit-def: $vgpr2 |
| ; GCN-NEXT: ; implicit-def: $vgpr1 |
| ; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GCN-NEXT: s_cbranch_execz .LBB41_2 |
| ; GCN-NEXT: .LBB41_4: ; %cmp.true |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v5 |
| ; GCN-NEXT: v_add_i32_e32 v2, vcc, 3, v2 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xff, v0 |
| ; GCN-NEXT: v_and_b32_e32 v2, 0xff, v2 |
| ; GCN-NEXT: v_or_b32_e32 v0, v4, v0 |
| ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0 |
| ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GCN-NEXT: v_or_b32_e32 v1, v1, v2 |
| ; GCN-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; GCN-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0 |
| ; GCN-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GCN-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; VI-LABEL: bitcast_v4i8_to_v1i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v5, v0 |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 |
| ; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v1 |
| ; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v3 |
| ; VI-NEXT: ; implicit-def: $vgpr0 |
| ; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; VI-NEXT: s_cbranch_execnz .LBB41_3 |
| ; VI-NEXT: ; %bb.1: ; %Flow |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execnz .LBB41_4 |
| ; VI-NEXT: .LBB41_2: ; %end |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; VI-NEXT: .LBB41_3: ; %cmp.false |
| ; VI-NEXT: v_or_b32_sdwa v0, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; VI-NEXT: ; implicit-def: $vgpr5 |
| ; VI-NEXT: ; implicit-def: $vgpr4 |
| ; VI-NEXT: ; implicit-def: $vgpr2 |
| ; VI-NEXT: ; implicit-def: $vgpr1 |
| ; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; VI-NEXT: s_cbranch_execz .LBB41_2 |
| ; VI-NEXT: .LBB41_4: ; %cmp.true |
| ; VI-NEXT: v_add_u16_e32 v0, 3, v5 |
| ; VI-NEXT: v_add_u16_e32 v2, 3, v2 |
| ; VI-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; VI-NEXT: v_mov_b32_e32 v2, 0x300 |
| ; VI-NEXT: v_add_u16_e32 v0, 0x300, v0 |
| ; VI-NEXT: v_add_u16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; VI-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; VI-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX9-LABEL: bitcast_v4i8_to_v1i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v5, v0 |
| ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v1 |
| ; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v3 |
| ; GFX9-NEXT: ; implicit-def: $vgpr0 |
| ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc |
| ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5] |
| ; GFX9-NEXT: s_cbranch_execnz .LBB41_3 |
| ; GFX9-NEXT: ; %bb.1: ; %Flow |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execnz .LBB41_4 |
| ; GFX9-NEXT: .LBB41_2: ; %end |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; GFX9-NEXT: .LBB41_3: ; %cmp.false |
| ; GFX9-NEXT: v_or_b32_sdwa v0, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD |
| ; GFX9-NEXT: ; implicit-def: $vgpr5 |
| ; GFX9-NEXT: ; implicit-def: $vgpr4 |
| ; GFX9-NEXT: ; implicit-def: $vgpr2 |
| ; GFX9-NEXT: ; implicit-def: $vgpr1 |
| ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] |
| ; GFX9-NEXT: s_cbranch_execz .LBB41_2 |
| ; GFX9-NEXT: .LBB41_4: ; %cmp.true |
| ; GFX9-NEXT: v_add_u16_e32 v0, 3, v5 |
| ; GFX9-NEXT: v_add_u16_e32 v2, 3, v2 |
| ; GFX9-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: s_movk_i32 s6, 0x300 |
| ; GFX9-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 |
| ; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0 |
| ; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD |
| ; GFX9-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-TRUE16-LABEL: bitcast_v4i8_to_v1i32: |
| ; GFX11-TRUE16: ; %bb.0: |
| ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.l |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v3.l |
| ; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0 |
| ; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v4 |
| ; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB41_3 |
| ; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow |
| ; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB41_4 |
| ; GFX11-TRUE16-NEXT: .LBB41_2: ; %end |
| ; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] |
| ; GFX11-TRUE16-NEXT: .LBB41_3: ; %cmp.false |
| ; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v2.h |
| ; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.l |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16 |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.l |
| ; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v0.h, v1.h |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16 |
| ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_hi16 |
| ; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB41_2 |
| ; GFX11-TRUE16-NEXT: .LBB41_4: ; %cmp.true |
| ; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v2.h, 3 |
| ; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v2.l, 3 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l |
| ; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l |
| ; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v0.h |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, 0x300, v0.l |
| ; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, 0x300, v0.h |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-FAKE16-LABEL: bitcast_v4i8_to_v1i32: |
| ; GFX11-FAKE16: ; %bb.0: |
| ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v5, v0 |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v1 |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3 |
| ; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0 |
| ; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v4 |
| ; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB41_3 |
| ; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow |
| ; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB41_4 |
| ; GFX11-FAKE16-NEXT: .LBB41_2: ; %end |
| ; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] |
| ; GFX11-FAKE16-NEXT: .LBB41_3: ; %cmp.false |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v5 |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr5 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr2 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr3 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr1 |
| ; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0 |
| ; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB41_2 |
| ; GFX11-FAKE16-NEXT: .LBB41_4: ; %cmp.true |
| ; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v5, 3 |
| ; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v2, 3 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0 |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0 |
| ; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 |
| ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] |
| %cmp = icmp eq i32 %b, 0 |
| br i1 %cmp, label %cmp.true, label %cmp.false |
| |
| cmp.true: |
| %a1 = add <4 x i8> %a, splat (i8 3) |
| %a2 = bitcast <4 x i8> %a1 to <1 x i32> |
| br label %end |
| |
| cmp.false: |
| %a3 = bitcast <4 x i8> %a to <1 x i32> |
| br label %end |
| |
| end: |
| %phi = phi <1 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ] |
| ret <1 x i32> %phi |
| } |
