| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 |
| ; RUN: llc -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=CI %s |
| ; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=VI %s |
| ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s |
| |
| declare i32 @llvm.amdgcn.atomic.inc.i32.p1(ptr addrspace(1) nocapture, i32, i32, i32, i1) #2 |
| declare i32 @llvm.amdgcn.atomic.inc.i32.p3(ptr addrspace(3) nocapture, i32, i32, i32, i1) #2 |
| declare i32 @llvm.amdgcn.atomic.inc.i32.p0(ptr nocapture, i32, i32, i32, i1) #2 |
| |
| declare i64 @llvm.amdgcn.atomic.inc.i64.p1(ptr addrspace(1) nocapture, i64, i32, i32, i1) #2 |
| declare i64 @llvm.amdgcn.atomic.inc.i64.p3(ptr addrspace(3) nocapture, i64, i32, i32, i1) #2 |
| declare i64 @llvm.amdgcn.atomic.inc.i64.p0(ptr nocapture, i64, i32, i32, i1) #2 |
| |
| declare i32 @llvm.amdgcn.workitem.id.x() #1 |
| |
| define amdgpu_kernel void @lds_atomic_inc_ret_i32(ptr addrspace(1) %out, ptr addrspace(3) %ptr) #0 { |
| ; CI-LABEL: lds_atomic_inc_ret_i32: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dword s2, s[4:5], 0xb |
| ; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 |
| ; CI-NEXT: v_mov_b32_e32 v0, 42 |
| ; CI-NEXT: s_mov_b32 m0, -1 |
| ; CI-NEXT: s_mov_b32 s3, 0xf000 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_mov_b32_e32 v1, s2 |
| ; CI-NEXT: ds_inc_rtn_u32 v0, v1, v0 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_mov_b32 s2, -1 |
| ; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: lds_atomic_inc_ret_i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dword s2, s[4:5], 0x2c |
| ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; VI-NEXT: v_mov_b32_e32 v0, 42 |
| ; VI-NEXT: s_mov_b32 m0, -1 |
| ; VI-NEXT: s_mov_b32 s3, 0xf000 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v1, s2 |
| ; VI-NEXT: ds_inc_rtn_u32 v0, v1, v0 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_mov_b32 s2, -1 |
| ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 |
| ; VI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: lds_atomic_inc_ret_i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c |
| ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 42 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v1, s2 |
| ; GFX9-NEXT: ds_inc_rtn_u32 v0, v1, v0 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 0 |
| ; GFX9-NEXT: global_store_dword v1, v0, s[0:1] |
| ; GFX9-NEXT: s_endpgm |
| %result = call i32 @llvm.amdgcn.atomic.inc.i32.p3(ptr addrspace(3) %ptr, i32 42, i32 0, i32 0, i1 false) |
| store i32 %result, ptr addrspace(1) %out |
| ret void |
| } |
| |
| define amdgpu_kernel void @lds_atomic_inc_ret_i32_offset(ptr addrspace(1) %out, ptr addrspace(3) %ptr) #0 { |
| ; CI-LABEL: lds_atomic_inc_ret_i32_offset: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dword s2, s[4:5], 0xb |
| ; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 |
| ; CI-NEXT: v_mov_b32_e32 v0, 42 |
| ; CI-NEXT: s_mov_b32 m0, -1 |
| ; CI-NEXT: s_mov_b32 s3, 0xf000 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_mov_b32_e32 v1, s2 |
| ; CI-NEXT: ds_inc_rtn_u32 v0, v1, v0 offset:16 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_mov_b32 s2, -1 |
| ; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: lds_atomic_inc_ret_i32_offset: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dword s2, s[4:5], 0x2c |
| ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; VI-NEXT: v_mov_b32_e32 v0, 42 |
| ; VI-NEXT: s_mov_b32 m0, -1 |
| ; VI-NEXT: s_mov_b32 s3, 0xf000 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v1, s2 |
| ; VI-NEXT: ds_inc_rtn_u32 v0, v1, v0 offset:16 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_mov_b32 s2, -1 |
| ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 |
| ; VI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: lds_atomic_inc_ret_i32_offset: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c |
| ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 42 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v1, s2 |
| ; GFX9-NEXT: ds_inc_rtn_u32 v0, v1, v0 offset:16 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 0 |
| ; GFX9-NEXT: global_store_dword v1, v0, s[0:1] |
| ; GFX9-NEXT: s_endpgm |
| %gep = getelementptr i32, ptr addrspace(3) %ptr, i32 4 |
| %result = call i32 @llvm.amdgcn.atomic.inc.i32.p3(ptr addrspace(3) %gep, i32 42, i32 0, i32 0, i1 false) |
| store i32 %result, ptr addrspace(1) %out |
| ret void |
| } |
| |
| define amdgpu_kernel void @lds_atomic_inc_noret_i32(ptr addrspace(3) %ptr) nounwind { |
| ; CI-LABEL: lds_atomic_inc_noret_i32: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dword s0, s[4:5], 0x9 |
| ; CI-NEXT: v_mov_b32_e32 v0, 42 |
| ; CI-NEXT: s_mov_b32 m0, -1 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_mov_b32_e32 v1, s0 |
| ; CI-NEXT: ds_inc_u32 v1, v0 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: lds_atomic_inc_noret_i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dword s0, s[4:5], 0x24 |
| ; VI-NEXT: v_mov_b32_e32 v0, 42 |
| ; VI-NEXT: s_mov_b32 m0, -1 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v1, s0 |
| ; VI-NEXT: ds_inc_u32 v1, v0 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: lds_atomic_inc_noret_i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dword s0, s[4:5], 0x24 |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 42 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v1, s0 |
| ; GFX9-NEXT: ds_inc_u32 v1, v0 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: s_endpgm |
| %result = call i32 @llvm.amdgcn.atomic.inc.i32.p3(ptr addrspace(3) %ptr, i32 42, i32 0, i32 0, i1 false) |
| ret void |
| } |
| |
| define amdgpu_kernel void @lds_atomic_inc_noret_i32_offset(ptr addrspace(3) %ptr) nounwind { |
| ; CI-LABEL: lds_atomic_inc_noret_i32_offset: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dword s0, s[4:5], 0x9 |
| ; CI-NEXT: v_mov_b32_e32 v0, 42 |
| ; CI-NEXT: s_mov_b32 m0, -1 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_mov_b32_e32 v1, s0 |
| ; CI-NEXT: ds_inc_u32 v1, v0 offset:16 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: lds_atomic_inc_noret_i32_offset: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dword s0, s[4:5], 0x24 |
| ; VI-NEXT: v_mov_b32_e32 v0, 42 |
| ; VI-NEXT: s_mov_b32 m0, -1 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v1, s0 |
| ; VI-NEXT: ds_inc_u32 v1, v0 offset:16 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: lds_atomic_inc_noret_i32_offset: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dword s0, s[4:5], 0x24 |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 42 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v1, s0 |
| ; GFX9-NEXT: ds_inc_u32 v1, v0 offset:16 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: s_endpgm |
| %gep = getelementptr i32, ptr addrspace(3) %ptr, i32 4 |
| %result = call i32 @llvm.amdgcn.atomic.inc.i32.p3(ptr addrspace(3) %gep, i32 42, i32 0, i32 0, i1 false) |
| ret void |
| } |
| |
| define amdgpu_kernel void @global_atomic_inc_ret_i32(ptr addrspace(1) %out, ptr addrspace(1) %ptr) #0 { |
| ; CI-LABEL: global_atomic_inc_ret_i32: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 |
| ; CI-NEXT: s_mov_b32 s7, 0xf000 |
| ; CI-NEXT: s_mov_b32 s6, -1 |
| ; CI-NEXT: s_mov_b32 s10, s6 |
| ; CI-NEXT: s_mov_b32 s11, s7 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_mov_b32 s8, s2 |
| ; CI-NEXT: s_mov_b32 s9, s3 |
| ; CI-NEXT: v_mov_b32_e32 v0, 42 |
| ; CI-NEXT: buffer_atomic_inc v0, off, s[8:11], 0 glc |
| ; CI-NEXT: s_waitcnt vmcnt(0) |
| ; CI-NEXT: buffer_wbinvl1_vol |
| ; CI-NEXT: s_mov_b32 s4, s0 |
| ; CI-NEXT: s_mov_b32 s5, s1 |
| ; CI-NEXT: buffer_store_dword v0, off, s[4:7], 0 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: global_atomic_inc_ret_i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; VI-NEXT: s_mov_b32 s7, 0xf000 |
| ; VI-NEXT: s_mov_b32 s6, -1 |
| ; VI-NEXT: s_mov_b32 s10, s6 |
| ; VI-NEXT: s_mov_b32 s11, s7 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_mov_b32 s8, s2 |
| ; VI-NEXT: s_mov_b32 s9, s3 |
| ; VI-NEXT: v_mov_b32_e32 v0, 42 |
| ; VI-NEXT: buffer_atomic_inc v0, off, s[8:11], 0 glc |
| ; VI-NEXT: s_waitcnt vmcnt(0) |
| ; VI-NEXT: buffer_wbinvl1_vol |
| ; VI-NEXT: s_mov_b32 s4, s0 |
| ; VI-NEXT: s_mov_b32 s5, s1 |
| ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 |
| ; VI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: global_atomic_inc_ret_i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 0 |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 42 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: global_atomic_inc v1, v0, v1, s[2:3] glc |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) |
| ; GFX9-NEXT: buffer_wbinvl1_vol |
| ; GFX9-NEXT: global_store_dword v0, v1, s[0:1] |
| ; GFX9-NEXT: s_endpgm |
| %result = call i32 @llvm.amdgcn.atomic.inc.i32.p1(ptr addrspace(1) %ptr, i32 42, i32 0, i32 0, i1 false) |
| store i32 %result, ptr addrspace(1) %out |
| ret void |
| } |
| |
| define amdgpu_kernel void @global_atomic_inc_ret_i32_offset(ptr addrspace(1) %out, ptr addrspace(1) %ptr) #0 { |
| ; CI-LABEL: global_atomic_inc_ret_i32_offset: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 |
| ; CI-NEXT: s_mov_b32 s7, 0xf000 |
| ; CI-NEXT: s_mov_b32 s6, -1 |
| ; CI-NEXT: s_mov_b32 s10, s6 |
| ; CI-NEXT: s_mov_b32 s11, s7 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_mov_b32 s8, s2 |
| ; CI-NEXT: s_mov_b32 s9, s3 |
| ; CI-NEXT: v_mov_b32_e32 v0, 42 |
| ; CI-NEXT: buffer_atomic_inc v0, off, s[8:11], 0 offset:16 glc |
| ; CI-NEXT: s_waitcnt vmcnt(0) |
| ; CI-NEXT: buffer_wbinvl1_vol |
| ; CI-NEXT: s_mov_b32 s4, s0 |
| ; CI-NEXT: s_mov_b32 s5, s1 |
| ; CI-NEXT: buffer_store_dword v0, off, s[4:7], 0 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: global_atomic_inc_ret_i32_offset: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; VI-NEXT: s_mov_b32 s7, 0xf000 |
| ; VI-NEXT: s_mov_b32 s6, -1 |
| ; VI-NEXT: s_mov_b32 s10, s6 |
| ; VI-NEXT: s_mov_b32 s11, s7 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_mov_b32 s8, s2 |
| ; VI-NEXT: s_mov_b32 s9, s3 |
| ; VI-NEXT: v_mov_b32_e32 v0, 42 |
| ; VI-NEXT: buffer_atomic_inc v0, off, s[8:11], 0 offset:16 glc |
| ; VI-NEXT: s_waitcnt vmcnt(0) |
| ; VI-NEXT: buffer_wbinvl1_vol |
| ; VI-NEXT: s_mov_b32 s4, s0 |
| ; VI-NEXT: s_mov_b32 s5, s1 |
| ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 |
| ; VI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: global_atomic_inc_ret_i32_offset: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 0 |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 42 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: global_atomic_inc v1, v0, v1, s[2:3] offset:16 glc |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) |
| ; GFX9-NEXT: buffer_wbinvl1_vol |
| ; GFX9-NEXT: global_store_dword v0, v1, s[0:1] |
| ; GFX9-NEXT: s_endpgm |
| %gep = getelementptr i32, ptr addrspace(1) %ptr, i32 4 |
| %result = call i32 @llvm.amdgcn.atomic.inc.i32.p1(ptr addrspace(1) %gep, i32 42, i32 0, i32 0, i1 false) |
| store i32 %result, ptr addrspace(1) %out |
| ret void |
| } |
| |
| define amdgpu_kernel void @global_atomic_inc_noret_i32(ptr addrspace(1) %ptr) nounwind { |
| ; CI-LABEL: global_atomic_inc_noret_i32: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 |
| ; CI-NEXT: s_mov_b32 s3, 0xf000 |
| ; CI-NEXT: s_mov_b32 s2, -1 |
| ; CI-NEXT: v_mov_b32_e32 v0, 42 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: buffer_atomic_inc v0, off, s[0:3], 0 |
| ; CI-NEXT: s_waitcnt vmcnt(0) |
| ; CI-NEXT: buffer_wbinvl1_vol |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: global_atomic_inc_noret_i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; VI-NEXT: s_mov_b32 s3, 0xf000 |
| ; VI-NEXT: s_mov_b32 s2, -1 |
| ; VI-NEXT: v_mov_b32_e32 v0, 42 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: buffer_atomic_inc v0, off, s[0:3], 0 |
| ; VI-NEXT: s_waitcnt vmcnt(0) |
| ; VI-NEXT: buffer_wbinvl1_vol |
| ; VI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: global_atomic_inc_noret_i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 0 |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 42 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: global_atomic_inc v0, v1, s[0:1] |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) |
| ; GFX9-NEXT: buffer_wbinvl1_vol |
| ; GFX9-NEXT: s_endpgm |
| %result = call i32 @llvm.amdgcn.atomic.inc.i32.p1(ptr addrspace(1) %ptr, i32 42, i32 0, i32 0, i1 false) |
| ret void |
| } |
| |
| define amdgpu_kernel void @global_atomic_inc_noret_i32_offset(ptr addrspace(1) %ptr) nounwind { |
| ; CI-LABEL: global_atomic_inc_noret_i32_offset: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 |
| ; CI-NEXT: s_mov_b32 s3, 0xf000 |
| ; CI-NEXT: s_mov_b32 s2, -1 |
| ; CI-NEXT: v_mov_b32_e32 v0, 42 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: buffer_atomic_inc v0, off, s[0:3], 0 offset:16 |
| ; CI-NEXT: s_waitcnt vmcnt(0) |
| ; CI-NEXT: buffer_wbinvl1_vol |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: global_atomic_inc_noret_i32_offset: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; VI-NEXT: s_mov_b32 s3, 0xf000 |
| ; VI-NEXT: s_mov_b32 s2, -1 |
| ; VI-NEXT: v_mov_b32_e32 v0, 42 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: buffer_atomic_inc v0, off, s[0:3], 0 offset:16 |
| ; VI-NEXT: s_waitcnt vmcnt(0) |
| ; VI-NEXT: buffer_wbinvl1_vol |
| ; VI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: global_atomic_inc_noret_i32_offset: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 0 |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 42 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: global_atomic_inc v0, v1, s[0:1] offset:16 |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) |
| ; GFX9-NEXT: buffer_wbinvl1_vol |
| ; GFX9-NEXT: s_endpgm |
| %gep = getelementptr i32, ptr addrspace(1) %ptr, i32 4 |
| %result = call i32 @llvm.amdgcn.atomic.inc.i32.p1(ptr addrspace(1) %gep, i32 42, i32 0, i32 0, i1 false) |
| ret void |
| } |
| |
| define amdgpu_kernel void @global_atomic_inc_ret_i32_offset_addr64(ptr addrspace(1) %out, ptr addrspace(1) %ptr) #0 { |
| ; CI-LABEL: global_atomic_inc_ret_i32_offset_addr64: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 |
| ; CI-NEXT: s_mov_b32 s7, 0xf000 |
| ; CI-NEXT: s_mov_b32 s6, 0 |
| ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 |
| ; CI-NEXT: v_mov_b32_e32 v1, 0 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_mov_b64 s[8:9], s[2:3] |
| ; CI-NEXT: s_mov_b64 s[10:11], s[6:7] |
| ; CI-NEXT: v_mov_b32_e32 v2, 42 |
| ; CI-NEXT: buffer_atomic_inc v2, v[0:1], s[8:11], 0 addr64 offset:20 glc |
| ; CI-NEXT: s_waitcnt vmcnt(0) |
| ; CI-NEXT: buffer_wbinvl1_vol |
| ; CI-NEXT: s_mov_b64 s[4:5], s[0:1] |
| ; CI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: global_atomic_inc_ret_i32_offset_addr64: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v0, s3 |
| ; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v2 |
| ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v0, vcc |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 20, v1 |
| ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc |
| ; VI-NEXT: v_mov_b32_e32 v3, 42 |
| ; VI-NEXT: flat_atomic_inc v3, v[0:1], v3 glc |
| ; VI-NEXT: s_waitcnt vmcnt(0) |
| ; VI-NEXT: buffer_wbinvl1_vol |
| ; VI-NEXT: v_mov_b32_e32 v1, s1 |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 |
| ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc |
| ; VI-NEXT: flat_store_dword v[0:1], v3 |
| ; VI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: global_atomic_inc_ret_i32_offset_addr64: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 42 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: global_atomic_inc v1, v0, v1, s[2:3] offset:20 glc |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) |
| ; GFX9-NEXT: buffer_wbinvl1_vol |
| ; GFX9-NEXT: global_store_dword v0, v1, s[0:1] |
| ; GFX9-NEXT: s_endpgm |
| %id = call i32 @llvm.amdgcn.workitem.id.x() |
| %gep.tid = getelementptr i32, ptr addrspace(1) %ptr, i32 %id |
| %out.gep = getelementptr i32, ptr addrspace(1) %out, i32 %id |
| %gep = getelementptr i32, ptr addrspace(1) %gep.tid, i32 5 |
| %result = call i32 @llvm.amdgcn.atomic.inc.i32.p1(ptr addrspace(1) %gep, i32 42, i32 0, i32 0, i1 false) |
| store i32 %result, ptr addrspace(1) %out.gep |
| ret void |
| } |
| |
| define amdgpu_kernel void @global_atomic_inc_noret_i32_offset_addr64(ptr addrspace(1) %ptr) #0 { |
| ; CI-LABEL: global_atomic_inc_noret_i32_offset_addr64: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 |
| ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 |
| ; CI-NEXT: v_mov_b32_e32 v1, 0 |
| ; CI-NEXT: s_mov_b32 s3, 0xf000 |
| ; CI-NEXT: s_mov_b32 s2, 0 |
| ; CI-NEXT: v_mov_b32_e32 v2, 42 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: buffer_atomic_inc v2, v[0:1], s[0:3], 0 addr64 offset:20 |
| ; CI-NEXT: s_waitcnt vmcnt(0) |
| ; CI-NEXT: buffer_wbinvl1_vol |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: global_atomic_inc_noret_i32_offset_addr64: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 |
| ; VI-NEXT: v_mov_b32_e32 v2, 42 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v1, s1 |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0 |
| ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 20, v0 |
| ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc |
| ; VI-NEXT: flat_atomic_inc v[0:1], v2 |
| ; VI-NEXT: s_waitcnt vmcnt(0) |
| ; VI-NEXT: buffer_wbinvl1_vol |
| ; VI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: global_atomic_inc_noret_i32_offset_addr64: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 42 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: global_atomic_inc v0, v1, s[0:1] offset:20 |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) |
| ; GFX9-NEXT: buffer_wbinvl1_vol |
| ; GFX9-NEXT: s_endpgm |
| %id = call i32 @llvm.amdgcn.workitem.id.x() |
| %gep.tid = getelementptr i32, ptr addrspace(1) %ptr, i32 %id |
| %gep = getelementptr i32, ptr addrspace(1) %gep.tid, i32 5 |
| %result = call i32 @llvm.amdgcn.atomic.inc.i32.p1(ptr addrspace(1) %gep, i32 42, i32 0, i32 0, i1 false) |
| ret void |
| } |
| |
| @lds0 = addrspace(3) global [512 x i32] poison, align 4 |
| |
| define amdgpu_kernel void @atomic_inc_shl_base_lds_0_i32(ptr addrspace(1) %out, ptr addrspace(1) %add_use) #0 { |
| ; CI-LABEL: atomic_inc_shl_base_lds_0_i32: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 |
| ; CI-NEXT: v_lshlrev_b32_e32 v1, 2, v0 |
| ; CI-NEXT: v_mov_b32_e32 v2, 9 |
| ; CI-NEXT: s_mov_b32 m0, -1 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: ds_inc_rtn_u32 v1, v1, v2 offset:8 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_mov_b32 s7, 0xf000 |
| ; CI-NEXT: s_mov_b32 s6, -1 |
| ; CI-NEXT: s_mov_b32 s4, s0 |
| ; CI-NEXT: s_mov_b32 s5, s1 |
| ; CI-NEXT: s_mov_b32 s0, s2 |
| ; CI-NEXT: s_mov_b32 s1, s3 |
| ; CI-NEXT: s_mov_b32 s2, s6 |
| ; CI-NEXT: s_mov_b32 s3, s7 |
| ; CI-NEXT: v_add_i32_e32 v0, vcc, 2, v0 |
| ; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0 |
| ; CI-NEXT: buffer_store_dword v1, off, s[4:7], 0 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: atomic_inc_shl_base_lds_0_i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v0 |
| ; VI-NEXT: v_mov_b32_e32 v2, 9 |
| ; VI-NEXT: s_mov_b32 m0, -1 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: ds_inc_rtn_u32 v1, v1, v2 offset:8 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_mov_b32 s7, 0xf000 |
| ; VI-NEXT: s_mov_b32 s6, -1 |
| ; VI-NEXT: s_mov_b32 s4, s0 |
| ; VI-NEXT: s_mov_b32 s5, s1 |
| ; VI-NEXT: s_mov_b32 s0, s2 |
| ; VI-NEXT: s_mov_b32 s1, s3 |
| ; VI-NEXT: s_mov_b32 s2, s6 |
| ; VI-NEXT: s_mov_b32 s3, s7 |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0 |
| ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 |
| ; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0 |
| ; VI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: atomic_inc_shl_base_lds_0_i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v0 |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 9 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: ds_inc_rtn_u32 v1, v1, v2 offset:8 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 0 |
| ; GFX9-NEXT: v_add_u32_e32 v0, 2, v0 |
| ; GFX9-NEXT: global_store_dword v2, v0, s[2:3] |
| ; GFX9-NEXT: global_store_dword v2, v1, s[0:1] |
| ; GFX9-NEXT: s_endpgm |
| %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 |
| %idx.0 = add nsw i32 %tid.x, 2 |
| %arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds0, i32 0, i32 %idx.0 |
| %val0 = call i32 @llvm.amdgcn.atomic.inc.i32.p3(ptr addrspace(3) %arrayidx0, i32 9, i32 0, i32 0, i1 false) |
| store i32 %idx.0, ptr addrspace(1) %add_use |
| store i32 %val0, ptr addrspace(1) %out |
| ret void |
| } |
| |
| define amdgpu_kernel void @lds_atomic_inc_ret_i64(ptr addrspace(1) %out, ptr addrspace(3) %ptr) #0 { |
| ; CI-LABEL: lds_atomic_inc_ret_i64: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dword s2, s[4:5], 0xb |
| ; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 |
| ; CI-NEXT: v_mov_b32_e32 v0, 42 |
| ; CI-NEXT: v_mov_b32_e32 v1, 0 |
| ; CI-NEXT: s_mov_b32 m0, -1 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_mov_b32_e32 v2, s2 |
| ; CI-NEXT: ds_inc_rtn_u64 v[0:1], v2, v[0:1] |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_mov_b32 s3, 0xf000 |
| ; CI-NEXT: s_mov_b32 s2, -1 |
| ; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: lds_atomic_inc_ret_i64: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dword s2, s[4:5], 0x2c |
| ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; VI-NEXT: v_mov_b32_e32 v0, 42 |
| ; VI-NEXT: v_mov_b32_e32 v1, 0 |
| ; VI-NEXT: s_mov_b32 m0, -1 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v2, s2 |
| ; VI-NEXT: ds_inc_rtn_u64 v[0:1], v2, v[0:1] |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_mov_b32 s3, 0xf000 |
| ; VI-NEXT: s_mov_b32 s2, -1 |
| ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 |
| ; VI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: lds_atomic_inc_ret_i64: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c |
| ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 42 |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 0 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v2, s2 |
| ; GFX9-NEXT: ds_inc_rtn_u64 v[0:1], v2, v[0:1] |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 0 |
| ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] |
| ; GFX9-NEXT: s_endpgm |
| %result = call i64 @llvm.amdgcn.atomic.inc.i64.p3(ptr addrspace(3) %ptr, i64 42, i32 0, i32 0, i1 false) |
| store i64 %result, ptr addrspace(1) %out |
| ret void |
| } |
| |
| define amdgpu_kernel void @lds_atomic_inc_ret_i64_offset(ptr addrspace(1) %out, ptr addrspace(3) %ptr) #0 { |
| ; CI-LABEL: lds_atomic_inc_ret_i64_offset: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dword s2, s[4:5], 0xb |
| ; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 |
| ; CI-NEXT: v_mov_b32_e32 v0, 42 |
| ; CI-NEXT: v_mov_b32_e32 v1, 0 |
| ; CI-NEXT: s_mov_b32 m0, -1 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_mov_b32_e32 v2, s2 |
| ; CI-NEXT: ds_inc_rtn_u64 v[0:1], v2, v[0:1] offset:32 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_mov_b32 s3, 0xf000 |
| ; CI-NEXT: s_mov_b32 s2, -1 |
| ; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: lds_atomic_inc_ret_i64_offset: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dword s2, s[4:5], 0x2c |
| ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; VI-NEXT: v_mov_b32_e32 v0, 42 |
| ; VI-NEXT: v_mov_b32_e32 v1, 0 |
| ; VI-NEXT: s_mov_b32 m0, -1 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v2, s2 |
| ; VI-NEXT: ds_inc_rtn_u64 v[0:1], v2, v[0:1] offset:32 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_mov_b32 s3, 0xf000 |
| ; VI-NEXT: s_mov_b32 s2, -1 |
| ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 |
| ; VI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: lds_atomic_inc_ret_i64_offset: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c |
| ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 42 |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 0 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v2, s2 |
| ; GFX9-NEXT: ds_inc_rtn_u64 v[0:1], v2, v[0:1] offset:32 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 0 |
| ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] |
| ; GFX9-NEXT: s_endpgm |
| %gep = getelementptr i64, ptr addrspace(3) %ptr, i32 4 |
| %result = call i64 @llvm.amdgcn.atomic.inc.i64.p3(ptr addrspace(3) %gep, i64 42, i32 0, i32 0, i1 false) |
| store i64 %result, ptr addrspace(1) %out |
| ret void |
| } |
| |
| define amdgpu_kernel void @lds_atomic_inc_noret_i64(ptr addrspace(3) %ptr) nounwind { |
| ; CI-LABEL: lds_atomic_inc_noret_i64: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dword s0, s[4:5], 0x9 |
| ; CI-NEXT: v_mov_b32_e32 v0, 42 |
| ; CI-NEXT: v_mov_b32_e32 v1, 0 |
| ; CI-NEXT: s_mov_b32 m0, -1 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_mov_b32_e32 v2, s0 |
| ; CI-NEXT: ds_inc_u64 v2, v[0:1] |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: lds_atomic_inc_noret_i64: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dword s0, s[4:5], 0x24 |
| ; VI-NEXT: v_mov_b32_e32 v0, 42 |
| ; VI-NEXT: v_mov_b32_e32 v1, 0 |
| ; VI-NEXT: s_mov_b32 m0, -1 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v2, s0 |
| ; VI-NEXT: ds_inc_u64 v2, v[0:1] |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: lds_atomic_inc_noret_i64: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dword s0, s[4:5], 0x24 |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 42 |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 0 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v2, s0 |
| ; GFX9-NEXT: ds_inc_u64 v2, v[0:1] |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: s_endpgm |
| %result = call i64 @llvm.amdgcn.atomic.inc.i64.p3(ptr addrspace(3) %ptr, i64 42, i32 0, i32 0, i1 false) |
| ret void |
| } |
| |
| define amdgpu_kernel void @lds_atomic_inc_noret_i64_offset(ptr addrspace(3) %ptr) nounwind { |
| ; CI-LABEL: lds_atomic_inc_noret_i64_offset: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dword s0, s[4:5], 0x9 |
| ; CI-NEXT: v_mov_b32_e32 v0, 42 |
| ; CI-NEXT: v_mov_b32_e32 v1, 0 |
| ; CI-NEXT: s_mov_b32 m0, -1 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_mov_b32_e32 v2, s0 |
| ; CI-NEXT: ds_inc_u64 v2, v[0:1] offset:32 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: lds_atomic_inc_noret_i64_offset: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dword s0, s[4:5], 0x24 |
| ; VI-NEXT: v_mov_b32_e32 v0, 42 |
| ; VI-NEXT: v_mov_b32_e32 v1, 0 |
| ; VI-NEXT: s_mov_b32 m0, -1 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v2, s0 |
| ; VI-NEXT: ds_inc_u64 v2, v[0:1] offset:32 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: lds_atomic_inc_noret_i64_offset: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dword s0, s[4:5], 0x24 |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 42 |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 0 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v2, s0 |
| ; GFX9-NEXT: ds_inc_u64 v2, v[0:1] offset:32 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: s_endpgm |
| %gep = getelementptr i64, ptr addrspace(3) %ptr, i32 4 |
| %result = call i64 @llvm.amdgcn.atomic.inc.i64.p3(ptr addrspace(3) %gep, i64 42, i32 0, i32 0, i1 false) |
| ret void |
| } |
| |
| define amdgpu_kernel void @global_atomic_inc_ret_i64(ptr addrspace(1) %out, ptr addrspace(1) %ptr) #0 { |
| ; CI-LABEL: global_atomic_inc_ret_i64: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 |
| ; CI-NEXT: s_mov_b32 s7, 0xf000 |
| ; CI-NEXT: s_mov_b32 s6, -1 |
| ; CI-NEXT: v_mov_b32_e32 v0, 42 |
| ; CI-NEXT: s_mov_b32 s10, s6 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_mov_b32 s8, s2 |
| ; CI-NEXT: s_mov_b32 s9, s3 |
| ; CI-NEXT: v_mov_b32_e32 v1, 0 |
| ; CI-NEXT: s_mov_b32 s11, s7 |
| ; CI-NEXT: buffer_atomic_inc_x2 v[0:1], off, s[8:11], 0 glc |
| ; CI-NEXT: s_waitcnt vmcnt(0) |
| ; CI-NEXT: buffer_wbinvl1_vol |
| ; CI-NEXT: s_mov_b32 s4, s0 |
| ; CI-NEXT: s_mov_b32 s5, s1 |
| ; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: global_atomic_inc_ret_i64: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; VI-NEXT: s_mov_b32 s7, 0xf000 |
| ; VI-NEXT: s_mov_b32 s6, -1 |
| ; VI-NEXT: v_mov_b32_e32 v0, 42 |
| ; VI-NEXT: s_mov_b32 s10, s6 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_mov_b32 s8, s2 |
| ; VI-NEXT: s_mov_b32 s9, s3 |
| ; VI-NEXT: v_mov_b32_e32 v1, 0 |
| ; VI-NEXT: s_mov_b32 s11, s7 |
| ; VI-NEXT: buffer_atomic_inc_x2 v[0:1], off, s[8:11], 0 glc |
| ; VI-NEXT: s_waitcnt vmcnt(0) |
| ; VI-NEXT: buffer_wbinvl1_vol |
| ; VI-NEXT: s_mov_b32 s4, s0 |
| ; VI-NEXT: s_mov_b32 s5, s1 |
| ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 |
| ; VI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: global_atomic_inc_ret_i64: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 42 |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 0 |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 0 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: global_atomic_inc_x2 v[0:1], v2, v[0:1], s[2:3] glc |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) |
| ; GFX9-NEXT: buffer_wbinvl1_vol |
| ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] |
| ; GFX9-NEXT: s_endpgm |
| %result = call i64 @llvm.amdgcn.atomic.inc.i64.p1(ptr addrspace(1) %ptr, i64 42, i32 0, i32 0, i1 false) |
| store i64 %result, ptr addrspace(1) %out |
| ret void |
| } |
| |
| define amdgpu_kernel void @global_atomic_inc_ret_i64_offset(ptr addrspace(1) %out, ptr addrspace(1) %ptr) #0 { |
| ; CI-LABEL: global_atomic_inc_ret_i64_offset: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 |
| ; CI-NEXT: s_mov_b32 s7, 0xf000 |
| ; CI-NEXT: s_mov_b32 s6, -1 |
| ; CI-NEXT: v_mov_b32_e32 v0, 42 |
| ; CI-NEXT: s_mov_b32 s10, s6 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_mov_b32 s8, s2 |
| ; CI-NEXT: s_mov_b32 s9, s3 |
| ; CI-NEXT: v_mov_b32_e32 v1, 0 |
| ; CI-NEXT: s_mov_b32 s11, s7 |
| ; CI-NEXT: buffer_atomic_inc_x2 v[0:1], off, s[8:11], 0 offset:32 glc |
| ; CI-NEXT: s_waitcnt vmcnt(0) |
| ; CI-NEXT: buffer_wbinvl1_vol |
| ; CI-NEXT: s_mov_b32 s4, s0 |
| ; CI-NEXT: s_mov_b32 s5, s1 |
| ; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: global_atomic_inc_ret_i64_offset: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; VI-NEXT: s_mov_b32 s7, 0xf000 |
| ; VI-NEXT: s_mov_b32 s6, -1 |
| ; VI-NEXT: v_mov_b32_e32 v0, 42 |
| ; VI-NEXT: s_mov_b32 s10, s6 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_mov_b32 s8, s2 |
| ; VI-NEXT: s_mov_b32 s9, s3 |
| ; VI-NEXT: v_mov_b32_e32 v1, 0 |
| ; VI-NEXT: s_mov_b32 s11, s7 |
| ; VI-NEXT: buffer_atomic_inc_x2 v[0:1], off, s[8:11], 0 offset:32 glc |
| ; VI-NEXT: s_waitcnt vmcnt(0) |
| ; VI-NEXT: buffer_wbinvl1_vol |
| ; VI-NEXT: s_mov_b32 s4, s0 |
| ; VI-NEXT: s_mov_b32 s5, s1 |
| ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 |
| ; VI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: global_atomic_inc_ret_i64_offset: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 42 |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 0 |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 0 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: global_atomic_inc_x2 v[0:1], v2, v[0:1], s[2:3] offset:32 glc |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) |
| ; GFX9-NEXT: buffer_wbinvl1_vol |
| ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] |
| ; GFX9-NEXT: s_endpgm |
| %gep = getelementptr i64, ptr addrspace(1) %ptr, i32 4 |
| %result = call i64 @llvm.amdgcn.atomic.inc.i64.p1(ptr addrspace(1) %gep, i64 42, i32 0, i32 0, i1 false) |
| store i64 %result, ptr addrspace(1) %out |
| ret void |
| } |
| |
| define amdgpu_kernel void @global_atomic_inc_noret_i64(ptr addrspace(1) %ptr) nounwind { |
| ; CI-LABEL: global_atomic_inc_noret_i64: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 |
| ; CI-NEXT: v_mov_b32_e32 v0, 42 |
| ; CI-NEXT: s_mov_b32 s3, 0xf000 |
| ; CI-NEXT: v_mov_b32_e32 v1, 0 |
| ; CI-NEXT: s_mov_b32 s2, -1 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: buffer_atomic_inc_x2 v[0:1], off, s[0:3], 0 |
| ; CI-NEXT: s_waitcnt vmcnt(0) |
| ; CI-NEXT: buffer_wbinvl1_vol |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: global_atomic_inc_noret_i64: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; VI-NEXT: v_mov_b32_e32 v0, 42 |
| ; VI-NEXT: s_mov_b32 s3, 0xf000 |
| ; VI-NEXT: v_mov_b32_e32 v1, 0 |
| ; VI-NEXT: s_mov_b32 s2, -1 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: buffer_atomic_inc_x2 v[0:1], off, s[0:3], 0 |
| ; VI-NEXT: s_waitcnt vmcnt(0) |
| ; VI-NEXT: buffer_wbinvl1_vol |
| ; VI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: global_atomic_inc_noret_i64: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 42 |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 0 |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 0 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: global_atomic_inc_x2 v2, v[0:1], s[0:1] |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) |
| ; GFX9-NEXT: buffer_wbinvl1_vol |
| ; GFX9-NEXT: s_endpgm |
| %result = call i64 @llvm.amdgcn.atomic.inc.i64.p1(ptr addrspace(1) %ptr, i64 42, i32 0, i32 0, i1 false) |
| ret void |
| } |
| |
| define amdgpu_kernel void @global_atomic_inc_noret_i64_offset(ptr addrspace(1) %ptr) nounwind { |
| ; CI-LABEL: global_atomic_inc_noret_i64_offset: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 |
| ; CI-NEXT: v_mov_b32_e32 v0, 42 |
| ; CI-NEXT: s_mov_b32 s3, 0xf000 |
| ; CI-NEXT: v_mov_b32_e32 v1, 0 |
| ; CI-NEXT: s_mov_b32 s2, -1 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: buffer_atomic_inc_x2 v[0:1], off, s[0:3], 0 offset:32 |
| ; CI-NEXT: s_waitcnt vmcnt(0) |
| ; CI-NEXT: buffer_wbinvl1_vol |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: global_atomic_inc_noret_i64_offset: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; VI-NEXT: v_mov_b32_e32 v0, 42 |
| ; VI-NEXT: s_mov_b32 s3, 0xf000 |
| ; VI-NEXT: v_mov_b32_e32 v1, 0 |
| ; VI-NEXT: s_mov_b32 s2, -1 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: buffer_atomic_inc_x2 v[0:1], off, s[0:3], 0 offset:32 |
| ; VI-NEXT: s_waitcnt vmcnt(0) |
| ; VI-NEXT: buffer_wbinvl1_vol |
| ; VI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: global_atomic_inc_noret_i64_offset: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 42 |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 0 |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 0 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: global_atomic_inc_x2 v2, v[0:1], s[0:1] offset:32 |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) |
| ; GFX9-NEXT: buffer_wbinvl1_vol |
| ; GFX9-NEXT: s_endpgm |
| %gep = getelementptr i64, ptr addrspace(1) %ptr, i32 4 |
| %result = call i64 @llvm.amdgcn.atomic.inc.i64.p1(ptr addrspace(1) %gep, i64 42, i32 0, i32 0, i1 false) |
| ret void |
| } |
| |
| define amdgpu_kernel void @global_atomic_inc_ret_i64_offset_addr64(ptr addrspace(1) %out, ptr addrspace(1) %ptr) #0 { |
| ; CI-LABEL: global_atomic_inc_ret_i64_offset_addr64: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 |
| ; CI-NEXT: s_mov_b32 s7, 0xf000 |
| ; CI-NEXT: s_mov_b32 s6, 0 |
| ; CI-NEXT: v_mov_b32_e32 v2, 42 |
| ; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v0 |
| ; CI-NEXT: v_mov_b32_e32 v1, 0 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_mov_b64 s[8:9], s[2:3] |
| ; CI-NEXT: v_mov_b32_e32 v3, 0 |
| ; CI-NEXT: s_mov_b64 s[10:11], s[6:7] |
| ; CI-NEXT: buffer_atomic_inc_x2 v[2:3], v[0:1], s[8:11], 0 addr64 offset:40 glc |
| ; CI-NEXT: s_waitcnt vmcnt(0) |
| ; CI-NEXT: buffer_wbinvl1_vol |
| ; CI-NEXT: s_mov_b64 s[4:5], s[0:1] |
| ; CI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: global_atomic_inc_ret_i64_offset_addr64: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; VI-NEXT: v_lshlrev_b32_e32 v4, 3, v0 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v0, s3 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, s2, v4 |
| ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v0, vcc |
| ; VI-NEXT: v_mov_b32_e32 v0, 42 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v2 |
| ; VI-NEXT: v_mov_b32_e32 v1, 0 |
| ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc |
| ; VI-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] glc |
| ; VI-NEXT: s_waitcnt vmcnt(0) |
| ; VI-NEXT: buffer_wbinvl1_vol |
| ; VI-NEXT: v_mov_b32_e32 v3, s1 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4 |
| ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc |
| ; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] |
| ; VI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: global_atomic_inc_ret_i64_offset_addr64: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 42 |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 0 |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v3, 3, v0 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: global_atomic_inc_x2 v[0:1], v3, v[1:2], s[2:3] offset:40 glc |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) |
| ; GFX9-NEXT: buffer_wbinvl1_vol |
| ; GFX9-NEXT: global_store_dwordx2 v3, v[0:1], s[0:1] |
| ; GFX9-NEXT: s_endpgm |
| %id = call i32 @llvm.amdgcn.workitem.id.x() |
| %gep.tid = getelementptr i64, ptr addrspace(1) %ptr, i32 %id |
| %out.gep = getelementptr i64, ptr addrspace(1) %out, i32 %id |
| %gep = getelementptr i64, ptr addrspace(1) %gep.tid, i32 5 |
| %result = call i64 @llvm.amdgcn.atomic.inc.i64.p1(ptr addrspace(1) %gep, i64 42, i32 0, i32 0, i1 false) |
| store i64 %result, ptr addrspace(1) %out.gep |
| ret void |
| } |
| |
| define amdgpu_kernel void @global_atomic_inc_noret_i64_offset_addr64(ptr addrspace(1) %ptr) #0 { |
| ; CI-LABEL: global_atomic_inc_noret_i64_offset_addr64: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 |
| ; CI-NEXT: v_mov_b32_e32 v2, 42 |
| ; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v0 |
| ; CI-NEXT: v_mov_b32_e32 v1, 0 |
| ; CI-NEXT: s_mov_b32 s3, 0xf000 |
| ; CI-NEXT: v_mov_b32_e32 v3, 0 |
| ; CI-NEXT: s_mov_b32 s2, 0 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: buffer_atomic_inc_x2 v[2:3], v[0:1], s[0:3], 0 addr64 offset:40 |
| ; CI-NEXT: s_waitcnt vmcnt(0) |
| ; CI-NEXT: buffer_wbinvl1_vol |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: global_atomic_inc_noret_i64_offset_addr64: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v1, s1 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v0 |
| ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc |
| ; VI-NEXT: v_mov_b32_e32 v0, 42 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v2 |
| ; VI-NEXT: v_mov_b32_e32 v1, 0 |
| ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc |
| ; VI-NEXT: flat_atomic_inc_x2 v[2:3], v[0:1] |
| ; VI-NEXT: s_waitcnt vmcnt(0) |
| ; VI-NEXT: buffer_wbinvl1_vol |
| ; VI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: global_atomic_inc_noret_i64_offset_addr64: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 42 |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 0 |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 3, v0 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: global_atomic_inc_x2 v0, v[1:2], s[0:1] offset:40 |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) |
| ; GFX9-NEXT: buffer_wbinvl1_vol |
| ; GFX9-NEXT: s_endpgm |
| %id = call i32 @llvm.amdgcn.workitem.id.x() |
| %gep.tid = getelementptr i64, ptr addrspace(1) %ptr, i32 %id |
| %gep = getelementptr i64, ptr addrspace(1) %gep.tid, i32 5 |
| %result = call i64 @llvm.amdgcn.atomic.inc.i64.p1(ptr addrspace(1) %gep, i64 42, i32 0, i32 0, i1 false) |
| ret void |
| } |
| |
| define amdgpu_kernel void @flat_atomic_inc_ret_i32(ptr %out, ptr %ptr) #0 { |
| ; CI-LABEL: flat_atomic_inc_ret_i32: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 |
| ; CI-NEXT: v_mov_b32_e32 v2, 42 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_mov_b32_e32 v0, s2 |
| ; CI-NEXT: v_mov_b32_e32 v1, s3 |
| ; CI-NEXT: flat_atomic_inc v2, v[0:1], v2 glc |
| ; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; CI-NEXT: buffer_wbinvl1_vol |
| ; CI-NEXT: v_mov_b32_e32 v0, s0 |
| ; CI-NEXT: v_mov_b32_e32 v1, s1 |
| ; CI-NEXT: flat_store_dword v[0:1], v2 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: flat_atomic_inc_ret_i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; VI-NEXT: v_mov_b32_e32 v2, 42 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v0, s2 |
| ; VI-NEXT: v_mov_b32_e32 v1, s3 |
| ; VI-NEXT: flat_atomic_inc v2, v[0:1], v2 glc |
| ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; VI-NEXT: buffer_wbinvl1_vol |
| ; VI-NEXT: v_mov_b32_e32 v0, s0 |
| ; VI-NEXT: v_mov_b32_e32 v1, s1 |
| ; VI-NEXT: flat_store_dword v[0:1], v2 |
| ; VI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: flat_atomic_inc_ret_i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 42 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v0, s2 |
| ; GFX9-NEXT: v_mov_b32_e32 v1, s3 |
| ; GFX9-NEXT: flat_atomic_inc v2, v[0:1], v2 glc |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: buffer_wbinvl1_vol |
| ; GFX9-NEXT: v_mov_b32_e32 v0, s0 |
| ; GFX9-NEXT: v_mov_b32_e32 v1, s1 |
| ; GFX9-NEXT: flat_store_dword v[0:1], v2 |
| ; GFX9-NEXT: s_endpgm |
| %result = call i32 @llvm.amdgcn.atomic.inc.i32.p0(ptr %ptr, i32 42, i32 0, i32 0, i1 false) |
| store i32 %result, ptr %out |
| ret void |
| } |
| |
| define amdgpu_kernel void @flat_atomic_inc_ret_i32_offset(ptr %out, ptr %ptr) #0 { |
| ; CI-LABEL: flat_atomic_inc_ret_i32_offset: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 |
| ; CI-NEXT: v_mov_b32_e32 v2, 42 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_add_u32 s2, s2, 16 |
| ; CI-NEXT: s_addc_u32 s3, s3, 0 |
| ; CI-NEXT: v_mov_b32_e32 v0, s2 |
| ; CI-NEXT: v_mov_b32_e32 v1, s3 |
| ; CI-NEXT: flat_atomic_inc v2, v[0:1], v2 glc |
| ; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; CI-NEXT: buffer_wbinvl1_vol |
| ; CI-NEXT: v_mov_b32_e32 v0, s0 |
| ; CI-NEXT: v_mov_b32_e32 v1, s1 |
| ; CI-NEXT: flat_store_dword v[0:1], v2 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: flat_atomic_inc_ret_i32_offset: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; VI-NEXT: v_mov_b32_e32 v2, 42 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_add_u32 s2, s2, 16 |
| ; VI-NEXT: s_addc_u32 s3, s3, 0 |
| ; VI-NEXT: v_mov_b32_e32 v0, s2 |
| ; VI-NEXT: v_mov_b32_e32 v1, s3 |
| ; VI-NEXT: flat_atomic_inc v2, v[0:1], v2 glc |
| ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; VI-NEXT: buffer_wbinvl1_vol |
| ; VI-NEXT: v_mov_b32_e32 v0, s0 |
| ; VI-NEXT: v_mov_b32_e32 v1, s1 |
| ; VI-NEXT: flat_store_dword v[0:1], v2 |
| ; VI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: flat_atomic_inc_ret_i32_offset: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 42 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v0, s2 |
| ; GFX9-NEXT: v_mov_b32_e32 v1, s3 |
| ; GFX9-NEXT: flat_atomic_inc v2, v[0:1], v2 offset:16 glc |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: buffer_wbinvl1_vol |
| ; GFX9-NEXT: v_mov_b32_e32 v0, s0 |
| ; GFX9-NEXT: v_mov_b32_e32 v1, s1 |
| ; GFX9-NEXT: flat_store_dword v[0:1], v2 |
| ; GFX9-NEXT: s_endpgm |
| %gep = getelementptr i32, ptr %ptr, i32 4 |
| %result = call i32 @llvm.amdgcn.atomic.inc.i32.p0(ptr %gep, i32 42, i32 0, i32 0, i1 false) |
| store i32 %result, ptr %out |
| ret void |
| } |
| |
| define amdgpu_kernel void @flat_atomic_inc_noret_i32(ptr %ptr) nounwind { |
| ; CI-LABEL: flat_atomic_inc_noret_i32: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 |
| ; CI-NEXT: v_mov_b32_e32 v2, 42 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_mov_b32_e32 v0, s0 |
| ; CI-NEXT: v_mov_b32_e32 v1, s1 |
| ; CI-NEXT: flat_atomic_inc v[0:1], v2 |
| ; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; CI-NEXT: buffer_wbinvl1_vol |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: flat_atomic_inc_noret_i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; VI-NEXT: v_mov_b32_e32 v2, 42 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v0, s0 |
| ; VI-NEXT: v_mov_b32_e32 v1, s1 |
| ; VI-NEXT: flat_atomic_inc v[0:1], v2 |
| ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; VI-NEXT: buffer_wbinvl1_vol |
| ; VI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: flat_atomic_inc_noret_i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 42 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v0, s0 |
| ; GFX9-NEXT: v_mov_b32_e32 v1, s1 |
| ; GFX9-NEXT: flat_atomic_inc v[0:1], v2 |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: buffer_wbinvl1_vol |
| ; GFX9-NEXT: s_endpgm |
| %result = call i32 @llvm.amdgcn.atomic.inc.i32.p0(ptr %ptr, i32 42, i32 0, i32 0, i1 false) |
| ret void |
| } |
| |
| define amdgpu_kernel void @flat_atomic_inc_noret_i32_offset(ptr %ptr) nounwind { |
| ; CI-LABEL: flat_atomic_inc_noret_i32_offset: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 |
| ; CI-NEXT: v_mov_b32_e32 v2, 42 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_add_u32 s0, s0, 16 |
| ; CI-NEXT: s_addc_u32 s1, s1, 0 |
| ; CI-NEXT: v_mov_b32_e32 v0, s0 |
| ; CI-NEXT: v_mov_b32_e32 v1, s1 |
| ; CI-NEXT: flat_atomic_inc v[0:1], v2 |
| ; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; CI-NEXT: buffer_wbinvl1_vol |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: flat_atomic_inc_noret_i32_offset: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; VI-NEXT: v_mov_b32_e32 v2, 42 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_add_u32 s0, s0, 16 |
| ; VI-NEXT: s_addc_u32 s1, s1, 0 |
| ; VI-NEXT: v_mov_b32_e32 v0, s0 |
| ; VI-NEXT: v_mov_b32_e32 v1, s1 |
| ; VI-NEXT: flat_atomic_inc v[0:1], v2 |
| ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; VI-NEXT: buffer_wbinvl1_vol |
| ; VI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: flat_atomic_inc_noret_i32_offset: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 42 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v0, s0 |
| ; GFX9-NEXT: v_mov_b32_e32 v1, s1 |
| ; GFX9-NEXT: flat_atomic_inc v[0:1], v2 offset:16 |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: buffer_wbinvl1_vol |
| ; GFX9-NEXT: s_endpgm |
| %gep = getelementptr i32, ptr %ptr, i32 4 |
| %result = call i32 @llvm.amdgcn.atomic.inc.i32.p0(ptr %gep, i32 42, i32 0, i32 0, i1 false) |
| ret void |
| } |
| |
| define amdgpu_kernel void @flat_atomic_inc_ret_i32_offset_addr64(ptr %out, ptr %ptr) #0 { |
| ; CI-LABEL: flat_atomic_inc_ret_i32_offset_addr64: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 |
| ; CI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_mov_b32_e32 v0, s3 |
| ; CI-NEXT: v_add_i32_e32 v1, vcc, s2, v2 |
| ; CI-NEXT: v_addc_u32_e32 v3, vcc, 0, v0, vcc |
| ; CI-NEXT: v_add_i32_e32 v0, vcc, 20, v1 |
| ; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc |
| ; CI-NEXT: v_mov_b32_e32 v3, 42 |
| ; CI-NEXT: flat_atomic_inc v3, v[0:1], v3 glc |
| ; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; CI-NEXT: buffer_wbinvl1_vol |
| ; CI-NEXT: v_mov_b32_e32 v1, s1 |
| ; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v2 |
| ; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc |
| ; CI-NEXT: flat_store_dword v[0:1], v3 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: flat_atomic_inc_ret_i32_offset_addr64: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v0, s3 |
| ; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v2 |
| ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v0, vcc |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 20, v1 |
| ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc |
| ; VI-NEXT: v_mov_b32_e32 v3, 42 |
| ; VI-NEXT: flat_atomic_inc v3, v[0:1], v3 glc |
| ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; VI-NEXT: buffer_wbinvl1_vol |
| ; VI-NEXT: v_mov_b32_e32 v1, s1 |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 |
| ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc |
| ; VI-NEXT: flat_store_dword v[0:1], v3 |
| ; VI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: flat_atomic_inc_ret_i32_offset_addr64: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 |
| ; GFX9-NEXT: v_mov_b32_e32 v3, 42 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v1, s3 |
| ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc |
| ; GFX9-NEXT: flat_atomic_inc v3, v[0:1], v3 offset:20 glc |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: buffer_wbinvl1_vol |
| ; GFX9-NEXT: v_mov_b32_e32 v1, s1 |
| ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc |
| ; GFX9-NEXT: flat_store_dword v[0:1], v3 |
| ; GFX9-NEXT: s_endpgm |
| %id = call i32 @llvm.amdgcn.workitem.id.x() |
| %gep.tid = getelementptr i32, ptr %ptr, i32 %id |
| %out.gep = getelementptr i32, ptr %out, i32 %id |
| %gep = getelementptr i32, ptr %gep.tid, i32 5 |
| %result = call i32 @llvm.amdgcn.atomic.inc.i32.p0(ptr %gep, i32 42, i32 0, i32 0, i1 false) |
| store i32 %result, ptr %out.gep |
| ret void |
| } |
| |
| define amdgpu_kernel void @flat_atomic_inc_noret_i32_offset_addr64(ptr %ptr) #0 { |
| ; CI-LABEL: flat_atomic_inc_noret_i32_offset_addr64: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 |
| ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 |
| ; CI-NEXT: v_mov_b32_e32 v2, 42 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_mov_b32_e32 v1, s1 |
| ; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v0 |
| ; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc |
| ; CI-NEXT: v_add_i32_e32 v0, vcc, 20, v0 |
| ; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc |
| ; CI-NEXT: flat_atomic_inc v[0:1], v2 |
| ; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; CI-NEXT: buffer_wbinvl1_vol |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: flat_atomic_inc_noret_i32_offset_addr64: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 |
| ; VI-NEXT: v_mov_b32_e32 v2, 42 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v1, s1 |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0 |
| ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 20, v0 |
| ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc |
| ; VI-NEXT: flat_atomic_inc v[0:1], v2 |
| ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; VI-NEXT: buffer_wbinvl1_vol |
| ; VI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: flat_atomic_inc_noret_i32_offset_addr64: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 42 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v1, s1 |
| ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc |
| ; GFX9-NEXT: flat_atomic_inc v[0:1], v2 offset:20 |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: buffer_wbinvl1_vol |
| ; GFX9-NEXT: s_endpgm |
| %id = call i32 @llvm.amdgcn.workitem.id.x() |
| %gep.tid = getelementptr i32, ptr %ptr, i32 %id |
| %gep = getelementptr i32, ptr %gep.tid, i32 5 |
| %result = call i32 @llvm.amdgcn.atomic.inc.i32.p0(ptr %gep, i32 42, i32 0, i32 0, i1 false) |
| ret void |
| } |
| |
| @lds1 = addrspace(3) global [512 x i64] poison, align 8 |
| |
| define amdgpu_kernel void @atomic_inc_shl_base_lds_0_i64(ptr addrspace(1) %out, ptr addrspace(1) %add_use) #0 { |
| ; CI-LABEL: atomic_inc_shl_base_lds_0_i64: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 |
| ; CI-NEXT: v_mov_b32_e32 v1, 9 |
| ; CI-NEXT: v_lshlrev_b32_e32 v3, 3, v0 |
| ; CI-NEXT: v_mov_b32_e32 v2, 0 |
| ; CI-NEXT: s_mov_b32 m0, -1 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: ds_inc_rtn_u64 v[1:2], v3, v[1:2] offset:16 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_mov_b32 s7, 0xf000 |
| ; CI-NEXT: s_mov_b32 s6, -1 |
| ; CI-NEXT: s_mov_b32 s4, s0 |
| ; CI-NEXT: s_mov_b32 s5, s1 |
| ; CI-NEXT: s_mov_b32 s0, s2 |
| ; CI-NEXT: s_mov_b32 s1, s3 |
| ; CI-NEXT: s_mov_b32 s2, s6 |
| ; CI-NEXT: s_mov_b32 s3, s7 |
| ; CI-NEXT: v_add_i32_e32 v0, vcc, 2, v0 |
| ; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0 |
| ; CI-NEXT: buffer_store_dwordx2 v[1:2], off, s[4:7], 0 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: atomic_inc_shl_base_lds_0_i64: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; VI-NEXT: v_mov_b32_e32 v1, 9 |
| ; VI-NEXT: v_lshlrev_b32_e32 v3, 3, v0 |
| ; VI-NEXT: v_mov_b32_e32 v2, 0 |
| ; VI-NEXT: s_mov_b32 m0, -1 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: ds_inc_rtn_u64 v[1:2], v3, v[1:2] offset:16 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_mov_b32 s7, 0xf000 |
| ; VI-NEXT: s_mov_b32 s6, -1 |
| ; VI-NEXT: s_mov_b32 s4, s0 |
| ; VI-NEXT: s_mov_b32 s5, s1 |
| ; VI-NEXT: s_mov_b32 s0, s2 |
| ; VI-NEXT: s_mov_b32 s1, s3 |
| ; VI-NEXT: s_mov_b32 s2, s6 |
| ; VI-NEXT: s_mov_b32 s3, s7 |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0 |
| ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 |
| ; VI-NEXT: buffer_store_dwordx2 v[1:2], off, s[4:7], 0 |
| ; VI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: atomic_inc_shl_base_lds_0_i64: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 9 |
| ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 0 |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v3, 3, v0 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: ds_inc_rtn_u64 v[1:2], v3, v[1:2] offset:16 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v3, 0 |
| ; GFX9-NEXT: v_add_u32_e32 v0, 2, v0 |
| ; GFX9-NEXT: global_store_dword v3, v0, s[2:3] |
| ; GFX9-NEXT: global_store_dwordx2 v3, v[1:2], s[0:1] |
| ; GFX9-NEXT: s_endpgm |
| %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 |
| %idx.0 = add nsw i32 %tid.x, 2 |
| %arrayidx0 = getelementptr inbounds [512 x i64], ptr addrspace(3) @lds1, i32 0, i32 %idx.0 |
| %val0 = call i64 @llvm.amdgcn.atomic.inc.i64.p3(ptr addrspace(3) %arrayidx0, i64 9, i32 0, i32 0, i1 false) |
| store i32 %idx.0, ptr addrspace(1) %add_use |
| store i64 %val0, ptr addrspace(1) %out |
| ret void |
| } |
| |
| define amdgpu_kernel void @flat_atomic_inc_ret_i64(ptr %out, ptr %ptr) #0 { |
| ; CI-LABEL: flat_atomic_inc_ret_i64: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 |
| ; CI-NEXT: v_mov_b32_e32 v0, 42 |
| ; CI-NEXT: v_mov_b32_e32 v1, 0 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_mov_b32_e32 v2, s2 |
| ; CI-NEXT: v_mov_b32_e32 v3, s3 |
| ; CI-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] glc |
| ; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; CI-NEXT: buffer_wbinvl1_vol |
| ; CI-NEXT: v_mov_b32_e32 v2, s0 |
| ; CI-NEXT: v_mov_b32_e32 v3, s1 |
| ; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: flat_atomic_inc_ret_i64: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; VI-NEXT: v_mov_b32_e32 v0, 42 |
| ; VI-NEXT: v_mov_b32_e32 v1, 0 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v2, s2 |
| ; VI-NEXT: v_mov_b32_e32 v3, s3 |
| ; VI-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] glc |
| ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; VI-NEXT: buffer_wbinvl1_vol |
| ; VI-NEXT: v_mov_b32_e32 v2, s0 |
| ; VI-NEXT: v_mov_b32_e32 v3, s1 |
| ; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] |
| ; VI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: flat_atomic_inc_ret_i64: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 42 |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 0 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v2, s2 |
| ; GFX9-NEXT: v_mov_b32_e32 v3, s3 |
| ; GFX9-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] glc |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: buffer_wbinvl1_vol |
| ; GFX9-NEXT: v_mov_b32_e32 v2, s0 |
| ; GFX9-NEXT: v_mov_b32_e32 v3, s1 |
| ; GFX9-NEXT: flat_store_dwordx2 v[2:3], v[0:1] |
| ; GFX9-NEXT: s_endpgm |
| %result = call i64 @llvm.amdgcn.atomic.inc.i64.p0(ptr %ptr, i64 42, i32 0, i32 0, i1 false) |
| store i64 %result, ptr %out |
| ret void |
| } |
| |
| define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset(ptr %out, ptr %ptr) #0 { |
| ; CI-LABEL: flat_atomic_inc_ret_i64_offset: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 |
| ; CI-NEXT: v_mov_b32_e32 v0, 42 |
| ; CI-NEXT: v_mov_b32_e32 v1, 0 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_add_u32 s2, s2, 32 |
| ; CI-NEXT: s_addc_u32 s3, s3, 0 |
| ; CI-NEXT: v_mov_b32_e32 v2, s2 |
| ; CI-NEXT: v_mov_b32_e32 v3, s3 |
| ; CI-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] glc |
| ; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; CI-NEXT: buffer_wbinvl1_vol |
| ; CI-NEXT: v_mov_b32_e32 v2, s0 |
| ; CI-NEXT: v_mov_b32_e32 v3, s1 |
| ; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: flat_atomic_inc_ret_i64_offset: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; VI-NEXT: v_mov_b32_e32 v0, 42 |
| ; VI-NEXT: v_mov_b32_e32 v1, 0 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_add_u32 s2, s2, 32 |
| ; VI-NEXT: s_addc_u32 s3, s3, 0 |
| ; VI-NEXT: v_mov_b32_e32 v2, s2 |
| ; VI-NEXT: v_mov_b32_e32 v3, s3 |
| ; VI-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] glc |
| ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; VI-NEXT: buffer_wbinvl1_vol |
| ; VI-NEXT: v_mov_b32_e32 v2, s0 |
| ; VI-NEXT: v_mov_b32_e32 v3, s1 |
| ; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] |
| ; VI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: flat_atomic_inc_ret_i64_offset: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 42 |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 0 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v2, s2 |
| ; GFX9-NEXT: v_mov_b32_e32 v3, s3 |
| ; GFX9-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] offset:32 glc |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: buffer_wbinvl1_vol |
| ; GFX9-NEXT: v_mov_b32_e32 v2, s0 |
| ; GFX9-NEXT: v_mov_b32_e32 v3, s1 |
| ; GFX9-NEXT: flat_store_dwordx2 v[2:3], v[0:1] |
| ; GFX9-NEXT: s_endpgm |
| %gep = getelementptr i64, ptr %ptr, i32 4 |
| %result = call i64 @llvm.amdgcn.atomic.inc.i64.p0(ptr %gep, i64 42, i32 0, i32 0, i1 false) |
| store i64 %result, ptr %out |
| ret void |
| } |
| |
| define amdgpu_kernel void @flat_atomic_inc_noret_i64(ptr %ptr) nounwind { |
| ; CI-LABEL: flat_atomic_inc_noret_i64: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 |
| ; CI-NEXT: v_mov_b32_e32 v0, 42 |
| ; CI-NEXT: v_mov_b32_e32 v1, 0 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_mov_b32_e32 v3, s1 |
| ; CI-NEXT: v_mov_b32_e32 v2, s0 |
| ; CI-NEXT: flat_atomic_inc_x2 v[2:3], v[0:1] |
| ; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; CI-NEXT: buffer_wbinvl1_vol |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: flat_atomic_inc_noret_i64: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; VI-NEXT: v_mov_b32_e32 v0, 42 |
| ; VI-NEXT: v_mov_b32_e32 v1, 0 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v3, s1 |
| ; VI-NEXT: v_mov_b32_e32 v2, s0 |
| ; VI-NEXT: flat_atomic_inc_x2 v[2:3], v[0:1] |
| ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; VI-NEXT: buffer_wbinvl1_vol |
| ; VI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: flat_atomic_inc_noret_i64: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 42 |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 0 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v3, s1 |
| ; GFX9-NEXT: v_mov_b32_e32 v2, s0 |
| ; GFX9-NEXT: flat_atomic_inc_x2 v[2:3], v[0:1] |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: buffer_wbinvl1_vol |
| ; GFX9-NEXT: s_endpgm |
| %result = call i64 @llvm.amdgcn.atomic.inc.i64.p0(ptr %ptr, i64 42, i32 0, i32 0, i1 false) |
| ret void |
| } |
| |
| define amdgpu_kernel void @flat_atomic_inc_noret_i64_offset(ptr %ptr) nounwind { |
| ; CI-LABEL: flat_atomic_inc_noret_i64_offset: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 |
| ; CI-NEXT: v_mov_b32_e32 v0, 42 |
| ; CI-NEXT: v_mov_b32_e32 v1, 0 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_add_u32 s0, s0, 32 |
| ; CI-NEXT: s_addc_u32 s1, s1, 0 |
| ; CI-NEXT: v_mov_b32_e32 v3, s1 |
| ; CI-NEXT: v_mov_b32_e32 v2, s0 |
| ; CI-NEXT: flat_atomic_inc_x2 v[2:3], v[0:1] |
| ; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; CI-NEXT: buffer_wbinvl1_vol |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: flat_atomic_inc_noret_i64_offset: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; VI-NEXT: v_mov_b32_e32 v0, 42 |
| ; VI-NEXT: v_mov_b32_e32 v1, 0 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_add_u32 s0, s0, 32 |
| ; VI-NEXT: s_addc_u32 s1, s1, 0 |
| ; VI-NEXT: v_mov_b32_e32 v3, s1 |
| ; VI-NEXT: v_mov_b32_e32 v2, s0 |
| ; VI-NEXT: flat_atomic_inc_x2 v[2:3], v[0:1] |
| ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; VI-NEXT: buffer_wbinvl1_vol |
| ; VI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: flat_atomic_inc_noret_i64_offset: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 42 |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 0 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v3, s1 |
| ; GFX9-NEXT: v_mov_b32_e32 v2, s0 |
| ; GFX9-NEXT: flat_atomic_inc_x2 v[2:3], v[0:1] offset:32 |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: buffer_wbinvl1_vol |
| ; GFX9-NEXT: s_endpgm |
| %gep = getelementptr i64, ptr %ptr, i32 4 |
| %result = call i64 @llvm.amdgcn.atomic.inc.i64.p0(ptr %gep, i64 42, i32 0, i32 0, i1 false) |
| ret void |
| } |
| |
| define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset_addr64(ptr %out, ptr %ptr) #0 { |
| ; CI-LABEL: flat_atomic_inc_ret_i64_offset_addr64: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 |
| ; CI-NEXT: v_lshlrev_b32_e32 v4, 3, v0 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_mov_b32_e32 v0, s3 |
| ; CI-NEXT: v_add_i32_e32 v2, vcc, s2, v4 |
| ; CI-NEXT: v_addc_u32_e32 v3, vcc, 0, v0, vcc |
| ; CI-NEXT: v_mov_b32_e32 v0, 42 |
| ; CI-NEXT: v_add_i32_e32 v2, vcc, 40, v2 |
| ; CI-NEXT: v_mov_b32_e32 v1, 0 |
| ; CI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc |
| ; CI-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] glc |
| ; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; CI-NEXT: buffer_wbinvl1_vol |
| ; CI-NEXT: v_mov_b32_e32 v3, s1 |
| ; CI-NEXT: v_add_i32_e32 v2, vcc, s0, v4 |
| ; CI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc |
| ; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: flat_atomic_inc_ret_i64_offset_addr64: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; VI-NEXT: v_lshlrev_b32_e32 v4, 3, v0 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v0, s3 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, s2, v4 |
| ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v0, vcc |
| ; VI-NEXT: v_mov_b32_e32 v0, 42 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v2 |
| ; VI-NEXT: v_mov_b32_e32 v1, 0 |
| ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc |
| ; VI-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] glc |
| ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; VI-NEXT: buffer_wbinvl1_vol |
| ; VI-NEXT: v_mov_b32_e32 v3, s1 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4 |
| ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc |
| ; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] |
| ; VI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: flat_atomic_inc_ret_i64_offset_addr64: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v5, 3, v0 |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 42 |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 0 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v0, s3 |
| ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, s2, v5 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v0, vcc |
| ; GFX9-NEXT: flat_atomic_inc_x2 v[0:1], v[3:4], v[1:2] offset:40 glc |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: buffer_wbinvl1_vol |
| ; GFX9-NEXT: v_mov_b32_e32 v3, s1 |
| ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v5 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc |
| ; GFX9-NEXT: flat_store_dwordx2 v[2:3], v[0:1] |
| ; GFX9-NEXT: s_endpgm |
| %id = call i32 @llvm.amdgcn.workitem.id.x() |
| %gep.tid = getelementptr i64, ptr %ptr, i32 %id |
| %out.gep = getelementptr i64, ptr %out, i32 %id |
| %gep = getelementptr i64, ptr %gep.tid, i32 5 |
| %result = call i64 @llvm.amdgcn.atomic.inc.i64.p0(ptr %gep, i64 42, i32 0, i32 0, i1 false) |
| store i64 %result, ptr %out.gep |
| ret void |
| } |
| |
| define amdgpu_kernel void @flat_atomic_inc_noret_i64_offset_addr64(ptr %ptr) #0 { |
| ; CI-LABEL: flat_atomic_inc_noret_i64_offset_addr64: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 |
| ; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v0 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_mov_b32_e32 v1, s1 |
| ; CI-NEXT: v_add_i32_e32 v2, vcc, s0, v0 |
| ; CI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc |
| ; CI-NEXT: v_mov_b32_e32 v0, 42 |
| ; CI-NEXT: v_add_i32_e32 v2, vcc, 40, v2 |
| ; CI-NEXT: v_mov_b32_e32 v1, 0 |
| ; CI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc |
| ; CI-NEXT: flat_atomic_inc_x2 v[2:3], v[0:1] |
| ; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; CI-NEXT: buffer_wbinvl1_vol |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: flat_atomic_inc_noret_i64_offset_addr64: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v1, s1 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v0 |
| ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc |
| ; VI-NEXT: v_mov_b32_e32 v0, 42 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v2 |
| ; VI-NEXT: v_mov_b32_e32 v1, 0 |
| ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc |
| ; VI-NEXT: flat_atomic_inc_x2 v[2:3], v[0:1] |
| ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; VI-NEXT: buffer_wbinvl1_vol |
| ; VI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: flat_atomic_inc_noret_i64_offset_addr64: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 3, v0 |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 42 |
| ; GFX9-NEXT: v_mov_b32_e32 v2, 0 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v4, s1 |
| ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, s0, v0 |
| ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc |
| ; GFX9-NEXT: flat_atomic_inc_x2 v[3:4], v[1:2] offset:40 |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: buffer_wbinvl1_vol |
| ; GFX9-NEXT: s_endpgm |
| %id = call i32 @llvm.amdgcn.workitem.id.x() |
| %gep.tid = getelementptr i64, ptr %ptr, i32 %id |
| %gep = getelementptr i64, ptr %gep.tid, i32 5 |
| %result = call i64 @llvm.amdgcn.atomic.inc.i64.p0(ptr %gep, i64 42, i32 0, i32 0, i1 false) |
| ret void |
| } |
| |
| define amdgpu_kernel void @nocse_lds_atomic_inc_ret_i32(ptr addrspace(1) %out0, ptr addrspace(1) %out1, ptr addrspace(3) %ptr) #0 { |
| ; CI-LABEL: nocse_lds_atomic_inc_ret_i32: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 |
| ; CI-NEXT: s_load_dword s8, s[4:5], 0xd |
| ; CI-NEXT: v_mov_b32_e32 v0, 42 |
| ; CI-NEXT: s_mov_b32 m0, -1 |
| ; CI-NEXT: s_mov_b32 s7, 0xf000 |
| ; CI-NEXT: s_mov_b32 s6, -1 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_mov_b32_e32 v1, s8 |
| ; CI-NEXT: ds_inc_rtn_u32 v2, v1, v0 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: ds_inc_rtn_u32 v0, v1, v0 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_mov_b32 s4, s0 |
| ; CI-NEXT: s_mov_b32 s5, s1 |
| ; CI-NEXT: s_mov_b32 s0, s2 |
| ; CI-NEXT: s_mov_b32 s1, s3 |
| ; CI-NEXT: s_mov_b32 s2, s6 |
| ; CI-NEXT: s_mov_b32 s3, s7 |
| ; CI-NEXT: buffer_store_dword v2, off, s[4:7], 0 |
| ; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: nocse_lds_atomic_inc_ret_i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; VI-NEXT: s_load_dword s8, s[4:5], 0x34 |
| ; VI-NEXT: v_mov_b32_e32 v0, 42 |
| ; VI-NEXT: s_mov_b32 m0, -1 |
| ; VI-NEXT: s_mov_b32 s7, 0xf000 |
| ; VI-NEXT: s_mov_b32 s6, -1 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v1, s8 |
| ; VI-NEXT: ds_inc_rtn_u32 v2, v1, v0 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: ds_inc_rtn_u32 v0, v1, v0 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_mov_b32 s4, s0 |
| ; VI-NEXT: s_mov_b32 s5, s1 |
| ; VI-NEXT: s_mov_b32 s0, s2 |
| ; VI-NEXT: s_mov_b32 s1, s3 |
| ; VI-NEXT: s_mov_b32 s2, s6 |
| ; VI-NEXT: s_mov_b32 s3, s7 |
| ; VI-NEXT: buffer_store_dword v2, off, s[4:7], 0 |
| ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 |
| ; VI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: nocse_lds_atomic_inc_ret_i32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dword s6, s[4:5], 0x34 |
| ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 42 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v1, s6 |
| ; GFX9-NEXT: ds_inc_rtn_u32 v2, v1, v0 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: ds_inc_rtn_u32 v0, v1, v0 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 0 |
| ; GFX9-NEXT: global_store_dword v1, v2, s[0:1] |
| ; GFX9-NEXT: global_store_dword v1, v0, s[2:3] |
| ; GFX9-NEXT: s_endpgm |
| %result0 = call i32 @llvm.amdgcn.atomic.inc.i32.p3(ptr addrspace(3) %ptr, i32 42, i32 0, i32 0, i1 false) |
| %result1 = call i32 @llvm.amdgcn.atomic.inc.i32.p3(ptr addrspace(3) %ptr, i32 42, i32 0, i32 0, i1 false) |
| |
| store i32 %result0, ptr addrspace(1) %out0 |
| store i32 %result1, ptr addrspace(1) %out1 |
| ret void |
| } |
| |
| attributes #0 = { nounwind } |
| attributes #1 = { nounwind readnone } |
| attributes #2 = { nounwind argmemonly } |
