llvm/test/CodeGen/RISCV/opt-w-instrs.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
# RUN: llc -mtriple=riscv64 -mattr='+d,+zfa,+v,+xtheadmempair' -verify-machineinstrs -run-pass=riscv-opt-w-instrs %s -o - | FileCheck %s

---
name:            fcvtmod_w_d
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10

    ; CHECK-LABEL: name: fcvtmod_w_d
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $x10
    ; CHECK-NEXT: [[FCVTMOD_W_D:%[0-9]+]]:gpr = nofpexcept FCVTMOD_W_D [[COPY]], 1
    ; CHECK-NEXT: $x10 = COPY [[FCVTMOD_W_D]]
    ; CHECK-NEXT: PseudoRET
    %0:fpr64 = COPY $x10

    %1:gpr = nofpexcept FCVTMOD_W_D %0, 1
    %2:gpr = ADDIW %1, 0
    $x10 = COPY %2
    PseudoRET
...

---
name:            physreg
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11

    ; CHECK-LABEL: name: physreg
    ; CHECK: liveins: $x10, $x11
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[COPY]], 0
    ; CHECK-NEXT: $x10 = COPY [[ADDIW]]
    ; CHECK-NEXT: PseudoRET
    %0:gpr = COPY $x10
    %1:gpr = ADDIW %0, 0
    $x10 = COPY %1
    PseudoRET
...
---
 name:            vfirst
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
     liveins: $x10, $v8

    ; CHECK-LABEL: name: vfirst
    ; CHECK: liveins: $x10, $v8
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x10
    ; CHECK-NEXT: [[PseudoVFIRST_M_B1_:%[0-9]+]]:gpr = PseudoVFIRST_M_B1 [[COPY]], [[COPY1]], 0 /* e8 */
    ; CHECK-NEXT: $x11 = COPY [[PseudoVFIRST_M_B1_]]
    ; CHECK-NEXT: PseudoRET
     %0:vr = COPY $v8
     %1:gprnox0 = COPY $x10

     %2:gpr = PseudoVFIRST_M_B1 %0:vr, %1:gprnox0, 0
     %3:gpr = ADDIW %2, 0
     $x11 = COPY %3
     PseudoRET
...
---
 name:            vcpop
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
     liveins: $x10, $v8

    ; CHECK-LABEL: name: vcpop
    ; CHECK: liveins: $x10, $v8
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x10
    ; CHECK-NEXT: [[PseudoVCPOP_M_B1_:%[0-9]+]]:gpr = PseudoVCPOP_M_B1 [[COPY]], [[COPY1]], 0 /* e8 */
    ; CHECK-NEXT: $x11 = COPY [[PseudoVCPOP_M_B1_]]
    ; CHECK-NEXT: PseudoRET
     %0:vr = COPY $v8
     %1:gprnox0 = COPY $x10

     %2:gpr = PseudoVCPOP_M_B1 %0:vr, %1:gprnox0, 0
     %3:gpr = ADDIW %2, 0
     $x11 = COPY %3
     PseudoRET
...
---
 name:            th_lwd
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
     liveins: $x10
    ; CHECK-LABEL: name: th_lwd
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; CHECK-NEXT: early-clobber %1:gpr, early-clobber %2:gpr = TH_LWD [[COPY]], 2, 3
    ; CHECK-NEXT: $x10 = COPY %1
    ; CHECK-NEXT: $x11 = COPY %2
    ; CHECK-NEXT: PseudoRET
     %0:gpr = COPY $x10
     early-clobber %1:gpr, early-clobber %2:gpr = TH_LWD %0, 2, 3
     %3:gpr = ADDIW %1, 0
     %4:gpr = ADDIW %2, 0
     $x10 = COPY %3
     $x11 = COPY %4
     PseudoRET
...