$ svn merge -c 91720 https://bwilson@llvm.org/svn/llvm-project/llvm-gcc-4.2/trunk
--- Merging r91720 into '.':
U gcc/fold-const.c
A gcc/testsuite/gcc.dg/6951876.c
A gcc/testsuite/gcc.dg/7105615.c
U gcc/testsuite/ChangeLog.apple
U gcc/local-alloc.c
U gcc/ChangeLog.apple
U gcc/version.c
U gcc/config/arm/t-darwin
U gcc/config/arm/arm1136jfs.md
U gcc/config/arm/arm.c
U gcc/config/arm/cortex-a8.md
U gcc/config/arm/sync.md
U build_gcc
$ svn merge -c 91721 https://bwilson@llvm.org/svn/llvm-project/llvm-gcc-4.2/trunk
--- Merging r91721 into '.':
U gcc/doc/invoke.texi
U gcc/gcc.c
$ svn merge -c 91723 https://bwilson@llvm.org/svn/llvm-project/llvm-gcc-4.2/trunk
--- Merging r91723 into '.':
U gcc/config/arm/linux-eabi.h
$ svn merge -c 91726 https://bwilson@llvm.org/svn/llvm-project/llvm-gcc-4.2/trunk
--- Merging r91726 into '.':
U gcc/config.gcc
U gcc/config/t-darwin
U gcc/config/darwin-c.c
$ svn merge -c 91728 https://bwilson@llvm.org/svn/llvm-project/llvm-gcc-4.2/trunk
--- Merging r91728 into '.':
U gcc/cp/parser.c
U gcc/tree-eh.c
llvm-svn: 91760
diff --git a/llvm-gcc-4.2/build_gcc b/llvm-gcc-4.2/build_gcc
index 55faf98..e4d08e2 100755
--- a/llvm-gcc-4.2/build_gcc
+++ b/llvm-gcc-4.2/build_gcc
@@ -123,14 +123,19 @@
ARM_LIBSTDCXX_VERSION=4.2.1
ARM_CONFIGFLAGS="--with-gxx-include-dir=/usr/include/c++/$ARM_LIBSTDCXX_VERSION"
-# If the build target is iPhone, use the iPhone SDK as the build sysroot
-# and use the tools from the iPhone platform directory. These paths have to
-# be hardcoded, at least for now, because the build system does not
-# consistently identify separate host and target SDKROOTS. (The buildit
-# script currently sets SDKROOT to the target iPhone SDK, but XBS sets it
-# to the default host SDK "/".)
-if [ "x$RC_TARGET_CONFIG" = "xiPhone" ]; then
+if [ -n "$ARM_SDK" ]; then
+ ARM_PLATFORM=`xcodebuild -version -sdk $ARM_SDK PlatformPath`
+ ARM_SYSROOT=`xcodebuild -version -sdk $ARM_SDK Path`
+ ARM_TOOLROOT=$ARM_PLATFORM/Developer
+
+elif [ "x$RC_TARGET_CONFIG" = "xiPhone" ]; then
+
+ # If the build target is iPhone, use the iPhone SDK as the build sysroot
+ # and use the tools from the iPhone platform directory. FIXME: This is a
+ # temporary fallback for builds where ARM_SDK is not set. It can be removed,
+ # along with the following bootstrap SDK fallback, when ARM_SDK is set for
+ # all builds.
ARM_PLATFORM=/Developer/Platforms/iPhoneOS.platform
ARM_IPHONE_SDK=iPhoneOS${IPHONEOS_DEPLOYMENT_TARGET}.Internal.sdk
diff --git a/llvm-gcc-4.2/gcc/ChangeLog.apple b/llvm-gcc-4.2/gcc/ChangeLog.apple
index c55f128..5e74a8e 100644
--- a/llvm-gcc-4.2/gcc/ChangeLog.apple
+++ b/llvm-gcc-4.2/gcc/ChangeLog.apple
@@ -1,3 +1,52 @@
+2009-12-04 Jim Grosbach <grosbach@apple.com>
+
+ Radar 6930582
+ * config/arm/arm1136jfs.md: Adjust load latencies up by one.
+ * config/arm/cortex-a8.md: Adjust load latencies up by one.
+
+2009-12-04 Jim Grosbach <grosbach@apple.com>
+
+ Radar 7393136
+ * config/arm/arm.c (arm_split_compare_and_swap): Just use a data
+ memory barrier after the strex. dsb is overkill.
+ * config/arm/sync.md (arm_memory_barrier_v7): Use "dmb ish" since
+ the compiler usage is for multithreading, not external device sync.
+
+2009-12-04 Jim Grosbach <grosbach@apple.com>
+
+ Radar 7442004
+ * config/arm/t-darwin: Always build libgcc2 functions with -marm.
+
+2009-11-03 Stuart Hastings <stuart@apple.com>
+
+ Radar 6951876
+ * local-alloc.c (reg_inheritance_1): Check for int->float
+ SUBREG cast, assume it uses the pic-base. This is the
+ 32-bit float analogue to 6050374 (see below).
+
+2009-11-02 Stuart Hastings <stuart@apple.com>
+
+ Radar 7105615
+ * fold-const.c (fold_binary): When folding an unsigned
+ comparision into a signed comparision, set TREE_OVERFLOW so
+ that the loop optimizer in tree-vrp.c understands that the
+ user did not write this.
+
+2009-10-15 Jim Grosbach <grosbach@apple.com>
+
+ Radar 7295521
+ * config/arm/arm.c (arm_split_compare_and_swap): Call insns for
+ arm_memory_barrier* and arm_memory_sync* directory rather than using
+ the expander.
+ * config/arm/sync.md (memory_barrier, memory_sync): Allocate a scratch
+ register rather than forcing IP.
+ (arm_memory_barrier_v6): Match the scratch register from the expander
+ rather than forcing IP. Rename to arm_memory_barrier_v6_explicit.
+ (arm_memory_barrier_v6_explicit): New.
+ (arm_memory_sync_v6): Match the scratch register from the expander
+ rather than forcing IP. Rename to arm_memory_sync_v6_explicit.
+ (arm_memory_sync_v6_explicit): New.
+
2009-09-11 Caroline Tice <ctice@apple.com>
Radar 6419781
@@ -9,8 +58,8 @@
2009-09-08 Jim Grosbach <grosbach@apple.com>
- Radar 7174451
- * config/arm/arm.c (arm_select_dominance_cc_mode): Unordered floats.
+ Radar 7174451
+ * config/arm/arm.c (arm_select_dominance_cc_mode): Unordered floats.
2009-09-08 Jim Grosbach <grosbach@apple.com>
@@ -1468,8 +1517,8 @@
2008-07-21 Stuart Hastings <stuart@apple.com>
Radar 6050374
- * local-alloc.c (reg_inheritance_1): Check for int->fp SUBREG
- cast, assume it uses the pic-base.
+ * local-alloc.c (reg_inheritance_1): Check for int->double
+ SUBREG cast, assume it uses the pic-base.
2008-07-18 Fariborz Jahanian <fjahanian@apple.com>
diff --git a/llvm-gcc-4.2/gcc/config.gcc b/llvm-gcc-4.2/gcc/config.gcc
index 7184230..45b6370 100644
--- a/llvm-gcc-4.2/gcc/config.gcc
+++ b/llvm-gcc-4.2/gcc/config.gcc
@@ -430,6 +430,7 @@
tm_p_file="${tm_p_file} darwin-protos.h"
# APPLE LOCAL 5681645
tmake_file="t-darwin ${cpu_type}/t-darwin"
+ # LLVM LOCAL put va_opt in GC memory 7210265
target_gtfiles="\$(srcdir)/config/darwin.c \$(srcdir)/config/darwin-c.c"
extra_options="${extra_options} darwin.opt"
c_target_objs="darwin-c.o"
diff --git a/llvm-gcc-4.2/gcc/config/arm/arm.c b/llvm-gcc-4.2/gcc/config/arm/arm.c
index b78fbf1..6205ec0 100644
--- a/llvm-gcc-4.2/gcc/config/arm/arm.c
+++ b/llvm-gcc-4.2/gcc/config/arm/arm.c
@@ -2421,8 +2421,22 @@
enum machine_mode mode = GET_MODE (mem);
rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CC_REGNUM);
rtx dest_cmp, oldval_cmp;
+ rtx block_scratch, block_unspec;
- emit_insn (gen_memory_barrier ());
+ block_scratch = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
+ block_unspec = gen_rtx_UNSPEC (BLKmode,
+ gen_rtvec (1, gen_rtx_MEM (BLKmode,
+ block_scratch)),
+ UNSPEC_BARRIER);
+
+ /* Use the insn patterns directly rather than the expander since we're
+ * post-reload here. The v6 pattern needs a scratch register and we
+ * have one here already, so just re-use it. */
+ if (arm_arch7a)
+ emit_insn (gen_arm_memory_barrier_v7 (block_scratch, block_unspec));
+ else
+ emit_insn (gen_arm_memory_barrier_v6_explicit(block_scratch,
+ block_unspec, scratch));
label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
@@ -2481,7 +2495,11 @@
x = gen_rtx_IF_THEN_ELSE (VOIDmode, x, label1, pc_rtx);
x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
- emit_insn (gen_memory_sync ());
+ if (arm_arch7a)
+ emit_insn (gen_arm_memory_barrier_v7 (block_scratch, block_unspec));
+ else
+ emit_insn (gen_arm_memory_barrier_v6_explicit(block_scratch,
+ block_unspec, scratch));
emit_label (XEXP (label2, 0));
}
/* APPLE LOCAL end 6258536 atomic builtins */
@@ -14741,7 +14759,7 @@
}
return;
- /* APPLE LOCAL 6150859 begin use NEON instructions for SF math */
+ /* APPLE LOCAL begin 6150859 use NEON instructions for SF math */
/* This code prints the double precision register name starting at
register number of the indicated single precision register. */
case 'p':
@@ -14766,7 +14784,7 @@
fprintf (stream, "d%d", (regno - FIRST_VFP_REGNUM) >> 1);
}
return;
- /* APPLE LOCAL 6150859 end use NEON instructions for SF math */
+ /* APPLE LOCAL end 6150859 use NEON instructions for SF math */
/* These two codes print the low/high doubleword register of a Neon quad
register, respectively. For pair-structure types, can also print
diff --git a/llvm-gcc-4.2/gcc/config/arm/arm1136jfs.md b/llvm-gcc-4.2/gcc/config/arm/arm1136jfs.md
index 3086697..5044a87 100644
--- a/llvm-gcc-4.2/gcc/config/arm/arm1136jfs.md
+++ b/llvm-gcc-4.2/gcc/config/arm/arm1136jfs.md
@@ -267,9 +267,11 @@
"11_branches")
(define_bypass 2 "11_alu_shift_reg_op"
"11_branches")
-(define_bypass 2 "11_load1,11_load2"
+;; APPLE LOCAL 6930582 load latencies
+(define_bypass 3 "11_load1,11_load2"
"11_branches")
-(define_bypass 3 "11_load34"
+;; APPLE LOCAL 6930582 load latencies
+(define_bypass 4 "11_load34"
"11_branches")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -282,7 +284,8 @@
;; if the PC is one of the registers involved, there are additional stalls
;; not modelled here. Addressing modes are also not modelled.
-(define_insn_reservation "11_load1" 3
+;; APPLE LOCAL 6930582 load latencies
+(define_insn_reservation "11_load1" 4
(and (eq_attr "tune" "arm1136js,arm1136jfs")
(eq_attr "type" "load1"))
"l_a+e_1,l_dc1,l_dc2,l_wb")
@@ -303,7 +306,8 @@
;; Load/store double words into adjacent registers. The timing and
;; latencies are different depending on whether the address is 64-bit
;; aligned. This model assumes that it is.
-(define_insn_reservation "11_load2" 3
+;; APPLE LOCAL 6930582 load latencies
+(define_insn_reservation "11_load2" 4
(and (eq_attr "tune" "arm1136js,arm1136jfs")
(eq_attr "type" "load2"))
"l_a+e_1,l_dc1,l_dc2,l_wb")
@@ -316,7 +320,8 @@
;; Load/store multiple registers. Two registers are stored per cycle.
;; Actual timing depends on how many registers are affected, so we
;; optimistically schedule a low latency.
-(define_insn_reservation "11_load34" 4
+;; APPLE LOCAL 6930582 load latencies
+(define_insn_reservation "11_load34" 5
(and (eq_attr "tune" "arm1136js,arm1136jfs")
(eq_attr "type" "load3,load4"))
"l_a+e_1,l_dc1*2,l_dc2,l_wb")
@@ -337,14 +342,16 @@
;; An alu op can start sooner after a load, if that alu op does not
;; have an early register dependency on the load
-(define_bypass 2 "11_load1"
+;; APPLE LOCAL begin 6930582 load latencies
+(define_bypass 3 "11_load1"
"11_alu_op")
-(define_bypass 2 "11_load1"
+(define_bypass 3 "11_load1"
"11_alu_shift_op"
"arm_no_early_alu_shift_value_dep")
-(define_bypass 2 "11_load1"
+(define_bypass 3 "11_load1"
"11_alu_shift_reg_op"
"arm_no_early_alu_shift_dep")
+;; APPLE LOCAL end 6930582 load latencies
(define_bypass 3 "11_loadb"
"11_alu_op")
@@ -357,10 +364,12 @@
;; A mul op can start sooner after a load, if that mul op does not
;; have an early multiply dependency
-(define_bypass 2 "11_load1"
+;; APPLE LOCAL 6930582 load latencies
+(define_bypass 3 "11_load1"
"11_mult1,11_mult2,11_mult3,11_mult4,11_mult5,11_mult6,11_mult7"
"arm_no_early_mul_dep")
-(define_bypass 3 "11_load34"
+;; APPLE LOCAL 6930582 load latencies
+(define_bypass 4 "11_load34"
"11_mult1,11_mult2,11_mult3,11_mult4,11_mult5,11_mult6,11_mult7"
"arm_no_early_mul_dep")
(define_bypass 3 "11_loadb"
@@ -369,7 +378,8 @@
;; A store can start sooner after a load, if that load does not
;; produce part of the address to access
-(define_bypass 2 "11_load1"
+;; APPLE LOCAL 6930582 load latencies
+(define_bypass 3 "11_load1"
"11_store1"
"arm_no_early_store_addr_dep")
(define_bypass 3 "11_loadb"
diff --git a/llvm-gcc-4.2/gcc/config/arm/cortex-a8.md b/llvm-gcc-4.2/gcc/config/arm/cortex-a8.md
index f5b6e38..c311f65 100644
--- a/llvm-gcc-4.2/gcc/config/arm/cortex-a8.md
+++ b/llvm-gcc-4.2/gcc/config/arm/cortex-a8.md
@@ -187,22 +187,24 @@
;; Load instructions.
;; The presence of any register writeback is ignored here.
-;; A load result has latency 3 unless the dependent instruction has
-;; no early dep, in which case it is only latency two.
+;; APPLE LOCAL begin 6930582 load latencies
+;; A load result has latency 4 unless the dependent instruction has
+;; no early dep, in which case it is only latency three.
;; We assume 64-bit alignment for doubleword loads.
-(define_insn_reservation "cortex_a8_load1_2" 3
+(define_insn_reservation "cortex_a8_load1_2" 4
(and (eq_attr "tune" "cortexa8")
(eq_attr "type" "load1,load2,load_byte"))
"cortex_a8_load_store_1")
-(define_bypass 2 "cortex_a8_load1_2"
+(define_bypass 3 "cortex_a8_load1_2"
"cortex_a8_alu")
-(define_bypass 2 "cortex_a8_load1_2"
+(define_bypass 3 "cortex_a8_load1_2"
"cortex_a8_alu_shift"
"arm_no_early_alu_shift_dep")
-(define_bypass 2 "cortex_a8_load1_2"
+(define_bypass 3 "cortex_a8_load1_2"
"cortex_a8_alu_shift_reg"
"arm_no_early_alu_shift_value_dep")
+;; APPLE LOCAL end 6930582 load latencies
;; We do not currently model the fact that loads with scaled register
;; offsets that are not LSL #2 have an extra cycle latency (they issue
diff --git a/llvm-gcc-4.2/gcc/config/arm/linux-eabi.h b/llvm-gcc-4.2/gcc/config/arm/linux-eabi.h
index 2494199..95c5aae 100644
--- a/llvm-gcc-4.2/gcc/config/arm/linux-eabi.h
+++ b/llvm-gcc-4.2/gcc/config/arm/linux-eabi.h
@@ -79,6 +79,7 @@
register unsigned long _end __asm ("a2") = (unsigned long) (END); \
register unsigned long _flg __asm ("a3") = 0; \
register unsigned long _scno __asm ("r7") = 0xf0002; \
+ /* LLVM LOCAL use valid SWI instruction */ \
__asm __volatile ("swi 0 @ sys_cacheflush" \
: "=r" (_beg) \
: "0" (_beg), "r" (_end), "r" (_flg), "r" (_scno)); \
diff --git a/llvm-gcc-4.2/gcc/config/arm/sync.md b/llvm-gcc-4.2/gcc/config/arm/sync.md
index b06ebdf..9994907 100644
--- a/llvm-gcc-4.2/gcc/config/arm/sync.md
+++ b/llvm-gcc-4.2/gcc/config/arm/sync.md
@@ -45,8 +45,7 @@
gen_rtvec (1, gen_rtx_MEM (BLKmode,
operands[0])),
UNSPEC_BARRIER));
- XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG(SImode,
- IP_REGNUM));
+ XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH(SImode));
emit_insn (par);
DONE;
}
@@ -56,16 +55,32 @@
[(set (match_operand:BLK 0 "" "")
(unspec:BLK [(match_operand:BLK 1 "" "")] UNSPEC_BARRIER))]
"TARGET_32BIT && arm_arch7a"
- "dmb"
+ "dmb\tish"
[(set_attr "length" "4")]
)
-(define_insn "arm_memory_barrier_v6"
+;; This version matches the define_expand above.
+(define_insn "arm_memory_barrier_v6_scratch"
[(set (match_operand:BLK 0 "" "")
(unspec:BLK [(match_operand:BLK 1 "" "")] UNSPEC_BARRIER))
- (clobber (reg:SI IP_REGNUM))]
+ (clobber (match_scratch:SI 2 "=&r"))]
"TARGET_32BIT && arm_arch6 && !arm_arch7a"
- "mov\tip, #0\n\tmcr\tp15, 0, ip, c7, c10, 5"
+ "mov\t%2, #0\n\tmcr\tp15, 0, %2, c7, c10, 5"
+ [(set (attr "length")
+ (if_then_else (eq_attr "is_thumb" "yes")
+ (const_int 6)
+ (const_int 8)))]
+)
+
+;; This version is used directly by the compare_and_swap splitter below.
+;; That runs after reload is complete, so we cannot use a new define_scratch.
+;; reload is not available to allocate one for us.
+(define_insn "arm_memory_barrier_v6_explicit"
+ [(set (match_operand:BLK 0 "" "")
+ (unspec:BLK [(match_operand:BLK 1 "" "")] UNSPEC_BARRIER))
+ (clobber (match_operand:SI 2 "register_operand" "=&r"))]
+ "TARGET_32BIT && arm_arch6 && !arm_arch7a"
+ "mov\t%2, #0\n\tmcr\tp15, 0, %2, c7, c10, 5"
[(set (attr "length")
(if_then_else (eq_attr "is_thumb" "yes")
(const_int 6)
@@ -91,8 +106,7 @@
gen_rtx_UNSPEC_VOLATILE (BLKmode,
gen_rtvec (1, operands[0]),
UNSPEC_SYNC));
- XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG(SImode,
- IP_REGNUM));
+ XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH(SImode));
emit_insn (par);
DONE;
}
@@ -106,12 +120,28 @@
[(set_attr "length" "4")]
)
-(define_insn "arm_memory_sync_v6"
+;; This version matches the define_expand above.
+(define_insn "arm_memory_sync_v6_scratch"
[(set (match_operand:BLK 0 "" "")
(unspec_volatile:BLK [(mem:BLK (match_operand 1))] UNSPEC_SYNC))
- (clobber (reg:SI IP_REGNUM))]
+ (clobber (match_scratch:SI 2 "=&r"))]
"TARGET_32BIT && arm_arch6 && !arm_arch7a"
- "mov\tip, #0\n\tmcr\tp15, 0, ip, c7, c10, 4"
+ "mov\t%2, #0\n\tmcr\tp15, 0, %2, c7, c10, 4"
+ [(set (attr "length")
+ (if_then_else (eq_attr "is_thumb" "yes")
+ (const_int 6)
+ (const_int 8)))]
+)
+
+;; This version is used directly by the compare_and_swap splitter below.
+;; That runs after reload is complete, so we cannot use a new define_scratch.
+;; reload is not available to allocate one for us.
+(define_insn "arm_memory_sync_v6_explicit"
+ [(set (match_operand:BLK 0 "" "")
+ (unspec_volatile:BLK [(mem:BLK (match_operand 1))] UNSPEC_SYNC))
+ (clobber (match_operand:SI 2 "register_operand" "=&r"))]
+ "TARGET_32BIT && arm_arch6 && !arm_arch7a"
+ "mov\t%2, #0\n\tmcr\tp15, 0, %2, c7, c10, 4"
[(set (attr "length")
(if_then_else (eq_attr "is_thumb" "yes")
(const_int 6)
diff --git a/llvm-gcc-4.2/gcc/config/arm/t-darwin b/llvm-gcc-4.2/gcc/config/arm/t-darwin
index 8f40be3..2d79020 100644
--- a/llvm-gcc-4.2/gcc/config/arm/t-darwin
+++ b/llvm-gcc-4.2/gcc/config/arm/t-darwin
@@ -70,5 +70,6 @@
endif
# APPLE LOCAL end 6611402 configurable multilib architectures
-TARGET_LIBGCC2_CFLAGS = -fno-inline
+# APPLE LOCAL 7442004 Always build multilib libgcc functions ARM mode.
+TARGET_LIBGCC2_CFLAGS = -fno-inline -marm
diff --git a/llvm-gcc-4.2/gcc/config/darwin-c.c b/llvm-gcc-4.2/gcc/config/darwin-c.c
index 4ef760d..9fea1b6 100644
--- a/llvm-gcc-4.2/gcc/config/darwin-c.c
+++ b/llvm-gcc-4.2/gcc/config/darwin-c.c
@@ -412,6 +412,7 @@
/* APPLE LOCAL end pragma reverse_bitfields */
/* APPLE LOCAL begin optimization pragmas 3124235/3420242 */
+/* LLVM LOCAL put va_opt in GC memory 7210265 */
static GTY(()) varray_type va_opt;
static void
@@ -1245,4 +1246,5 @@
return decl;
}
/* APPLE LOCAL end radar 2996215 - 6068877 */
+/* LLVM LOCAL put va_opt in GC memory 7210265 */
#include "gt-darwin-c.h"
diff --git a/llvm-gcc-4.2/gcc/config/t-darwin b/llvm-gcc-4.2/gcc/config/t-darwin
index abd8254..8b94934 100644
--- a/llvm-gcc-4.2/gcc/config/t-darwin
+++ b/llvm-gcc-4.2/gcc/config/t-darwin
@@ -14,12 +14,15 @@
config/darwin-sections.def
$(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $(srcdir)/config/darwin.c
+# LLVM LOCAL begin put va_opt in GC memory 7210265
darwin-c.o: $(srcdir)/config/darwin-c.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \
$(TM_H) $(CPPLIB_H) $(TREE_H) c-pragma.h $(C_TREE_H) toplev.h $(TM_P_H) \
c-incpath.h flags.h $(C_COMMON_H) gt-darwin-c.h
$(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $(srcdir)/config/darwin-c.c $(PREPROCESSOR_DEFINES)
+# LLVM LOCAL end put va_opt in GC memory 7210265
gt-darwin.h : s-gtype ; @true
+# LLVM LOCAL put va_opt in GC memory 7210265
gt-darwin-c.h : s-gtype ; @true
# APPLE LOCAL begin mainline 2007-06-14 5235474
diff --git a/llvm-gcc-4.2/gcc/cp/parser.c b/llvm-gcc-4.2/gcc/cp/parser.c
index ba03650..a815e96 100644
--- a/llvm-gcc-4.2/gcc/cp/parser.c
+++ b/llvm-gcc-4.2/gcc/cp/parser.c
@@ -21078,12 +21078,11 @@
CONSTRUCTOR_ELTS (constructor) = build_block_struct_initlist (block_struct_type,
block_impl);
/* Temporary representing a global block is made global static. */
- /* APPLE LOCAL begin radar 6230297 */
+ /* APPLE LOCAL radar 6230297 */
if (staticBlockTmp || global_bindings_p ()) {
TREE_PUBLIC (block_holder_tmp_decl) = 0;
TREE_STATIC (block_holder_tmp_decl) = 1;
}
- /* APPLE LOCAL end radar 6230297 */
cp_finish_decl (block_holder_tmp_decl, constructor, 0, 0, LOOKUP_ONLYCONVERTING);
return block_holder_tmp_decl;
}
diff --git a/llvm-gcc-4.2/gcc/doc/invoke.texi b/llvm-gcc-4.2/gcc/doc/invoke.texi
index 3eecab0..e002026 100644
--- a/llvm-gcc-4.2/gcc/doc/invoke.texi
+++ b/llvm-gcc-4.2/gcc/doc/invoke.texi
@@ -175,8 +175,10 @@
@table @emph
@item Overall Options
@xref{Overall Options,,Options Controlling the Kind of Output}.
+@c LLVM LOCAL begin no-canonical-prefixes
@gccoptlist{-c -S -E -o @var{file} -combine -no-canonical-prefixes @gol
-pipe -pass-exit-codes @gol
+@c LLVM LOCAL end no-canonical-prefixes
@c APPLE LOCAL -ObjC 2001-08-03 --sts **
-ObjC (APPLE ONLY) -ObjC++ (APPLE ONLY) @gol
@c APPLE LOCAL begin fat builds
@@ -1239,11 +1241,13 @@
Print (on the standard output) a description of target specific command
line options for each tool.
+@c LLVM LOCAL begin no-canonical-prefixes
@item -no-canonical-prefixes
@opindex no-canonical-prefixes
Do not expand any symbolic links, resolve references to @samp{/../}
or @samp{/./}, or make the path absolute when generating a relative
prefix.
+@c LLVM LOCAL end no-canonical-prefixes
@item --version
@opindex version
diff --git a/llvm-gcc-4.2/gcc/fold-const.c b/llvm-gcc-4.2/gcc/fold-const.c
index d4c58fb..45263d2 100644
--- a/llvm-gcc-4.2/gcc/fold-const.c
+++ b/llvm-gcc-4.2/gcc/fold-const.c
@@ -11280,10 +11280,24 @@
if (code == LE_EXPR || code == GT_EXPR)
{
tree st;
+ /* APPLE LOCAL begin 7105615 */
+ tree ov_zero;
st = lang_hooks.types.signed_type (TREE_TYPE (arg1));
+ /*
+ * We need a zero that is NOT part of the constant
+ * pool, because we're going to set its
+ * TREE_OVERFLOW bit. If the returned
+ * CONSTANT_INT is part of the constant pool, it
+ * may be returned to another caller in another
+ * context (i.e. tree-vrp.c), who may arbitrarily
+ * *clear* this TREE_OVERFLOW bit.
+ */
+ ov_zero = copy_node (build_int_cst (st, 0));
+ TREE_OVERFLOW (ov_zero) = 1;
return fold_build2 (code == LE_EXPR ? GE_EXPR : LT_EXPR,
type, fold_convert (st, arg0),
- build_int_cst (st, 0));
+ ov_zero);
+ /* APPLE LOCAL end 7105615 */
}
}
}
diff --git a/llvm-gcc-4.2/gcc/gcc.c b/llvm-gcc-4.2/gcc/gcc.c
index 8f40ea4..3cc86c3 100644
--- a/llvm-gcc-4.2/gcc/gcc.c
+++ b/llvm-gcc-4.2/gcc/gcc.c
@@ -1190,6 +1190,7 @@
/* LLVM LOCAL end */
{"--machine", "-m", "aj"},
{"--machine-", "-m", "*j"},
+ /* LLVM LOCAL no-canonical-prefixes */
{"--no-canonical-prefixes", "-no-canonical-prefixes", 0},
{"--no-integrated-cpp", "-no-integrated-cpp", 0},
{"--no-line-commands", "-P", 0},
@@ -3342,10 +3343,11 @@
fputs (_(" -Xlinker <arg> Pass <arg> on to the linker\n"), stdout);
fputs (_(" -combine Pass multiple source files to compiler at once\n"), stdout);
fputs (_(" -save-temps Do not delete intermediate files\n"), stdout);
+ /* LLVM LOCAL begin no-canonical-prefixes */
fputs (_("\
-no-canonical-prefixes Do not canonicalize paths when building relative\n\
prefixes to other gcc components\n"), stdout);
-
+ /* LLVM LOCAL end no-canonical-prefixes */
fputs (_(" -pipe Use pipes rather than intermediate files\n"), stdout);
fputs (_(" -time Time the execution of each subprocess\n"), stdout);
fputs (_(" -specs=<file> Override built-in specs with the contents of <file>\n"), stdout);
@@ -3438,8 +3440,10 @@
int is_modify_target_name;
unsigned int j;
#endif
+ /* LLVM LOCAL begin no-canonical-prefixes */
char *(*get_relative_prefix) (const char *, const char *,
const char *) = NULL;
+ /* LLVM LOCAL end no-canonical-prefixes */
GET_ENVIRONMENT (gcc_exec_prefix, "GCC_EXEC_PREFIX");
@@ -3526,6 +3530,7 @@
fatal ("couldn't run '%s': %s", new_argv0, xstrerror (errno));
}
+ /* LLVM LOCAL begin no-canonical-prefixes */
/* Convert new-style -- options to old-style. */
translate_options (&argc, (const char * const **) &argv);
@@ -3547,6 +3552,7 @@
}
if (! get_relative_prefix)
get_relative_prefix = make_relative_prefix;
+ /* LLVM LOCAL end no-canonical-prefixes */
/* Set up the default search paths. If there is no GCC_EXEC_PREFIX,
see if we can create it from the pathname specified in argv[0]. */
@@ -3556,12 +3562,14 @@
/* FIXME: make_relative_prefix doesn't yet work for VMS. */
if (!gcc_exec_prefix)
{
+ /* LLVM LOCAL begin no-canonical-prefixes */
gcc_exec_prefix = get_relative_prefix (argv[0],
standard_bindir_prefix,
standard_exec_prefix);
gcc_libexec_prefix = get_relative_prefix (argv[0],
standard_bindir_prefix,
standard_libexec_prefix);
+ /* LLVM LOCAL end no-canonical-prefixes */
if (gcc_exec_prefix)
putenv (concat ("GCC_EXEC_PREFIX=", gcc_exec_prefix, NULL));
}
@@ -3572,9 +3580,11 @@
/ (which is ignored by make_relative_prefix), so append a
program name. */
char *tmp_prefix = concat (gcc_exec_prefix, "gcc", NULL);
+ /* LLVM LOCAL begin no-canonical-prefixes */
gcc_libexec_prefix = get_relative_prefix (tmp_prefix,
standard_exec_prefix,
standard_libexec_prefix);
+ /* LLVM LOCAL end no-canonical-prefixes */
free (tmp_prefix);
}
#else
@@ -3704,6 +3714,9 @@
}
}
+ /* LLVM LOCAL begin no-canonical-prefixes */
+ /* LLVM LOCAL end no-canonical-prefixes */
+
/* Scan argv twice. Here, the first time, just count how many switches
there will be in their vector, and how many input files in theirs.
Here we also parse the switches that cc itself uses (e.g. -v). */
@@ -3915,9 +3928,11 @@
n_infiles += 2;
i++;
}
+ /* LLVM LOCAL begin no-canonical-prefixes */
else if (strcmp (argv[i], "-no-canonical-prefixes") == 0)
/* Already handled as a special case, so ignored here. */
;
+ /* LLVM LOCAL end no-canonical-prefixes */
/* APPLE LOCAL end -weak_* (radar 3235250) */
else if (strcmp (argv[i], "-combine") == 0)
{
@@ -4251,9 +4266,11 @@
``make_relative_prefix'' is not compiled for VMS, so don't call it. */
if (target_system_root && gcc_exec_prefix)
{
+ /* LLVM LOCAL begin no-canonical-prefixes */
char *tmp_prefix = get_relative_prefix (argv[0],
standard_bindir_prefix,
target_system_root);
+ /* LLVM LOCAL end no-canonical-prefixes */
if (tmp_prefix && access_check (tmp_prefix, F_OK) == 0)
{
target_system_root = tmp_prefix;
@@ -4295,8 +4312,10 @@
;
else if (! strncmp (argv[i], "-Wp,", 4))
;
+ /* LLVM LOCAL begin no-canonical-prefixes */
else if (! strcmp (argv[i], "-no-canonical-prefixes"))
;
+ /* LLVM LOCAL end no-canonical-prefixes */
else if (! strcmp (argv[i], "-pass-exit-codes"))
;
else if (! strcmp (argv[i], "-print-search-dirs"))
diff --git a/llvm-gcc-4.2/gcc/local-alloc.c b/llvm-gcc-4.2/gcc/local-alloc.c
index 4589db0..4e69b3a 100644
--- a/llvm-gcc-4.2/gcc/local-alloc.c
+++ b/llvm-gcc-4.2/gcc/local-alloc.c
@@ -2679,19 +2679,24 @@
dstregno = (int)data;
#ifdef TARGET_386
- /* Ugly special case: When moving a DImode constant into an FP
- register, GCC will use the movdf_nointeger pattern, pushing the
- DImode constant into memory and loading into the '387. It looks
- like this: (set (reg:DF) (subreg:DF (reg:DI))). We're choosing
- to match the subreg; hope this is sufficient.
+ /*
+ Ugly special case: When moving a DI/SI/mode constant into an FP
+ register, GCC will use the mov/df/sf/_nointeger pattern, pushing
+ the DI/SI/mode constant into memory and loading therefrom into an
+ FP register ('387 or SSE). It looks like this: (set (reg:DF)
+ (subreg:DF (reg:DI))). We're choosing to match the subreg; hope
+ this is sufficient. See Radars 6050374 and 6951876.
*/
- if (GET_CODE (x) == SUBREG
- && GET_MODE (x) == DFmode
- && GET_MODE (SUBREG_REG (x)) == DImode)
- {
- SET_BIT (reg_inheritance_matrix[dstregno], PIC_OFFSET_TABLE_REGNUM);
- return 0;
- }
+ if (GET_CODE (x) == SUBREG)
+ if ((GET_MODE (x) == DFmode
+ && GET_MODE (SUBREG_REG (x)) == DImode)
+ ||
+ (GET_MODE (x) == SFmode
+ && GET_MODE (SUBREG_REG (x)) == SImode))
+ {
+ SET_BIT (reg_inheritance_matrix[dstregno], PIC_OFFSET_TABLE_REGNUM);
+ return 0;
+ }
#endif
if (GET_CODE (x) == SUBREG)
x = SUBREG_REG (x);
diff --git a/llvm-gcc-4.2/gcc/testsuite/ChangeLog.apple b/llvm-gcc-4.2/gcc/testsuite/ChangeLog.apple
index 9f8b45f..14baae2 100644
--- a/llvm-gcc-4.2/gcc/testsuite/ChangeLog.apple
+++ b/llvm-gcc-4.2/gcc/testsuite/ChangeLog.apple
@@ -1,3 +1,13 @@
+2009-11-03 Stuart Hastings <stuart@apple.com>
+
+ Radar 6951876
+ * gcc.dg/6951876.c: New.
+
+2009-11-02 Stuart Hastings <stuart@apple.com>
+
+ Radar 7105615
+ * gcc.dg/7105615.c: New.
+
2009-06-15 Fariborz Jahanian <fjahanian@apple.com>
Radar 6936421
diff --git a/llvm-gcc-4.2/gcc/testsuite/gcc.dg/6951876.c b/llvm-gcc-4.2/gcc/testsuite/gcc.dg/6951876.c
new file mode 100644
index 0000000..40994db
--- /dev/null
+++ b/llvm-gcc-4.2/gcc/testsuite/gcc.dg/6951876.c
@@ -0,0 +1,28 @@
+/* APPLE LOCAL file 6951876 */
+/* { dg-do compile { target { { i?86-*-* x86_64-*-* } && ilp32 } } } */
+/* { dg-options "-O2" } */
+/* Kludge: assuming PIC-base labels have a particular format: */
+/* { dg-final { scan-assembler "\"L00\[0-9\]*\\\$pb\":" } } */
+extern unsigned char*GetLine(int *s, int y);
+typedef struct {
+ int dst;
+} PIXWEIGHT ;
+typedef union {
+ int i;
+ float f;
+} INTTORFLOAT;
+void __Rescale(int *src)
+{
+ int i, y;
+ INTTORFLOAT bias;
+ INTTORFLOAT f;
+ bias.i = 22;
+ for (;;)
+ {
+ GetLine(src, y);
+ float * dstata;
+ PIXWEIGHT * _p;
+ f.f-=bias.f;
+ dstata[_p->dst] += f.f;
+ }
+}
diff --git a/llvm-gcc-4.2/gcc/testsuite/gcc.dg/7105615.c b/llvm-gcc-4.2/gcc/testsuite/gcc.dg/7105615.c
new file mode 100644
index 0000000..9b792bd
--- /dev/null
+++ b/llvm-gcc-4.2/gcc/testsuite/gcc.dg/7105615.c
@@ -0,0 +1,13 @@
+/* APPLE LOCAL file 7105615 */
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-strict-overflow" } */
+int
+main() {
+ unsigned char uch;
+ unsigned int ui = 0;
+
+ /* Original failure was an infinite loop: */
+ for (uch = 0; uch < 0x80; uch++)
+ ui = uch + ui;
+ return ui != 8128; /* Return 0 for success. */
+}
diff --git a/llvm-gcc-4.2/gcc/tree-eh.c b/llvm-gcc-4.2/gcc/tree-eh.c
index 9e69193..f93ad64 100644
--- a/llvm-gcc-4.2/gcc/tree-eh.c
+++ b/llvm-gcc-4.2/gcc/tree-eh.c
@@ -839,10 +839,12 @@
save_eptr = create_tmp_var (ptr_type_node, "save_eptr");
save_filt = create_tmp_var (integer_type_node, "save_filt");
+
i = tsi_start (finally);
x = build0 (EXC_PTR_EXPR, ptr_type_node);
x = build2 (MODIFY_EXPR, void_type_node, save_eptr, x);
tsi_link_before (&i, x, TSI_CONTINUE_LINKING);
+
x = build0 (FILTER_EXPR, integer_type_node);
x = build2 (MODIFY_EXPR, void_type_node, save_filt, x);
tsi_link_before (&i, x, TSI_CONTINUE_LINKING);
diff --git a/llvm-gcc-4.2/gcc/version.c b/llvm-gcc-4.2/gcc/version.c
index 12184ab..20e49e7 100644
--- a/llvm-gcc-4.2/gcc/version.c
+++ b/llvm-gcc-4.2/gcc/version.c
@@ -11,12 +11,12 @@
/* APPLE LOCAL begin Apple version */
#ifdef ENABLE_LLVM
#ifdef LLVM_VERSION_INFO
-#define VERSUFFIX " (Based on Apple Inc. build 5653) (LLVM build " LLVM_VERSION_INFO ")"
+#define VERSUFFIX " (Based on Apple Inc. build 5658) (LLVM build " LLVM_VERSION_INFO ")"
#else
-#define VERSUFFIX " (Based on Apple Inc. build 5653) (LLVM build)"
+#define VERSUFFIX " (Based on Apple Inc. build 5658) (LLVM build)"
#endif
#else
-#define VERSUFFIX " (Based on Apple Inc. build 5653)"
+#define VERSUFFIX " (Based on Apple Inc. build 5658)"
#endif
/* APPLE LOCAL end Apple version */
