{
   "context" : "{  :  }",
   "name" : "for.preheader => for.end10",
   "statements" : [
      {
         "accesses" : [
            {
               "kind" : "write",
               "relation" : "{ Stmt_for_preheader[i0] -> MemRef_acc_reg2mem[0] }"
            }
         ],
         "domain" : "{ Stmt_for_preheader[i0] : i0 >= 0 and i0 <= 19 }",
         "name" : "Stmt_for_preheader",
         "schedule" : "{ Stmt_for_preheader[i0] -> [o0, o1, i0, 19i0, 0] : exists (e0 = [(o1)/32], e1 = [(o0)/32]: 32e0 = o1 and 32e1 = o0 and o0 <= i0 and o0 >= -31 + i0 and o1 <= 19i0 and o1 >= -31 + 19i0 and i0 >= 0 and i0 <= 19) }"
      },
      {
         "accesses" : [
            {
               "kind" : "write",
               "relation" : "{ Stmt_for_inc[i0, i1] -> MemRef_acc_reg2mem[0] }"
            }
         ],
         "domain" : "{ Stmt_for_inc[i0, i1] : i0 >= 0 and i0 <= 19 and i1 >= 0 and i1 <= 19 }",
         "name" : "Stmt_for_inc",
         "schedule" : "{ Stmt_for_inc[i0, i1] -> [o0, o1, i0, 19i0 + i1, 1] : exists (e0 = [(o1)/32], e1 = [(o0)/32]: 32e0 = o1 and 32e1 = o0 and o0 <= i0 and o0 >= -31 + i0 and o1 <= 19i0 + i1 and o1 >= -31 + 19i0 + i1 and i0 >= 0 and i0 <= 19 and i1 >= 0 and i1 <= 19) }"
      }
   ]
}