# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s

--- |
  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"

  define void @add_s32_gpr() { ret void }
  define void @add_s64_gpr() { ret void }

  define void @add_imm_s32_gpr() { ret void }
  define void @add_imm_s64_gpr() { ret void }

  define void @add_imm_s32_gpr_bb() { ret void }

  define void @sub_s32_gpr() { ret void }
  define void @sub_s64_gpr() { ret void }

  define void @or_s32_gpr() { ret void }
  define void @or_s64_gpr() { ret void }
  define void @or_v2s32_fpr() { ret void }

  define void @and_s32_gpr() { ret void }
  define void @and_s64_gpr() { ret void }

  define void @shl_s32_gpr() { ret void }
  define void @shl_s64_gpr() { ret void }

  define void @lshr_s32_gpr() { ret void }
  define void @lshr_s64_gpr() { ret void }

  define void @ashr_s32_gpr() { ret void }
  define void @ashr_s64_gpr() { ret void }

  define void @mul_s32_gpr() { ret void }
  define void @mul_s64_gpr() { ret void }

  define void @mulh_s64_gpr() { ret void }

  define void @sdiv_s32_gpr() { ret void }
  define void @sdiv_s64_gpr() { ret void }

  define void @udiv_s32_gpr() { ret void }
  define void @udiv_s64_gpr() { ret void }

  define void @fadd_s32_fpr() { ret void }
  define void @fadd_s64_fpr() { ret void }

  define void @fsub_s32_fpr() { ret void }
  define void @fsub_s64_fpr() { ret void }

  define void @fmul_s32_fpr() { ret void }
  define void @fmul_s64_fpr() { ret void }

  define void @fdiv_s32_fpr() { ret void }
  define void @fdiv_s64_fpr() { ret void }

...

---
# Check that we select a 32-bit GPR G_ADD into ADDWrr on GPR32.
# Also check that we constrain the register class of the COPY to GPR32.
name:            add_s32_gpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

body:             |
  bb.0:
    liveins: %w0, %w1

    ; CHECK-LABEL: name: add_s32_gpr
    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
    ; CHECK: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]
    ; CHECK: %w0 = COPY [[ADDWrr]]
    %0(s32) = COPY %w0
    %1(s32) = COPY %w1
    %2(s32) = G_ADD %0, %1
    %w0 = COPY %2(s32)
...

---
# Same as add_s32_gpr, for 64-bit operations.
name:            add_s64_gpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

body:             |
  bb.0:
    liveins: %x0, %x1

    ; CHECK-LABEL: name: add_s64_gpr
    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
    ; CHECK: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[COPY1]]
    ; CHECK: %x0 = COPY [[ADDXrr]]
    %0(s64) = COPY %x0
    %1(s64) = COPY %x1
    %2(s64) = G_ADD %0, %1
    %x0 = COPY %2(s64)
...

---
name:            add_imm_s32_gpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

body:             |
  bb.0:
    liveins: %w0, %w1

    ; CHECK-LABEL: name: add_imm_s32_gpr
    ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY %w0
    ; CHECK: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 1, 0
    ; CHECK: %w0 = COPY [[ADDWri]]
    %0(s32) = COPY %w0
    %1(s32) = G_CONSTANT i32 1
    %2(s32) = G_ADD %0, %1
    %w0 = COPY %2(s32)
...

---
name:            add_imm_s64_gpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

body:             |
  bb.0:
    liveins: %x0, %w1

    ; CHECK-LABEL: name: add_imm_s64_gpr
    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
    ; CHECK: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 1, 0
    ; CHECK: %x0 = COPY [[ADDXri]]
    %0(s64) = COPY %x0
    %1(s64) = G_CONSTANT i32 1
    %2(s64) = G_ADD %0, %1
    %x0 = COPY %2(s64)
...

---
name:            add_imm_s32_gpr_bb
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

body:             |
  ; CHECK-LABEL: name: add_imm_s32_gpr_bb
  ; CHECK: bb.0:
  ; CHECK:   successors: %bb.1(0x80000000)
  ; CHECK:   [[COPY:%[0-9]+]]:gpr32sp = COPY %w0
  ; CHECK:   B %bb.1
  ; CHECK: bb.1:
  ; CHECK:   [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 1, 0
  ; CHECK:   %w0 = COPY [[ADDWri]]
  bb.0:
    liveins: %w0, %w1
    successors: %bb.1

    %0(s32) = COPY %w0
    %1(s32) = G_CONSTANT i32 1
    G_BR %bb.1

  bb.1:
    %2(s32) = G_ADD %0, %1
    %w0 = COPY %2(s32)
...

---
# Same as add_s32_gpr, for G_SUB operations.
name:            sub_s32_gpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

body:             |
  bb.0:
    liveins: %w0, %w1

    ; CHECK-LABEL: name: sub_s32_gpr
    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
    ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[COPY1]], implicit-def %nzcv
    ; CHECK: %w0 = COPY [[SUBSWrr]]
    %0(s32) = COPY %w0
    %1(s32) = COPY %w1
    %2(s32) = G_SUB %0, %1
    %w0 = COPY %2(s32)
...

---
# Same as add_s64_gpr, for G_SUB operations.
name:            sub_s64_gpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

body:             |
  bb.0:
    liveins: %x0, %x1

    ; CHECK-LABEL: name: sub_s64_gpr
    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
    ; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY1]], implicit-def %nzcv
    ; CHECK: %x0 = COPY [[SUBSXrr]]
    %0(s64) = COPY %x0
    %1(s64) = COPY %x1
    %2(s64) = G_SUB %0, %1
    %x0 = COPY %2(s64)
...

---
# Same as add_s32_gpr, for G_OR operations.
name:            or_s32_gpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

body:             |
  bb.0:
    liveins: %w0, %w1

    ; CHECK-LABEL: name: or_s32_gpr
    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
    ; CHECK: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[COPY]], [[COPY1]]
    ; CHECK: %w0 = COPY [[ORRWrr]]
    %0(s32) = COPY %w0
    %1(s32) = COPY %w1
    %2(s32) = G_OR %0, %1
    %w0 = COPY %2(s32)
...

---
# Same as add_s64_gpr, for G_OR operations.
name:            or_s64_gpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

body:             |
  bb.0:
    liveins: %x0, %x1

    ; CHECK-LABEL: name: or_s64_gpr
    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
    ; CHECK: [[ORRXrr:%[0-9]+]]:gpr64 = ORRXrr [[COPY]], [[COPY1]]
    ; CHECK: %x0 = COPY [[ORRXrr]]
    %0(s64) = COPY %x0
    %1(s64) = COPY %x1
    %2(s64) = G_OR %0, %1
    %x0 = COPY %2(s64)
...

---
# 64-bit G_OR on vector registers.
name:            or_v2s32_fpr
legalized:       true
regBankSelected: true
#
registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: fpr }

# The actual OR does not matter as long as it is operating
# on 64-bit width vector.
body:             |
  bb.0:
    liveins: %d0, %d1

    ; CHECK-LABEL: name: or_v2s32_fpr
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
    ; CHECK: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY]], [[COPY1]]
    ; CHECK: %d0 = COPY [[ORRv8i8_]]
      %0(<2 x s32>) = COPY %d0
      %1(<2 x s32>) = COPY %d1
      %2(<2 x s32>) = G_OR %0, %1
      %d0 = COPY %2(<2 x s32>)
...

---
# Same as add_s32_gpr, for G_AND operations.
name:            and_s32_gpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

body:             |
  bb.0:
    liveins: %w0, %w1

    ; CHECK-LABEL: name: and_s32_gpr
    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
    ; CHECK: [[ANDWrr:%[0-9]+]]:gpr32 = ANDWrr [[COPY]], [[COPY1]]
    ; CHECK: %w0 = COPY [[ANDWrr]]
    %0(s32) = COPY %w0
    %1(s32) = COPY %w1
    %2(s32) = G_AND %0, %1
    %w0 = COPY %2(s32)
...

---
# Same as add_s64_gpr, for G_AND operations.
name:            and_s64_gpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

body:             |
  bb.0:
    liveins: %x0, %x1

    ; CHECK-LABEL: name: and_s64_gpr
    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
    ; CHECK: [[ANDXrr:%[0-9]+]]:gpr64 = ANDXrr [[COPY]], [[COPY1]]
    ; CHECK: %x0 = COPY [[ANDXrr]]
    %0(s64) = COPY %x0
    %1(s64) = COPY %x1
    %2(s64) = G_AND %0, %1
    %x0 = COPY %2(s64)
...

---
# Same as add_s32_gpr, for G_SHL operations.
name:            shl_s32_gpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

body:             |
  bb.0:
    liveins: %w0, %w1

    ; CHECK-LABEL: name: shl_s32_gpr
    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
    ; CHECK: [[LSLVWr:%[0-9]+]]:gpr32 = LSLVWr [[COPY]], [[COPY1]]
    ; CHECK: %w0 = COPY [[LSLVWr]]
    %0(s32) = COPY %w0
    %1(s32) = COPY %w1
    %2(s32) = G_SHL %0, %1
    %w0 = COPY %2(s32)
...

---
# Same as add_s64_gpr, for G_SHL operations.
name:            shl_s64_gpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

body:             |
  bb.0:
    liveins: %x0, %x1

    ; CHECK-LABEL: name: shl_s64_gpr
    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
    ; CHECK: [[LSLVXr:%[0-9]+]]:gpr64 = LSLVXr [[COPY]], [[COPY1]]
    ; CHECK: %x0 = COPY [[LSLVXr]]
    %0(s64) = COPY %x0
    %1(s64) = COPY %x1
    %2(s64) = G_SHL %0, %1
    %x0 = COPY %2(s64)
...

---
# Same as add_s32_gpr, for G_LSHR operations.
name:            lshr_s32_gpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

body:             |
  bb.0:
    liveins: %w0, %w1

    ; CHECK-LABEL: name: lshr_s32_gpr
    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
    ; CHECK: [[LSRVWr:%[0-9]+]]:gpr32 = LSRVWr [[COPY]], [[COPY1]]
    ; CHECK: %w0 = COPY [[LSRVWr]]
    %0(s32) = COPY %w0
    %1(s32) = COPY %w1
    %2(s32) = G_LSHR %0, %1
    %w0 = COPY %2(s32)
...

---
# Same as add_s64_gpr, for G_LSHR operations.
name:            lshr_s64_gpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

body:             |
  bb.0:
    liveins: %x0, %x1

    ; CHECK-LABEL: name: lshr_s64_gpr
    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
    ; CHECK: [[LSRVXr:%[0-9]+]]:gpr64 = LSRVXr [[COPY]], [[COPY1]]
    ; CHECK: %x0 = COPY [[LSRVXr]]
    %0(s64) = COPY %x0
    %1(s64) = COPY %x1
    %2(s64) = G_LSHR %0, %1
    %x0 = COPY %2(s64)
...

---
# Same as add_s32_gpr, for G_ASHR operations.
name:            ashr_s32_gpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

body:             |
  bb.0:
    liveins: %w0, %w1

    ; CHECK-LABEL: name: ashr_s32_gpr
    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
    ; CHECK: [[ASRVWr:%[0-9]+]]:gpr32 = ASRVWr [[COPY]], [[COPY1]]
    ; CHECK: %w0 = COPY [[ASRVWr]]
    %0(s32) = COPY %w0
    %1(s32) = COPY %w1
    %2(s32) = G_ASHR %0, %1
    %w0 = COPY %2(s32)
...

---
# Same as add_s64_gpr, for G_ASHR operations.
name:            ashr_s64_gpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

body:             |
  bb.0:
    liveins: %x0, %x1

    ; CHECK-LABEL: name: ashr_s64_gpr
    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
    ; CHECK: [[ASRVXr:%[0-9]+]]:gpr64 = ASRVXr [[COPY]], [[COPY1]]
    ; CHECK: %x0 = COPY [[ASRVXr]]
    %0(s64) = COPY %x0
    %1(s64) = COPY %x1
    %2(s64) = G_ASHR %0, %1
    %x0 = COPY %2(s64)
...

---
# Check that we select s32 GPR G_MUL. This is trickier than other binops because
# there is only MADDWrrr, and we have to use the WZR physreg.
name:            mul_s32_gpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

body:             |
  bb.0:
    liveins: %w0, %w1

    ; CHECK-LABEL: name: mul_s32_gpr
    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
    ; CHECK: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY]], [[COPY1]], %wzr
    ; CHECK: %w0 = COPY [[MADDWrrr]]
    %0(s32) = COPY %w0
    %1(s32) = COPY %w1
    %2(s32) = G_MUL %0, %1
    %w0 = COPY %2(s32)
...

---
# Same as mul_s32_gpr for the s64 type.
name:            mul_s64_gpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

body:             |
  bb.0:
    liveins: %x0, %x1

    ; CHECK-LABEL: name: mul_s64_gpr
    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
    ; CHECK: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[COPY]], [[COPY1]], %xzr
    ; CHECK: %x0 = COPY [[MADDXrrr]]
    %0(s64) = COPY %x0
    %1(s64) = COPY %x1
    %2(s64) = G_MUL %0, %1
    %x0 = COPY %2(s64)
...

---
# Same as mul_s32_gpr for the s64 type.
name:            mulh_s64_gpr
legalized:       true
regBankSelected: true


body:             |
  bb.0:
    liveins: %x0, %x1

    ; CHECK-LABEL: name: mulh_s64_gpr
    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
    ; CHECK: [[SMULHrr:%[0-9]+]]:gpr64 = SMULHrr [[COPY]], [[COPY1]]
    ; CHECK: [[UMULHrr:%[0-9]+]]:gpr64 = UMULHrr [[COPY]], [[COPY1]]
    ; CHECK: %x0 = COPY [[SMULHrr]]
    ; CHECK: %x0 = COPY [[UMULHrr]]
    %0:gpr(s64) = COPY %x0
    %1:gpr(s64) = COPY %x1
    %2:gpr(s64) = G_SMULH %0, %1
    %3:gpr(s64) = G_UMULH %0, %1
    %x0 = COPY %2(s64)
    %x0 = COPY %3(s64)
...

---
# Same as add_s32_gpr, for G_SDIV operations.
name:            sdiv_s32_gpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

body:             |
  bb.0:
    liveins: %w0, %w1

    ; CHECK-LABEL: name: sdiv_s32_gpr
    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
    ; CHECK: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[COPY]], [[COPY1]]
    ; CHECK: %w0 = COPY [[SDIVWr]]
    %0(s32) = COPY %w0
    %1(s32) = COPY %w1
    %2(s32) = G_SDIV %0, %1
    %w0 = COPY %2(s32)
...

---
# Same as add_s64_gpr, for G_SDIV operations.
name:            sdiv_s64_gpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

body:             |
  bb.0:
    liveins: %x0, %x1

    ; CHECK-LABEL: name: sdiv_s64_gpr
    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
    ; CHECK: [[SDIVXr:%[0-9]+]]:gpr64 = SDIVXr [[COPY]], [[COPY1]]
    ; CHECK: %x0 = COPY [[SDIVXr]]
    %0(s64) = COPY %x0
    %1(s64) = COPY %x1
    %2(s64) = G_SDIV %0, %1
    %x0 = COPY %2(s64)
...

---
# Same as add_s32_gpr, for G_UDIV operations.
name:            udiv_s32_gpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

body:             |
  bb.0:
    liveins: %w0, %w1

    ; CHECK-LABEL: name: udiv_s32_gpr
    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
    ; CHECK: [[UDIVWr:%[0-9]+]]:gpr32 = UDIVWr [[COPY]], [[COPY1]]
    ; CHECK: %w0 = COPY [[UDIVWr]]
    %0(s32) = COPY %w0
    %1(s32) = COPY %w1
    %2(s32) = G_UDIV %0, %1
    %w0 = COPY %2(s32)
...

---
# Same as add_s64_gpr, for G_UDIV operations.
name:            udiv_s64_gpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

body:             |
  bb.0:
    liveins: %x0, %x1

    ; CHECK-LABEL: name: udiv_s64_gpr
    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
    ; CHECK: [[UDIVXr:%[0-9]+]]:gpr64 = UDIVXr [[COPY]], [[COPY1]]
    ; CHECK: %x0 = COPY [[UDIVXr]]
    %0(s64) = COPY %x0
    %1(s64) = COPY %x1
    %2(s64) = G_UDIV %0, %1
    %x0 = COPY %2(s64)
...

---
# Check that we select a s32 FPR G_FADD into FADDSrr.
name:            fadd_s32_fpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: fpr }

body:             |
  bb.0:
    liveins: %s0, %s1

    ; CHECK-LABEL: name: fadd_s32_fpr
    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY %s1
    ; CHECK: [[FADDSrr:%[0-9]+]]:fpr32 = FADDSrr [[COPY]], [[COPY1]]
    ; CHECK: %s0 = COPY [[FADDSrr]]
    %0(s32) = COPY %s0
    %1(s32) = COPY %s1
    %2(s32) = G_FADD %0, %1
    %s0 = COPY %2(s32)
...

---
name:            fadd_s64_fpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: fpr }

body:             |
  bb.0:
    liveins: %d0, %d1

    ; CHECK-LABEL: name: fadd_s64_fpr
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
    ; CHECK: [[FADDDrr:%[0-9]+]]:fpr64 = FADDDrr [[COPY]], [[COPY1]]
    ; CHECK: %d0 = COPY [[FADDDrr]]
    %0(s64) = COPY %d0
    %1(s64) = COPY %d1
    %2(s64) = G_FADD %0, %1
    %d0 = COPY %2(s64)
...

---
name:            fsub_s32_fpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: fpr }

body:             |
  bb.0:
    liveins: %s0, %s1

    ; CHECK-LABEL: name: fsub_s32_fpr
    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY %s1
    ; CHECK: [[FSUBSrr:%[0-9]+]]:fpr32 = FSUBSrr [[COPY]], [[COPY1]]
    ; CHECK: %s0 = COPY [[FSUBSrr]]
    %0(s32) = COPY %s0
    %1(s32) = COPY %s1
    %2(s32) = G_FSUB %0, %1
    %s0 = COPY %2(s32)
...

---
name:            fsub_s64_fpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: fpr }

body:             |
  bb.0:
    liveins: %d0, %d1

    ; CHECK-LABEL: name: fsub_s64_fpr
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
    ; CHECK: [[FSUBDrr:%[0-9]+]]:fpr64 = FSUBDrr [[COPY]], [[COPY1]]
    ; CHECK: %d0 = COPY [[FSUBDrr]]
    %0(s64) = COPY %d0
    %1(s64) = COPY %d1
    %2(s64) = G_FSUB %0, %1
    %d0 = COPY %2(s64)
...

---
name:            fmul_s32_fpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: fpr }

body:             |
  bb.0:
    liveins: %s0, %s1

    ; CHECK-LABEL: name: fmul_s32_fpr
    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY %s1
    ; CHECK: [[FMULSrr:%[0-9]+]]:fpr32 = FMULSrr [[COPY]], [[COPY1]]
    ; CHECK: %s0 = COPY [[FMULSrr]]
    %0(s32) = COPY %s0
    %1(s32) = COPY %s1
    %2(s32) = G_FMUL %0, %1
    %s0 = COPY %2(s32)
...

---
name:            fmul_s64_fpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: fpr }

body:             |
  bb.0:
    liveins: %d0, %d1

    ; CHECK-LABEL: name: fmul_s64_fpr
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
    ; CHECK: [[FMULDrr:%[0-9]+]]:fpr64 = FMULDrr [[COPY]], [[COPY1]]
    ; CHECK: %d0 = COPY [[FMULDrr]]
    %0(s64) = COPY %d0
    %1(s64) = COPY %d1
    %2(s64) = G_FMUL %0, %1
    %d0 = COPY %2(s64)
...

---
name:            fdiv_s32_fpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: fpr }

body:             |
  bb.0:
    liveins: %s0, %s1

    ; CHECK-LABEL: name: fdiv_s32_fpr
    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY %s1
    ; CHECK: [[FDIVSrr:%[0-9]+]]:fpr32 = FDIVSrr [[COPY]], [[COPY1]]
    ; CHECK: %s0 = COPY [[FDIVSrr]]
    %0(s32) = COPY %s0
    %1(s32) = COPY %s1
    %2(s32) = G_FDIV %0, %1
    %s0 = COPY %2(s32)
...

---
name:            fdiv_s64_fpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: fpr }
  - { id: 1, class: fpr }
  - { id: 2, class: fpr }

body:             |
  bb.0:
    liveins: %d0, %d1

    ; CHECK-LABEL: name: fdiv_s64_fpr
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
    ; CHECK: [[FDIVDrr:%[0-9]+]]:fpr64 = FDIVDrr [[COPY]], [[COPY1]]
    ; CHECK: %d0 = COPY [[FDIVDrr]]
    %0(s64) = COPY %d0
    %1(s64) = COPY %d1
    %2(s64) = G_FDIV %0, %1
    %d0 = COPY %2(s64)
...