# RUN: llc -march=amdgcn -verify-machineinstrs -start-before si-shrink-instructions -stop-before si-insert-skips -o - %s | FileCheck -check-prefix=GCN %s

# GCN-LABEL: name: subbrev{{$}}
# GCN:       V_SUBBREV_U32_e64 0, undef %vgpr0, killed %vcc, implicit %exec

---
name:            subbrev
tracksRegLiveness: true
registers:
  - { id: 0, class: vgpr_32 }
  - { id: 1, class: vgpr_32 }
  - { id: 2, class: vgpr_32 }
  - { id: 3, class: sreg_64 }
  - { id: 4, class: vgpr_32 }
  - { id: 5, class: sreg_64 }
body:             |
  bb.0:

    %0 = IMPLICIT_DEF
    %1 = IMPLICIT_DEF
    %2 = IMPLICIT_DEF
    %3 = V_CMP_GT_U32_e64 %0, %1, implicit %exec
    %4, %5 = V_SUBBREV_U32_e64 0, %0, %3, implicit %exec
    S_ENDPGM

...

# GCN-LABEL: name: subb{{$}}
# GCN:       V_SUBB_U32_e64 undef %vgpr0, 0, killed %vcc, implicit %exec

---
name:            subb
tracksRegLiveness: true
registers:
  - { id: 0, class: vgpr_32 }
  - { id: 1, class: vgpr_32 }
  - { id: 2, class: vgpr_32 }
  - { id: 3, class: sreg_64 }
  - { id: 4, class: vgpr_32 }
  - { id: 5, class: sreg_64 }
body:             |
  bb.0:

    %0 = IMPLICIT_DEF
    %1 = IMPLICIT_DEF
    %2 = IMPLICIT_DEF
    %3 = V_CMP_GT_U32_e64 %0, %1, implicit %exec
    %4, %5 = V_SUBB_U32_e64 %0, 0, %3, implicit %exec
    S_ENDPGM

...

# GCN-LABEL: name: addc{{$}}
# GCN:       V_ADDC_U32_e32 0, undef %vgpr0, implicit-def %vcc, implicit killed %vcc, implicit %exec

---
name:            addc
tracksRegLiveness: true
registers:
  - { id: 0, class: vgpr_32 }
  - { id: 1, class: vgpr_32 }
  - { id: 2, class: vgpr_32 }
  - { id: 3, class: sreg_64 }
  - { id: 4, class: vgpr_32 }
  - { id: 5, class: sreg_64 }
body:             |
  bb.0:

    %0 = IMPLICIT_DEF
    %1 = IMPLICIT_DEF
    %2 = IMPLICIT_DEF
    %3 = V_CMP_GT_U32_e64 %0, %1, implicit %exec
    %4, %5 = V_ADDC_U32_e64 0, %0, %3, implicit %exec
    S_ENDPGM

...

# GCN-LABEL: name: addc2{{$}}
# GCN:       V_ADDC_U32_e32 0, undef %vgpr0, implicit-def %vcc, implicit killed %vcc, implicit %exec

---
name:            addc2
tracksRegLiveness: true
registers:
  - { id: 0, class: vgpr_32 }
  - { id: 1, class: vgpr_32 }
  - { id: 2, class: vgpr_32 }
  - { id: 3, class: sreg_64 }
  - { id: 4, class: vgpr_32 }
  - { id: 5, class: sreg_64 }
body:             |
  bb.0:

    %0 = IMPLICIT_DEF
    %1 = IMPLICIT_DEF
    %2 = IMPLICIT_DEF
    %3 = V_CMP_GT_U32_e64 %0, %1, implicit %exec
    %4, %5 = V_ADDC_U32_e64 %0, 0, %3, implicit %exec
    S_ENDPGM

...