| //===- PPCScheduleA2.td - PPC A2 Scheduling Definitions --*- tablegen -*-===// |
| // |
| // The LLVM Compiler Infrastructure |
| // |
| // This file is distributed under the University of Illinois Open Source |
| // License. See LICENSE.TXT for details. |
| // |
| //===----------------------------------------------------------------------===// |
| |
| // Primary reference: |
| // A2 Processor User's Manual. |
| // IBM (as updated in) 2010. |
| |
| //===----------------------------------------------------------------------===// |
| // Functional units on the PowerPC A2 chip sets |
| // |
| def IU0to3_0 : FuncUnit; // Fetch unit 1 to 4 slot 1 |
| def IU0to3_1 : FuncUnit; // Fetch unit 1 to 4 slot 2 |
| def IU0to3_2 : FuncUnit; // Fetch unit 1 to 4 slot 3 |
| def IU0to3_3 : FuncUnit; // Fetch unit 1 to 4 slot 4 |
| def IU4_0 : FuncUnit; // Instruction buffer slot 1 |
| def IU4_1 : FuncUnit; // Instruction buffer slot 2 |
| def IU4_2 : FuncUnit; // Instruction buffer slot 3 |
| def IU4_3 : FuncUnit; // Instruction buffer slot 4 |
| def IU4_4 : FuncUnit; // Instruction buffer slot 5 |
| def IU4_5 : FuncUnit; // Instruction buffer slot 6 |
| def IU4_6 : FuncUnit; // Instruction buffer slot 7 |
| def IU4_7 : FuncUnit; // Instruction buffer slot 8 |
| def IU5 : FuncUnit; // Dependency resolution |
| def IU6 : FuncUnit; // Instruction issue |
| def RF0 : FuncUnit; |
| def XRF1 : FuncUnit; |
| def XEX1 : FuncUnit; // Execution stage 1 for the XU pipeline |
| def XEX2 : FuncUnit; // Execution stage 2 for the XU pipeline |
| def XEX3 : FuncUnit; // Execution stage 3 for the XU pipeline |
| def XEX4 : FuncUnit; // Execution stage 4 for the XU pipeline |
| def XEX5 : FuncUnit; // Execution stage 5 for the XU pipeline |
| def XEX6 : FuncUnit; // Execution stage 6 for the XU pipeline |
| def FRF1 : FuncUnit; |
| def FEX1 : FuncUnit; // Execution stage 1 for the FU pipeline |
| def FEX2 : FuncUnit; // Execution stage 2 for the FU pipeline |
| def FEX3 : FuncUnit; // Execution stage 3 for the FU pipeline |
| def FEX4 : FuncUnit; // Execution stage 4 for the FU pipeline |
| def FEX5 : FuncUnit; // Execution stage 5 for the FU pipeline |
| def FEX6 : FuncUnit; // Execution stage 6 for the FU pipeline |
| |
| def CR_Bypass : Bypass; // The bypass for condition regs. |
| //def GPR_Bypass : Bypass; // The bypass for general-purpose regs. |
| //def FPR_Bypass : Bypass; // The bypass for floating-point regs. |
| |
| // |
| // This file defines the itinerary class data for the PPC A2 processor. |
| // |
| //===----------------------------------------------------------------------===// |
| |
| |
| def PPCA2Itineraries : ProcessorItineraries< |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3, |
| IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7, |
| IU5, IU6, RF0, XRF1, XEX1, XEX2, XEX3, XEX4, XEX5, XEX6, |
| FRF1, FEX1, FEX2, FEX3, FEX4, FEX5, FEX6], |
| [CR_Bypass, GPR_Bypass, FPR_Bypass], [ |
| InstrItinData<IntGeneral , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [10, 7, 7], |
| [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, |
| InstrItinData<IntCompare , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [10, 7, 7], |
| [CR_Bypass, GPR_Bypass, GPR_Bypass]>, |
| InstrItinData<IntDivW , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<38, [XEX6]>], |
| [53, 7, 7], |
| [NoBypass, GPR_Bypass, GPR_Bypass]>, |
| InstrItinData<IntMFFS , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [10, 7, 7], |
| [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, |
| InstrItinData<IntMTFSB0 , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [10, 7, 7], |
| [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, |
| InstrItinData<IntMulHW , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [14, 7, 7], |
| [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, |
| InstrItinData<IntMulHWU , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [14, 7, 7], |
| [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, |
| InstrItinData<IntMulLI , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [15, 7, 7], |
| [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, |
| InstrItinData<IntRotate , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [10, 7, 7], |
| [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, |
| InstrItinData<IntShift , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [10, 7, 7], |
| [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, |
| InstrItinData<IntTrapW , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [10, 7, 7], |
| [GPR_Bypass, GPR_Bypass]>, |
| InstrItinData<BrB , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [15, 7, 7], |
| [NoBypass, GPR_Bypass]>, |
| InstrItinData<BrCR , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [10, 7, 7], |
| [CR_Bypass, CR_Bypass, CR_Bypass]>, |
| InstrItinData<BrMCR , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [10, 7, 7], |
| [CR_Bypass, CR_Bypass, CR_Bypass]>, |
| InstrItinData<BrMCRX , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [10, 7, 7], |
| [CR_Bypass, GPR_Bypass, GPR_Bypass]>, |
| InstrItinData<LdStDCBA , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [13, 11], |
| [NoBypass, GPR_Bypass]>, |
| InstrItinData<LdStDCBF , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [13, 11], |
| [NoBypass, GPR_Bypass]>, |
| InstrItinData<LdStDCBI , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [13, 11], |
| [NoBypass, GPR_Bypass]>, |
| InstrItinData<LdStLoad , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [14, 7], |
| [GPR_Bypass, GPR_Bypass]>, |
| InstrItinData<LdStStore , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [13, 7], |
| [GPR_Bypass, GPR_Bypass]>, |
| InstrItinData<LdStICBI , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [14, 7], |
| [NoBypass, GPR_Bypass]>, |
| InstrItinData<LdStUX , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [14, 7, 7], |
| [NoBypass, FPR_Bypass, FPR_Bypass]>, |
| InstrItinData<LdStLFD , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [14, 7, 7], |
| [FPR_Bypass, GPR_Bypass, GPR_Bypass]>, |
| InstrItinData<LdStLFDU , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [14, 7, 7], |
| [FPR_Bypass, GPR_Bypass, GPR_Bypass]>, |
| InstrItinData<LdStLHA , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [14, 7], |
| [NoBypass, GPR_Bypass]>, |
| InstrItinData<LdStLMW , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [14, 7], |
| [NoBypass, GPR_Bypass]>, |
| InstrItinData<LdStLWARX , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<13, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [26, 7], |
| [NoBypass, GPR_Bypass]>, |
| InstrItinData<LdStSTD , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [13, 7], |
| [GPR_Bypass, GPR_Bypass]>, |
| InstrItinData<LdStSTDCX , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<13, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [26, 7], |
| [NoBypass, GPR_Bypass]>, |
| InstrItinData<LdStSTD , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [13, 7], |
| [GPR_Bypass, GPR_Bypass]>, |
| InstrItinData<LdStSTDCX , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<13, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [26, 7], |
| [NoBypass, GPR_Bypass]>, |
| InstrItinData<LdStSTWCX , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<13, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [26, 7], |
| [NoBypass, GPR_Bypass]>, |
| InstrItinData<LdStSync , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<12, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>]>, |
| InstrItinData<SprISYNC , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>]>, |
| InstrItinData<SprMFSR , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [15, 7], |
| [GPR_Bypass, NoBypass]>, |
| InstrItinData<SprMTMSR , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [15, 7], |
| [NoBypass, GPR_Bypass]>, |
| InstrItinData<SprMTSR , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [15, 7], |
| [NoBypass, GPR_Bypass]>, |
| InstrItinData<SprTLBSYNC , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>]>, |
| InstrItinData<SprMFCR , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [10, 7], |
| [GPR_Bypass, CR_Bypass]>, |
| InstrItinData<SprMFMSR , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [15, 7], |
| [GPR_Bypass, NoBypass]>, |
| InstrItinData<SprMFSPR , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [15, 7], |
| [NoBypass, GPR_Bypass]>, |
| InstrItinData<SprMFTB , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>], |
| [29, 7], |
| [NoBypass, GPR_Bypass]>, |
| InstrItinData<SprMTSPR , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], |
| [15, 7], |
| [NoBypass, GPR_Bypass]>, |
| InstrItinData<SprMTSRIN , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>], |
| [29, 7], |
| [NoBypass, GPR_Bypass]>, |
| InstrItinData<SprRFI , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>], |
| [29, 7], |
| [NoBypass, GPR_Bypass]>, |
| InstrItinData<SprSC , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, |
| InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, |
| InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, |
| InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>], |
| [29, 7], |
| [NoBypass, GPR_Bypass]>, |
| InstrItinData<FPGeneral , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [FRF1]>, |
| InstrStage<1, [FEX1]>, InstrStage<1, [FEX2]>, |
| InstrStage<1, [FEX3]>, InstrStage<1, [FEX4]>, |
| InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>], |
| [15, 7, 7], |
| [FPR_Bypass, FPR_Bypass, FPR_Bypass]>, |
| InstrItinData<FPCompare , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [FRF1]>, |
| InstrStage<1, [FEX1]>, InstrStage<1, [FEX2]>, |
| InstrStage<1, [FEX3]>, InstrStage<1, [FEX4]>, |
| InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>], |
| [13, 7, 7], |
| [CR_Bypass, FPR_Bypass, FPR_Bypass]>, |
| InstrItinData<FPDivD , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<71, [FRF1], 0>, |
| InstrStage<71, [FEX1], 0>, |
| InstrStage<71, [FEX2], 0>, |
| InstrStage<71, [FEX3], 0>, |
| InstrStage<71, [FEX4], 0>, |
| InstrStage<71, [FEX5], 0>, |
| InstrStage<71, [FEX6]>], |
| [86, 7, 7], |
| [NoBypass, FPR_Bypass, FPR_Bypass]>, |
| InstrItinData<FPDivS , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<58, [FRF1], 0>, |
| InstrStage<58, [FEX1], 0>, |
| InstrStage<58, [FEX2], 0>, |
| InstrStage<58, [FEX3], 0>, |
| InstrStage<58, [FEX4], 0>, |
| InstrStage<58, [FEX5], 0>, |
| InstrStage<58, [FEX6]>], |
| [73, 7, 7], |
| [NoBypass, FPR_Bypass, FPR_Bypass]>, |
| InstrItinData<FPSqrt , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<68, [FRF1], 0>, |
| InstrStage<68, [FEX1], 0>, |
| InstrStage<68, [FEX2], 0>, |
| InstrStage<68, [FEX3], 0>, |
| InstrStage<68, [FEX4], 0>, |
| InstrStage<68, [FEX5], 0>, |
| InstrStage<68, [FEX6]>], |
| [86, 7], // FIXME: should be [86, 7] for double |
| // and [82, 7] for single. Likewise, |
| // the FEX? cycle count should be 68 |
| // for double and 64 for single. |
| [NoBypass, FPR_Bypass]>, |
| InstrItinData<FPFused , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [FRF1]>, |
| InstrStage<1, [FEX1]>, InstrStage<1, [FEX2]>, |
| InstrStage<1, [FEX3]>, InstrStage<1, [FEX4]>, |
| InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>], |
| [15, 7, 7, 7], |
| [FPR_Bypass, FPR_Bypass, FPR_Bypass, FPR_Bypass]>, |
| InstrItinData<FPRes , [InstrStage<4, |
| [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, |
| InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
| IU4_4, IU4_5, IU4_6, IU4_7]>, |
| InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, |
| InstrStage<1, [RF0]>, InstrStage<1, [FRF1]>, |
| InstrStage<1, [FEX1]>, InstrStage<1, [FEX2]>, |
| InstrStage<1, [FEX3]>, InstrStage<1, [FEX4]>, |
| InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>], |
| [15, 7], |
| [FPR_Bypass, FPR_Bypass]> |
| ]>; |
