commit fcf88f08a21221c9fcb0fa27a7895ed3a9b30fd9
author Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> Wed Feb 13 11:02:42 2019 +0000
committer Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> Wed Feb 13 11:02:42 2019 +0000
tree f3100be777f59bb935d0340c5c7ced4d5e415ed7
parent b902ab171c3c46f61e4485717b046609956f386b

[MCA][Scheduler] Use latency information to further classify busy instructions.

This patch introduces a new instruction stage named 'IS_PENDING'.
An instruction transitions from the IS_DISPATCHED to the IS_PENDING stage if
input registers are not available, but their latency is known.

This patch also adds a new set of instructions named 'PendingSet' to class
Scheduler. The idea is that the PendingSet will only contain instructions that
have reached the IS_PENDING stage.
By construction, an instruction in the PendingSet is only dependent on
instructions that have already reached the execution stage. The plan is to use
this knowledge to identify bottlenecks caused by data dependencies (see
PR37494).

Differential Revision: https://reviews.llvm.org/D58066


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353937 91177308-0d34-0410-b5e6-96231b3b80d8