test/CodeGen/Mips/longbranch/branch-limits-msa.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=mips64-mti-linux-gnu -mcpu=mips64r5 -mattr=+fp64,+msa %s -o - -start-before mips-delay-slot-filler -stop-after mips-branch-expansion | FileCheck %s --check-prefix=MSA
# RUN: llc -mtriple=mips64-mti-linux-gnu -mcpu=mips64r5 -mattr=+fp64,+msa %s -o - -start-before mips-delay-slot-filler -stop-after mips-branch-expansion -relocation-model=pic | FileCheck %s --check-prefix=PIC

# Test the long branch expansion of various branches



--- |

  define i32 @_Z4bz_8Dv16_a(i64 inreg %d.coerce0, i64 inreg %d.coerce1) {
    entry:
    %0 = bitcast i64 %d.coerce0 to <8 x i8>
    %d.0.vec.expand = shufflevector <8 x i8> %0, <8 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
    %1 = bitcast i64 %d.coerce1 to <8 x i8>
    %d.8.vec.expand = shufflevector <8 x i8> %1, <8 x i8> undef, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
    %d.8.vecblend = shufflevector <16 x i8> %d.8.vec.expand, <16 x i8> %d.0.vec.expand, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
    %2 = tail call i32 @llvm.mips.bz.b(<16 x i8> %d.8.vecblend)
    %tobool = icmp eq i32 %2, 0
    br i1 %tobool, label %return, label %if.then

    if.then:
    tail call void asm sideeffect ".space 810680", "~{$1}"()
    br label %return

    return:
    %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ]
    ret i32 %retval.0
  }

  declare i32 @llvm.mips.bz.b(<16 x i8>)

  define i32 @_Z5bz_16Dv8_s(i64 inreg %d.coerce0, i64 inreg %d.coerce1) {
    entry:
    %0 = bitcast i64 %d.coerce0 to <4 x i16>
    %d.0.vec.expand = shufflevector <4 x i16> %0, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
    %1 = bitcast i64 %d.coerce1 to <4 x i16>
    %d.8.vec.expand = shufflevector <4 x i16> %1, <4 x i16> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3>
    %d.8.vecblend = shufflevector <8 x i16> %d.8.vec.expand, <8 x i16> %d.0.vec.expand, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
    %2 = tail call i32 @llvm.mips.bz.h(<8 x i16> %d.8.vecblend)
    %tobool = icmp eq i32 %2, 0
    br i1 %tobool, label %return, label %if.then

    if.then:
    tail call void asm sideeffect ".space 810680", "~{$1}"()
    br label %return

    return:
    %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ]
    ret i32 %retval.0
  }

  declare i32 @llvm.mips.bz.h(<8 x i16>)

  define i32 @_Z5bz_32Dv4_i(i64 inreg %d.coerce0, i64 inreg %d.coerce1) {
    entry:
    %0 = bitcast i64 %d.coerce0 to <2 x i32>
    %d.0.vec.expand = shufflevector <2 x i32> %0, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
    %1 = bitcast i64 %d.coerce1 to <2 x i32>
    %d.8.vec.expand = shufflevector <2 x i32> %1, <2 x i32> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
    %d.8.vecblend = shufflevector <4 x i32> %d.8.vec.expand, <4 x i32> %d.0.vec.expand, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
    %2 = tail call i32 @llvm.mips.bz.w(<4 x i32> %d.8.vecblend)
    %tobool = icmp eq i32 %2, 0
    br i1 %tobool, label %return, label %if.then

    if.then:
    tail call void asm sideeffect ".space 810680", "~{$1}"()
    br label %return

    return:
    %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ]
    ret i32 %retval.0
  }

  declare i32 @llvm.mips.bz.w(<4 x i32>)

  define i32 @_Z5bz_64Dv2_x(i64 inreg %d.coerce0, i64 inreg %d.coerce1) {
    entry:
    %d.0.vec.insert = insertelement <2 x i64> undef, i64 %d.coerce0, i32 0
    %d.8.vec.insert = insertelement <2 x i64> %d.0.vec.insert, i64 %d.coerce1, i32 1
    %0 = tail call i32 @llvm.mips.bz.d(<2 x i64> %d.8.vec.insert)
    %tobool = icmp eq i32 %0, 0
    br i1 %tobool, label %return, label %if.then

    if.then:
    tail call void asm sideeffect ".space 810680", "~{$1}"()
    br label %return

    return:
    %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ]
    ret i32 %retval.0
  }

  declare i32 @llvm.mips.bz.d(<2 x i64>)

  define i32 @_Z5bz_64_vDv2_x(i64 inreg %d.coerce0, i64 inreg %d.coerce1) {
    entry:
    %d.0.vec.insert = insertelement <2 x i64> undef, i64 %d.coerce0, i32 0
    %d.8.vec.insert = insertelement <2 x i64> %d.0.vec.insert, i64 %d.coerce1, i32 1
    %d.16.vec.insert = bitcast <2 x i64> %d.8.vec.insert to <16 x i8>
    %0 = tail call i32 @llvm.mips.bz.v(<16 x i8> %d.16.vec.insert)
    %tobool = icmp eq i32 %0, 0
    br i1 %tobool, label %return, label %if.then

    if.then:
    tail call void asm sideeffect ".space 810680", "~{$1}"()
    br label %return

    return:
    %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ]
    ret i32 %retval.0
  }

  declare i32 @llvm.mips.bz.v(<16 x i8>)

  define i32 @_Z5bnz_8Dv16_a(i64 inreg %d.coerce0, i64 inreg %d.coerce1) {
    entry:
    %0 = bitcast i64 %d.coerce0 to <8 x i8>
    %d.0.vec.expand = shufflevector <8 x i8> %0, <8 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
    %1 = bitcast i64 %d.coerce1 to <8 x i8>
    %d.8.vec.expand = shufflevector <8 x i8> %1, <8 x i8> undef, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
    %d.8.vecblend = shufflevector <16 x i8> %d.8.vec.expand, <16 x i8> %d.0.vec.expand, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
    %2 = tail call i32 @llvm.mips.bnz.b(<16 x i8> %d.8.vecblend)
    %tobool = icmp eq i32 %2, 0
    br i1 %tobool, label %return, label %if.then

    if.then:
    tail call void asm sideeffect ".space 810680", "~{$1}"()
    br label %return

    return:
    %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ]
    ret i32 %retval.0
  }

  declare i32 @llvm.mips.bnz.b(<16 x i8>)

  define i32 @_Z6bnz_16Dv8_s(i64 inreg %d.coerce0, i64 inreg %d.coerce1) {
    entry:
    %0 = bitcast i64 %d.coerce0 to <4 x i16>
    %d.0.vec.expand = shufflevector <4 x i16> %0, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
    %1 = bitcast i64 %d.coerce1 to <4 x i16>
    %d.8.vec.expand = shufflevector <4 x i16> %1, <4 x i16> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3>
    %d.8.vecblend = shufflevector <8 x i16> %d.8.vec.expand, <8 x i16> %d.0.vec.expand, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
    %2 = tail call i32 @llvm.mips.bnz.h(<8 x i16> %d.8.vecblend)
    %tobool = icmp eq i32 %2, 0
    br i1 %tobool, label %return, label %if.then

    if.then:
    tail call void asm sideeffect ".space 810680", "~{$1}"()
    br label %return

    return:
    %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ]
    ret i32 %retval.0
  }

  declare i32 @llvm.mips.bnz.h(<8 x i16>)

  define i32 @_Z6bnz_32Dv4_i(i64 inreg %d.coerce0, i64 inreg %d.coerce1) {
    entry:
    %0 = bitcast i64 %d.coerce0 to <2 x i32>
    %d.0.vec.expand = shufflevector <2 x i32> %0, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
    %1 = bitcast i64 %d.coerce1 to <2 x i32>
    %d.8.vec.expand = shufflevector <2 x i32> %1, <2 x i32> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
    %d.8.vecblend = shufflevector <4 x i32> %d.8.vec.expand, <4 x i32> %d.0.vec.expand, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
    %2 = tail call i32 @llvm.mips.bnz.w(<4 x i32> %d.8.vecblend)
    %tobool = icmp eq i32 %2, 0
    br i1 %tobool, label %return, label %if.then

    if.then:
    tail call void asm sideeffect ".space 810680", "~{$1}"()
    br label %return

    return:
    %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ]
    ret i32 %retval.0
  }

  declare i32 @llvm.mips.bnz.w(<4 x i32>)

  define i32 @_Z6bnz_64Dv2_x(i64 inreg %d.coerce0, i64 inreg %d.coerce1) {
    entry:
    %d.0.vec.insert = insertelement <2 x i64> undef, i64 %d.coerce0, i32 0
    %d.8.vec.insert = insertelement <2 x i64> %d.0.vec.insert, i64 %d.coerce1, i32 1
    %0 = tail call i32 @llvm.mips.bnz.d(<2 x i64> %d.8.vec.insert)
    %tobool = icmp eq i32 %0, 0
    br i1 %tobool, label %return, label %if.then

    if.then:
    tail call void asm sideeffect ".space 810680", "~{$1}"()
    br label %return

    return:
    %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ]
    ret i32 %retval.0
  }

  declare i32 @llvm.mips.bnz.d(<2 x i64>)

  define i32 @_Z6bnz_64_vDv2_x(i64 inreg %d.coerce0, i64 inreg %d.coerce1) {
    entry:
    %d.0.vec.insert = insertelement <2 x i64> undef, i64 %d.coerce0, i32 0
    %d.8.vec.insert = insertelement <2 x i64> %d.0.vec.insert, i64 %d.coerce1, i32 1
    %d.16.vec.insert = bitcast <2 x i64> %d.8.vec.insert to <16 x i8>
    %0 = tail call i32 @llvm.mips.bnz.v(<16 x i8> %d.16.vec.insert)
    %tobool = icmp eq i32 %0, 0
    br i1 %tobool, label %return, label %if.then

    if.then:
    tail call void asm sideeffect ".space 810680", "~{$1}"()
    br label %return

    return:
    %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ]
    ret i32 %retval.0
  }

  declare i32 @llvm.mips.bnz.v(<16 x i8>)

...
---
name:            _Z4bz_8Dv16_a
alignment:       3
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
registers:
liveins:
  - { reg: '$a0_64', virtual-reg: '' }
  - { reg: '$a1_64', virtual-reg: '' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    1
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:
stack:
constants:
body:             |
  ; MSA-LABEL: name: _Z4bz_8Dv16_a
  ; MSA: bb.0.entry:
  ; MSA:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; MSA:   renamable $w0 = LDI_B 0
  ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
  ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
  ; MSA:   renamable $w0 = SHF_B killed renamable $w0, 27
  ; MSA:   renamable $w0 = SHF_W killed renamable $w0, 177
  ; MSA:   BNZ_B $w0, %bb.2, implicit-def $at {
  ; MSA:     NOP
  ; MSA:   }
  ; MSA: bb.1.entry:
  ; MSA:   successors: %bb.3(0x80000000)
  ; MSA:   J %bb.3, implicit-def $at {
  ; MSA:     NOP
  ; MSA:   }
  ; MSA: bb.2.if.then:
  ; MSA:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
  ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; MSA:     renamable $v0 = ADDiu $zero, 1
  ; MSA:   }
  ; MSA: bb.3:
  ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; MSA:     renamable $v0 = ADDiu $zero, 0
  ; MSA:   }
  ; PIC-LABEL: name: _Z4bz_8Dv16_a
  ; PIC: bb.0.entry:
  ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
  ; PIC:   renamable $w0 = LDI_B 0
  ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
  ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
  ; PIC:   renamable $w0 = SHF_B killed renamable $w0, 27
  ; PIC:   renamable $w0 = SHF_W killed renamable $w0, 177
  ; PIC:   BNZ_B $w0, %bb.3, implicit-def $at {
  ; PIC:     NOP
  ; PIC:   }
  ; PIC: bb.1.entry:
  ; PIC:   successors: %bb.2(0x80000000)
  ; PIC:   $sp_64 = DADDiu $sp_64, -16
  ; PIC:   SD $ra_64, $sp_64, 0
  ; PIC:   $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
  ; PIC:   $at_64 = DSLL $at_64, 16
  ; PIC:   BAL_BR %bb.2, implicit-def $ra {
  ; PIC:     $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
  ; PIC:   }
  ; PIC: bb.2.entry:
  ; PIC:   successors: %bb.4(0x80000000)
  ; PIC:   $at_64 = DADDu $ra_64, $at_64
  ; PIC:   $ra_64 = LD $sp_64, 0
  ; PIC:   JR64 $at_64 {
  ; PIC:     $sp_64 = DADDiu $sp_64, 16
  ; PIC:   }
  ; PIC: bb.3.if.then:
  ; PIC:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
  ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; PIC:     renamable $v0 = ADDiu $zero, 1
  ; PIC:   }
  ; PIC: bb.4:
  ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; PIC:     renamable $v0 = ADDiu $zero, 0
  ; PIC:   }
  bb.0.entry:
    successors: %bb.1(0x40000000), %bb.2(0x40000000)
    liveins: $a0_64, $a1_64

    renamable $w0 = LDI_B 0
    renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
    renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
    renamable $w0 = SHF_B killed renamable $w0, 27
    renamable $w0 = SHF_W killed renamable $w0, 177
    BZ_B killed renamable $w0, %bb.2, implicit-def dead $at

  bb.1.if.then:
    INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
    renamable $v0 = ADDiu $zero, 1
    PseudoReturn64 undef $ra_64, implicit killed $v0

  bb.2:
    renamable $v0 = ADDiu $zero, 0
    PseudoReturn64 undef $ra_64, implicit killed $v0

...
---
name:            _Z5bz_16Dv8_s
alignment:       3
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
registers:
liveins:
  - { reg: '$a0_64', virtual-reg: '' }
  - { reg: '$a1_64', virtual-reg: '' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    1
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:
stack:
constants:
body:             |
  ; MSA-LABEL: name: _Z5bz_16Dv8_s
  ; MSA: bb.0.entry:
  ; MSA:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; MSA:   renamable $w0 = LDI_B 0
  ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
  ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
  ; MSA:   renamable $w0 = SHF_H killed renamable $w0, 27
  ; MSA:   BNZ_H $w0, %bb.2, implicit-def $at {
  ; MSA:     NOP
  ; MSA:   }
  ; MSA: bb.1.entry:
  ; MSA:   successors: %bb.3(0x80000000)
  ; MSA:   J %bb.3, implicit-def $at {
  ; MSA:     NOP
  ; MSA:   }
  ; MSA: bb.2.if.then:
  ; MSA:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
  ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; MSA:     renamable $v0 = ADDiu $zero, 1
  ; MSA:   }
  ; MSA: bb.3:
  ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; MSA:     renamable $v0 = ADDiu $zero, 0
  ; MSA:   }
  ; PIC-LABEL: name: _Z5bz_16Dv8_s
  ; PIC: bb.0.entry:
  ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
  ; PIC:   renamable $w0 = LDI_B 0
  ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
  ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
  ; PIC:   renamable $w0 = SHF_H killed renamable $w0, 27
  ; PIC:   BNZ_H $w0, %bb.3, implicit-def $at {
  ; PIC:     NOP
  ; PIC:   }
  ; PIC: bb.1.entry:
  ; PIC:   successors: %bb.2(0x80000000)
  ; PIC:   $sp_64 = DADDiu $sp_64, -16
  ; PIC:   SD $ra_64, $sp_64, 0
  ; PIC:   $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
  ; PIC:   $at_64 = DSLL $at_64, 16
  ; PIC:   BAL_BR %bb.2, implicit-def $ra {
  ; PIC:     $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
  ; PIC:   }
  ; PIC: bb.2.entry:
  ; PIC:   successors: %bb.4(0x80000000)
  ; PIC:   $at_64 = DADDu $ra_64, $at_64
  ; PIC:   $ra_64 = LD $sp_64, 0
  ; PIC:   JR64 $at_64 {
  ; PIC:     $sp_64 = DADDiu $sp_64, 16
  ; PIC:   }
  ; PIC: bb.3.if.then:
  ; PIC:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
  ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; PIC:     renamable $v0 = ADDiu $zero, 1
  ; PIC:   }
  ; PIC: bb.4:
  ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; PIC:     renamable $v0 = ADDiu $zero, 0
  ; PIC:   }
  bb.0.entry:
    successors: %bb.1(0x40000000), %bb.2(0x40000000)
    liveins: $a0_64, $a1_64

    renamable $w0 = LDI_B 0
    renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
    renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
    renamable $w0 = SHF_H killed renamable $w0, 27
    BZ_H killed renamable $w0, %bb.2, implicit-def dead $at

  bb.1.if.then:
    INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
    renamable $v0 = ADDiu $zero, 1
    PseudoReturn64 undef $ra_64, implicit killed $v0

  bb.2:
    renamable $v0 = ADDiu $zero, 0
    PseudoReturn64 undef $ra_64, implicit killed $v0

...
---
name:            _Z5bz_32Dv4_i
alignment:       3
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
registers:
liveins:
  - { reg: '$a0_64', virtual-reg: '' }
  - { reg: '$a1_64', virtual-reg: '' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    1
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:
stack:
constants:
body:             |
  ; MSA-LABEL: name: _Z5bz_32Dv4_i
  ; MSA: bb.0.entry:
  ; MSA:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; MSA:   renamable $w0 = LDI_B 0
  ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
  ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
  ; MSA:   renamable $w0 = SHF_W killed renamable $w0, 177
  ; MSA:   BNZ_W $w0, %bb.2, implicit-def $at {
  ; MSA:     NOP
  ; MSA:   }
  ; MSA: bb.1.entry:
  ; MSA:   successors: %bb.3(0x80000000)
  ; MSA:   J %bb.3, implicit-def $at {
  ; MSA:     NOP
  ; MSA:   }
  ; MSA: bb.2.if.then:
  ; MSA:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
  ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; MSA:     renamable $v0 = ADDiu $zero, 1
  ; MSA:   }
  ; MSA: bb.3:
  ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; MSA:     renamable $v0 = ADDiu $zero, 0
  ; MSA:   }
  ; PIC-LABEL: name: _Z5bz_32Dv4_i
  ; PIC: bb.0.entry:
  ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
  ; PIC:   renamable $w0 = LDI_B 0
  ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
  ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
  ; PIC:   renamable $w0 = SHF_W killed renamable $w0, 177
  ; PIC:   BNZ_W $w0, %bb.3, implicit-def $at {
  ; PIC:     NOP
  ; PIC:   }
  ; PIC: bb.1.entry:
  ; PIC:   successors: %bb.2(0x80000000)
  ; PIC:   $sp_64 = DADDiu $sp_64, -16
  ; PIC:   SD $ra_64, $sp_64, 0
  ; PIC:   $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
  ; PIC:   $at_64 = DSLL $at_64, 16
  ; PIC:   BAL_BR %bb.2, implicit-def $ra {
  ; PIC:     $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
  ; PIC:   }
  ; PIC: bb.2.entry:
  ; PIC:   successors: %bb.4(0x80000000)
  ; PIC:   $at_64 = DADDu $ra_64, $at_64
  ; PIC:   $ra_64 = LD $sp_64, 0
  ; PIC:   JR64 $at_64 {
  ; PIC:     $sp_64 = DADDiu $sp_64, 16
  ; PIC:   }
  ; PIC: bb.3.if.then:
  ; PIC:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
  ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; PIC:     renamable $v0 = ADDiu $zero, 1
  ; PIC:   }
  ; PIC: bb.4:
  ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; PIC:     renamable $v0 = ADDiu $zero, 0
  ; PIC:   }
  bb.0.entry:
    successors: %bb.1(0x40000000), %bb.2(0x40000000)
    liveins: $a0_64, $a1_64

    renamable $w0 = LDI_B 0
    renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
    renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
    renamable $w0 = SHF_W killed renamable $w0, 177
    BZ_W killed renamable $w0, %bb.2, implicit-def dead $at

  bb.1.if.then:
    INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
    renamable $v0 = ADDiu $zero, 1
    PseudoReturn64 undef $ra_64, implicit killed $v0

  bb.2:
    renamable $v0 = ADDiu $zero, 0
    PseudoReturn64 undef $ra_64, implicit killed $v0

...
---
name:            _Z5bz_64Dv2_x
alignment:       3
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
registers:
liveins:
  - { reg: '$a0_64', virtual-reg: '' }
  - { reg: '$a1_64', virtual-reg: '' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    1
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:
stack:
constants:
body:             |
  ; MSA-LABEL: name: _Z5bz_64Dv2_x
  ; MSA: bb.0.entry:
  ; MSA:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; MSA:   renamable $w0 = LDI_B 0
  ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
  ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
  ; MSA:   BNZ_D $w0, %bb.2, implicit-def $at {
  ; MSA:     NOP
  ; MSA:   }
  ; MSA: bb.1.entry:
  ; MSA:   successors: %bb.3(0x80000000)
  ; MSA:   J %bb.3, implicit-def $at {
  ; MSA:     NOP
  ; MSA:   }
  ; MSA: bb.2.if.then:
  ; MSA:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
  ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; MSA:     renamable $v0 = ADDiu $zero, 1
  ; MSA:   }
  ; MSA: bb.3:
  ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; MSA:     renamable $v0 = ADDiu $zero, 0
  ; MSA:   }
  ; PIC-LABEL: name: _Z5bz_64Dv2_x
  ; PIC: bb.0.entry:
  ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
  ; PIC:   renamable $w0 = LDI_B 0
  ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
  ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
  ; PIC:   BNZ_D $w0, %bb.3, implicit-def $at {
  ; PIC:     NOP
  ; PIC:   }
  ; PIC: bb.1.entry:
  ; PIC:   successors: %bb.2(0x80000000)
  ; PIC:   $sp_64 = DADDiu $sp_64, -16
  ; PIC:   SD $ra_64, $sp_64, 0
  ; PIC:   $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
  ; PIC:   $at_64 = DSLL $at_64, 16
  ; PIC:   BAL_BR %bb.2, implicit-def $ra {
  ; PIC:     $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
  ; PIC:   }
  ; PIC: bb.2.entry:
  ; PIC:   successors: %bb.4(0x80000000)
  ; PIC:   $at_64 = DADDu $ra_64, $at_64
  ; PIC:   $ra_64 = LD $sp_64, 0
  ; PIC:   JR64 $at_64 {
  ; PIC:     $sp_64 = DADDiu $sp_64, 16
  ; PIC:   }
  ; PIC: bb.3.if.then:
  ; PIC:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
  ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; PIC:     renamable $v0 = ADDiu $zero, 1
  ; PIC:   }
  ; PIC: bb.4:
  ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; PIC:     renamable $v0 = ADDiu $zero, 0
  ; PIC:   }
  bb.0.entry:
    successors: %bb.1(0x40000000), %bb.2(0x40000000)
    liveins: $a0_64, $a1_64

    renamable $w0 = LDI_B 0
    renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
    renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
    BZ_D killed renamable $w0, %bb.2, implicit-def dead $at

  bb.1.if.then:
    INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
    renamable $v0 = ADDiu $zero, 1
    PseudoReturn64 undef $ra_64, implicit killed $v0

  bb.2:
    renamable $v0 = ADDiu $zero, 0
    PseudoReturn64 undef $ra_64, implicit killed $v0

...
---
name:            _Z5bz_64_vDv2_x
alignment:       3
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
registers:
liveins:
  - { reg: '$a0_64', virtual-reg: '' }
  - { reg: '$a1_64', virtual-reg: '' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    1
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:
stack:
constants:
body:             |
  ; MSA-LABEL: name: _Z5bz_64_vDv2_x
  ; MSA: bb.0.entry:
  ; MSA:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; MSA:   renamable $w0 = LDI_B 0
  ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
  ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
  ; MSA:   BNZ_V $w0, %bb.2, implicit-def $at {
  ; MSA:     NOP
  ; MSA:   }
  ; MSA: bb.1.entry:
  ; MSA:   successors: %bb.3(0x80000000)
  ; MSA:   J %bb.3, implicit-def $at {
  ; MSA:     NOP
  ; MSA:   }
  ; MSA: bb.2.if.then:
  ; MSA:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
  ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; MSA:     renamable $v0 = ADDiu $zero, 1
  ; MSA:   }
  ; MSA: bb.3:
  ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; MSA:     renamable $v0 = ADDiu $zero, 0
  ; MSA:   }
  ; PIC-LABEL: name: _Z5bz_64_vDv2_x
  ; PIC: bb.0.entry:
  ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
  ; PIC:   renamable $w0 = LDI_B 0
  ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
  ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
  ; PIC:   BNZ_V $w0, %bb.3, implicit-def $at {
  ; PIC:     NOP
  ; PIC:   }
  ; PIC: bb.1.entry:
  ; PIC:   successors: %bb.2(0x80000000)
  ; PIC:   $sp_64 = DADDiu $sp_64, -16
  ; PIC:   SD $ra_64, $sp_64, 0
  ; PIC:   $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
  ; PIC:   $at_64 = DSLL $at_64, 16
  ; PIC:   BAL_BR %bb.2, implicit-def $ra {
  ; PIC:     $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
  ; PIC:   }
  ; PIC: bb.2.entry:
  ; PIC:   successors: %bb.4(0x80000000)
  ; PIC:   $at_64 = DADDu $ra_64, $at_64
  ; PIC:   $ra_64 = LD $sp_64, 0
  ; PIC:   JR64 $at_64 {
  ; PIC:     $sp_64 = DADDiu $sp_64, 16
  ; PIC:   }
  ; PIC: bb.3.if.then:
  ; PIC:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
  ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; PIC:     renamable $v0 = ADDiu $zero, 1
  ; PIC:   }
  ; PIC: bb.4:
  ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; PIC:     renamable $v0 = ADDiu $zero, 0
  ; PIC:   }
  bb.0.entry:
    successors: %bb.1(0x40000000), %bb.2(0x40000000)
    liveins: $a0_64, $a1_64

    renamable $w0 = LDI_B 0
    renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
    renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
    BZ_V killed renamable $w0, %bb.2, implicit-def dead $at

  bb.1.if.then:
    INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
    renamable $v0 = ADDiu $zero, 1
    PseudoReturn64 undef $ra_64, implicit killed $v0

  bb.2:
    renamable $v0 = ADDiu $zero, 0
    PseudoReturn64 undef $ra_64, implicit killed $v0

...
---
name:            _Z5bnz_8Dv16_a
alignment:       3
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
registers:
liveins:
  - { reg: '$a0_64', virtual-reg: '' }
  - { reg: '$a1_64', virtual-reg: '' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    1
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:
stack:
constants:
body:             |
  ; MSA-LABEL: name: _Z5bnz_8Dv16_a
  ; MSA: bb.0.entry:
  ; MSA:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; MSA:   renamable $w0 = LDI_B 0
  ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
  ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
  ; MSA:   renamable $w0 = SHF_B killed renamable $w0, 27
  ; MSA:   renamable $w0 = SHF_W killed renamable $w0, 177
  ; MSA:   BZ_B $w0, %bb.2, implicit-def $at {
  ; MSA:     NOP
  ; MSA:   }
  ; MSA: bb.1.entry:
  ; MSA:   successors: %bb.3(0x80000000)
  ; MSA:   J %bb.3, implicit-def $at {
  ; MSA:     NOP
  ; MSA:   }
  ; MSA: bb.2.if.then:
  ; MSA:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
  ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; MSA:     renamable $v0 = ADDiu $zero, 1
  ; MSA:   }
  ; MSA: bb.3:
  ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; MSA:     renamable $v0 = ADDiu $zero, 0
  ; MSA:   }
  ; PIC-LABEL: name: _Z5bnz_8Dv16_a
  ; PIC: bb.0.entry:
  ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
  ; PIC:   renamable $w0 = LDI_B 0
  ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
  ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
  ; PIC:   renamable $w0 = SHF_B killed renamable $w0, 27
  ; PIC:   renamable $w0 = SHF_W killed renamable $w0, 177
  ; PIC:   BZ_B $w0, %bb.3, implicit-def $at {
  ; PIC:     NOP
  ; PIC:   }
  ; PIC: bb.1.entry:
  ; PIC:   successors: %bb.2(0x80000000)
  ; PIC:   $sp_64 = DADDiu $sp_64, -16
  ; PIC:   SD $ra_64, $sp_64, 0
  ; PIC:   $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
  ; PIC:   $at_64 = DSLL $at_64, 16
  ; PIC:   BAL_BR %bb.2, implicit-def $ra {
  ; PIC:     $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
  ; PIC:   }
  ; PIC: bb.2.entry:
  ; PIC:   successors: %bb.4(0x80000000)
  ; PIC:   $at_64 = DADDu $ra_64, $at_64
  ; PIC:   $ra_64 = LD $sp_64, 0
  ; PIC:   JR64 $at_64 {
  ; PIC:     $sp_64 = DADDiu $sp_64, 16
  ; PIC:   }
  ; PIC: bb.3.if.then:
  ; PIC:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
  ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; PIC:     renamable $v0 = ADDiu $zero, 1
  ; PIC:   }
  ; PIC: bb.4:
  ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; PIC:     renamable $v0 = ADDiu $zero, 0
  ; PIC:   }
  bb.0.entry:
    successors: %bb.1(0x40000000), %bb.2(0x40000000)
    liveins: $a0_64, $a1_64

    renamable $w0 = LDI_B 0
    renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
    renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
    renamable $w0 = SHF_B killed renamable $w0, 27
    renamable $w0 = SHF_W killed renamable $w0, 177
    BNZ_B killed renamable $w0, %bb.2, implicit-def dead $at

  bb.1.if.then:
    INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
    renamable $v0 = ADDiu $zero, 1
    PseudoReturn64 undef $ra_64, implicit killed $v0

  bb.2:
    renamable $v0 = ADDiu $zero, 0
    PseudoReturn64 undef $ra_64, implicit killed $v0

...
---
name:            _Z6bnz_16Dv8_s
alignment:       3
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
registers:
liveins:
  - { reg: '$a0_64', virtual-reg: '' }
  - { reg: '$a1_64', virtual-reg: '' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    1
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:
stack:
constants:
body:             |
  ; MSA-LABEL: name: _Z6bnz_16Dv8_s
  ; MSA: bb.0.entry:
  ; MSA:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; MSA:   renamable $w0 = LDI_B 0
  ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
  ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
  ; MSA:   renamable $w0 = SHF_H killed renamable $w0, 27
  ; MSA:   BZ_H $w0, %bb.2, implicit-def $at {
  ; MSA:     NOP
  ; MSA:   }
  ; MSA: bb.1.entry:
  ; MSA:   successors: %bb.3(0x80000000)
  ; MSA:   J %bb.3, implicit-def $at {
  ; MSA:     NOP
  ; MSA:   }
  ; MSA: bb.2.if.then:
  ; MSA:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
  ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; MSA:     renamable $v0 = ADDiu $zero, 1
  ; MSA:   }
  ; MSA: bb.3:
  ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; MSA:     renamable $v0 = ADDiu $zero, 0
  ; MSA:   }
  ; PIC-LABEL: name: _Z6bnz_16Dv8_s
  ; PIC: bb.0.entry:
  ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
  ; PIC:   renamable $w0 = LDI_B 0
  ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
  ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
  ; PIC:   renamable $w0 = SHF_H killed renamable $w0, 27
  ; PIC:   BZ_H $w0, %bb.3, implicit-def $at {
  ; PIC:     NOP
  ; PIC:   }
  ; PIC: bb.1.entry:
  ; PIC:   successors: %bb.2(0x80000000)
  ; PIC:   $sp_64 = DADDiu $sp_64, -16
  ; PIC:   SD $ra_64, $sp_64, 0
  ; PIC:   $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
  ; PIC:   $at_64 = DSLL $at_64, 16
  ; PIC:   BAL_BR %bb.2, implicit-def $ra {
  ; PIC:     $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
  ; PIC:   }
  ; PIC: bb.2.entry:
  ; PIC:   successors: %bb.4(0x80000000)
  ; PIC:   $at_64 = DADDu $ra_64, $at_64
  ; PIC:   $ra_64 = LD $sp_64, 0
  ; PIC:   JR64 $at_64 {
  ; PIC:     $sp_64 = DADDiu $sp_64, 16
  ; PIC:   }
  ; PIC: bb.3.if.then:
  ; PIC:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
  ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; PIC:     renamable $v0 = ADDiu $zero, 1
  ; PIC:   }
  ; PIC: bb.4:
  ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; PIC:     renamable $v0 = ADDiu $zero, 0
  ; PIC:   }
  bb.0.entry:
    successors: %bb.1(0x40000000), %bb.2(0x40000000)
    liveins: $a0_64, $a1_64

    renamable $w0 = LDI_B 0
    renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
    renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
    renamable $w0 = SHF_H killed renamable $w0, 27
    BNZ_H killed renamable $w0, %bb.2, implicit-def dead $at

  bb.1.if.then:
    INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
    renamable $v0 = ADDiu $zero, 1
    PseudoReturn64 undef $ra_64, implicit killed $v0

  bb.2:
    renamable $v0 = ADDiu $zero, 0
    PseudoReturn64 undef $ra_64, implicit killed $v0

...
---
name:            _Z6bnz_32Dv4_i
alignment:       3
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
registers:
liveins:
  - { reg: '$a0_64', virtual-reg: '' }
  - { reg: '$a1_64', virtual-reg: '' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    1
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:
stack:
constants:
body:             |
  ; MSA-LABEL: name: _Z6bnz_32Dv4_i
  ; MSA: bb.0.entry:
  ; MSA:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; MSA:   renamable $w0 = LDI_B 0
  ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
  ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
  ; MSA:   renamable $w0 = SHF_W killed renamable $w0, 177
  ; MSA:   BZ_W $w0, %bb.2, implicit-def $at {
  ; MSA:     NOP
  ; MSA:   }
  ; MSA: bb.1.entry:
  ; MSA:   successors: %bb.3(0x80000000)
  ; MSA:   J %bb.3, implicit-def $at {
  ; MSA:     NOP
  ; MSA:   }
  ; MSA: bb.2.if.then:
  ; MSA:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
  ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; MSA:     renamable $v0 = ADDiu $zero, 1
  ; MSA:   }
  ; MSA: bb.3:
  ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; MSA:     renamable $v0 = ADDiu $zero, 0
  ; MSA:   }
  ; PIC-LABEL: name: _Z6bnz_32Dv4_i
  ; PIC: bb.0.entry:
  ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
  ; PIC:   renamable $w0 = LDI_B 0
  ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
  ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
  ; PIC:   renamable $w0 = SHF_W killed renamable $w0, 177
  ; PIC:   BZ_W $w0, %bb.3, implicit-def $at {
  ; PIC:     NOP
  ; PIC:   }
  ; PIC: bb.1.entry:
  ; PIC:   successors: %bb.2(0x80000000)
  ; PIC:   $sp_64 = DADDiu $sp_64, -16
  ; PIC:   SD $ra_64, $sp_64, 0
  ; PIC:   $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
  ; PIC:   $at_64 = DSLL $at_64, 16
  ; PIC:   BAL_BR %bb.2, implicit-def $ra {
  ; PIC:     $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
  ; PIC:   }
  ; PIC: bb.2.entry:
  ; PIC:   successors: %bb.4(0x80000000)
  ; PIC:   $at_64 = DADDu $ra_64, $at_64
  ; PIC:   $ra_64 = LD $sp_64, 0
  ; PIC:   JR64 $at_64 {
  ; PIC:     $sp_64 = DADDiu $sp_64, 16
  ; PIC:   }
  ; PIC: bb.3.if.then:
  ; PIC:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
  ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; PIC:     renamable $v0 = ADDiu $zero, 1
  ; PIC:   }
  ; PIC: bb.4:
  ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; PIC:     renamable $v0 = ADDiu $zero, 0
  ; PIC:   }
  bb.0.entry:
    successors: %bb.1(0x40000000), %bb.2(0x40000000)
    liveins: $a0_64, $a1_64

    renamable $w0 = LDI_B 0
    renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
    renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
    renamable $w0 = SHF_W killed renamable $w0, 177
    BNZ_W killed renamable $w0, %bb.2, implicit-def dead $at

  bb.1.if.then:
    INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
    renamable $v0 = ADDiu $zero, 1
    PseudoReturn64 undef $ra_64, implicit killed $v0

  bb.2:
    renamable $v0 = ADDiu $zero, 0
    PseudoReturn64 undef $ra_64, implicit killed $v0

...
---
name:            _Z6bnz_64Dv2_x
alignment:       3
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
registers:
liveins:
  - { reg: '$a0_64', virtual-reg: '' }
  - { reg: '$a1_64', virtual-reg: '' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    1
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:
stack:
constants:
body:             |
  ; MSA-LABEL: name: _Z6bnz_64Dv2_x
  ; MSA: bb.0.entry:
  ; MSA:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; MSA:   renamable $w0 = LDI_B 0
  ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
  ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
  ; MSA:   BZ_D $w0, %bb.2, implicit-def $at {
  ; MSA:     NOP
  ; MSA:   }
  ; MSA: bb.1.entry:
  ; MSA:   successors: %bb.3(0x80000000)
  ; MSA:   J %bb.3, implicit-def $at {
  ; MSA:     NOP
  ; MSA:   }
  ; MSA: bb.2.if.then:
  ; MSA:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
  ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; MSA:     renamable $v0 = ADDiu $zero, 1
  ; MSA:   }
  ; MSA: bb.3:
  ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; MSA:     renamable $v0 = ADDiu $zero, 0
  ; MSA:   }
  ; PIC-LABEL: name: _Z6bnz_64Dv2_x
  ; PIC: bb.0.entry:
  ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
  ; PIC:   renamable $w0 = LDI_B 0
  ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
  ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
  ; PIC:   BZ_D $w0, %bb.3, implicit-def $at {
  ; PIC:     NOP
  ; PIC:   }
  ; PIC: bb.1.entry:
  ; PIC:   successors: %bb.2(0x80000000)
  ; PIC:   $sp_64 = DADDiu $sp_64, -16
  ; PIC:   SD $ra_64, $sp_64, 0
  ; PIC:   $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
  ; PIC:   $at_64 = DSLL $at_64, 16
  ; PIC:   BAL_BR %bb.2, implicit-def $ra {
  ; PIC:     $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
  ; PIC:   }
  ; PIC: bb.2.entry:
  ; PIC:   successors: %bb.4(0x80000000)
  ; PIC:   $at_64 = DADDu $ra_64, $at_64
  ; PIC:   $ra_64 = LD $sp_64, 0
  ; PIC:   JR64 $at_64 {
  ; PIC:     $sp_64 = DADDiu $sp_64, 16
  ; PIC:   }
  ; PIC: bb.3.if.then:
  ; PIC:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
  ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; PIC:     renamable $v0 = ADDiu $zero, 1
  ; PIC:   }
  ; PIC: bb.4:
  ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; PIC:     renamable $v0 = ADDiu $zero, 0
  ; PIC:   }
  bb.0.entry:
    successors: %bb.1(0x40000000), %bb.2(0x40000000)
    liveins: $a0_64, $a1_64

    renamable $w0 = LDI_B 0
    renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
    renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
    BNZ_D killed renamable $w0, %bb.2, implicit-def dead $at

  bb.1.if.then:
    INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
    renamable $v0 = ADDiu $zero, 1
    PseudoReturn64 undef $ra_64, implicit killed $v0

  bb.2:
    renamable $v0 = ADDiu $zero, 0
    PseudoReturn64 undef $ra_64, implicit killed $v0

...
---
name:            _Z6bnz_64_vDv2_x
alignment:       3
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
registers:
liveins:
  - { reg: '$a0_64', virtual-reg: '' }
  - { reg: '$a1_64', virtual-reg: '' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    1
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:
stack:
constants:
body:             |
  ; MSA-LABEL: name: _Z6bnz_64_vDv2_x
  ; MSA: bb.0.entry:
  ; MSA:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; MSA:   renamable $w0 = LDI_B 0
  ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
  ; MSA:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
  ; MSA:   BZ_V $w0, %bb.2, implicit-def $at {
  ; MSA:     NOP
  ; MSA:   }
  ; MSA: bb.1.entry:
  ; MSA:   successors: %bb.3(0x80000000)
  ; MSA:   J %bb.3, implicit-def $at {
  ; MSA:     NOP
  ; MSA:   }
  ; MSA: bb.2.if.then:
  ; MSA:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
  ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; MSA:     renamable $v0 = ADDiu $zero, 1
  ; MSA:   }
  ; MSA: bb.3:
  ; MSA:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; MSA:     renamable $v0 = ADDiu $zero, 0
  ; MSA:   }
  ; PIC-LABEL: name: _Z6bnz_64_vDv2_x
  ; PIC: bb.0.entry:
  ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
  ; PIC:   renamable $w0 = LDI_B 0
  ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
  ; PIC:   renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
  ; PIC:   BZ_V $w0, %bb.3, implicit-def $at {
  ; PIC:     NOP
  ; PIC:   }
  ; PIC: bb.1.entry:
  ; PIC:   successors: %bb.2(0x80000000)
  ; PIC:   $sp_64 = DADDiu $sp_64, -16
  ; PIC:   SD $ra_64, $sp_64, 0
  ; PIC:   $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
  ; PIC:   $at_64 = DSLL $at_64, 16
  ; PIC:   BAL_BR %bb.2, implicit-def $ra {
  ; PIC:     $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
  ; PIC:   }
  ; PIC: bb.2.entry:
  ; PIC:   successors: %bb.4(0x80000000)
  ; PIC:   $at_64 = DADDu $ra_64, $at_64
  ; PIC:   $ra_64 = LD $sp_64, 0
  ; PIC:   JR64 $at_64 {
  ; PIC:     $sp_64 = DADDiu $sp_64, 16
  ; PIC:   }
  ; PIC: bb.3.if.then:
  ; PIC:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
  ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; PIC:     renamable $v0 = ADDiu $zero, 1
  ; PIC:   }
  ; PIC: bb.4:
  ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0 {
  ; PIC:     renamable $v0 = ADDiu $zero, 0
  ; PIC:   }
  bb.0.entry:
    successors: %bb.1(0x40000000), %bb.2(0x40000000)
    liveins: $a0_64, $a1_64

    renamable $w0 = LDI_B 0
    renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0
    renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1
    BNZ_V killed renamable $w0, %bb.2, implicit-def dead $at

  bb.1.if.then:
    INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
    renamable $v0 = ADDiu $zero, 1
    PseudoReturn64 undef $ra_64, implicit killed $v0

  bb.2:
    renamable $v0 = ADDiu $zero, 0
    PseudoReturn64 undef $ra_64, implicit killed $v0

...