)]}' { "commit": "ee57dd49214a7ca74f0b01111bf0ce16d42cecb5", "tree": "b8303681706acf70021efcdd4031e2d292315541", "parents": [ "a461b7a03cde32cd6560dcbcea23ec51dfd1e522" ], "author": { "name": "Petar Avramovic", "email": "Petar.Avramovic@rt-rk.com", "time": "Tue Oct 22 13:51:57 2019 +0000" }, "committer": { "name": "Petar Avramovic", "email": "Petar.Avramovic@rt-rk.com", "time": "Tue Oct 22 13:51:57 2019 +0000" }, "message": "[MIPS GlobalISel] Select MSA vector generic and builtin add\n\nSelect vector G_ADD for MIPS32 with MSA. We have to set bank\nfor vector operands to fprb and selectImpl will do the rest.\n__builtin_msa_addv_\u003cformat\u003e will be transformed into G_ADD\nin legalizeIntrinsic and selected in the same way.\n__builtin_msa_addvi_\u003cformat\u003e will be directly selected into\nADDVI_\u003cformat\u003e in legalizeIntrinsic. MIR tests for it have\nunnecessary additional copies. Capture current state of tests\nwith run-pass\u003dlegalizer with a test in test/CodeGen/MIR/Mips.\n\nDifferential Revision: https://reviews.llvm.org/D68984\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375501 91177308-0d34-0410-b5e6-96231b3b80d8\n", "tree_diff": [ { "type": "modify", "old_id": "96706d3b3966e2760b93bfc1b881695002dedb6f", "old_mode": 33188, "old_path": "lib/Target/Mips/MipsLegalizerInfo.cpp", "new_id": "bb4a1d902d75d093c05759ed7b58dae9846dab2f", "new_mode": 33188, "new_path": "lib/Target/Mips/MipsLegalizerInfo.cpp" }, { "type": "modify", "old_id": "a203ab5081af2185291f40eab8f05ea8d52cb2f7", "old_mode": 33188, "old_path": "lib/Target/Mips/MipsRegisterBankInfo.cpp", "new_id": "d334366e727cd88bf3b1938da8ee4b419a86582b", "new_mode": 33188, "new_path": "lib/Target/Mips/MipsRegisterBankInfo.cpp" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "71329fd45b5d39c016e3bc55b4fc3b0decd3b784", "new_mode": 33188, "new_path": "test/CodeGen/MIR/Mips/setRegClassOrRegBank.ll" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "2645c97095ea3d280f077f36eff906b647b14e96", "new_mode": 33188, "new_path": "test/CodeGen/MIR/Mips/setRegClassOrRegBank.mir" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "6903f01ae5adeccd77bbf459b5f14d2b2e9680bf", "new_mode": 33188, "new_path": "test/CodeGen/Mips/GlobalISel/instruction-select/add_vec.mir" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "d0950ea638f81eebd5a84b6be2db855ed20207f2", "new_mode": 33188, "new_path": "test/CodeGen/Mips/GlobalISel/legalizer/add_vec.mir" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "2e71669bc9d0a9db06f8daf4ca5a95ba491f9c09", "new_mode": 33188, "new_path": "test/CodeGen/Mips/GlobalISel/legalizer/add_vec_builtin.mir" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "5d8585173b995d12f57d4fbe154af12453ddf3e1", "new_mode": 33188, "new_path": "test/CodeGen/Mips/GlobalISel/llvm-ir/add_vec.ll" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "ea05479ce2e8b69cabac36f18f532fcd60893a37", "new_mode": 33188, "new_path": "test/CodeGen/Mips/GlobalISel/llvm-ir/add_vec_builtin.ll" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "59fa2a89bf3dd163bf861aac45f1347ff0b6c43b", "new_mode": 33188, "new_path": "test/CodeGen/Mips/GlobalISel/regbankselect/add_vec.mir" } ] }